1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADC12130/ADC12132/ADC12138 12-bit plus sign ADC driver 4 * 5 * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com> 6 * 7 * Datasheet: http://www.ti.com/lit/ds/symlink/adc12138.pdf 8 */ 9 10 #include <linux/module.h> 11 #include <linux/interrupt.h> 12 #include <linux/completion.h> 13 #include <linux/clk.h> 14 #include <linux/spi/spi.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/buffer.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/regulator/consumer.h> 21 22 #define ADC12138_MODE_AUTO_CAL 0x08 23 #define ADC12138_MODE_READ_STATUS 0x0c 24 #define ADC12138_MODE_ACQUISITION_TIME_6 0x0e 25 #define ADC12138_MODE_ACQUISITION_TIME_10 0x4e 26 #define ADC12138_MODE_ACQUISITION_TIME_18 0x8e 27 #define ADC12138_MODE_ACQUISITION_TIME_34 0xce 28 29 #define ADC12138_STATUS_CAL BIT(6) 30 31 enum { 32 adc12130, 33 adc12132, 34 adc12138, 35 }; 36 37 struct adc12138 { 38 struct spi_device *spi; 39 unsigned int id; 40 /* conversion clock */ 41 struct clk *cclk; 42 /* positive analog voltage reference */ 43 struct regulator *vref_p; 44 /* negative analog voltage reference */ 45 struct regulator *vref_n; 46 struct mutex lock; 47 struct completion complete; 48 /* The number of cclk periods for the S/H's acquisition time */ 49 unsigned int acquisition_time; 50 /* 51 * Maximum size needed: 16x 2 bytes ADC data + 8 bytes timestamp. 52 * Less may be need if not all channels are enabled, as long as 53 * the 8 byte alignment of the timestamp is maintained. 54 */ 55 __be16 data[20] __aligned(8); 56 57 u8 tx_buf[2] ____cacheline_aligned; 58 u8 rx_buf[2]; 59 }; 60 61 #define ADC12138_VOLTAGE_CHANNEL(chan) \ 62 { \ 63 .type = IIO_VOLTAGE, \ 64 .indexed = 1, \ 65 .channel = chan, \ 66 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 67 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ 68 | BIT(IIO_CHAN_INFO_OFFSET), \ 69 .scan_index = chan, \ 70 .scan_type = { \ 71 .sign = 's', \ 72 .realbits = 13, \ 73 .storagebits = 16, \ 74 .shift = 3, \ 75 .endianness = IIO_BE, \ 76 }, \ 77 } 78 79 #define ADC12138_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \ 80 { \ 81 .type = IIO_VOLTAGE, \ 82 .indexed = 1, \ 83 .channel = (chan1), \ 84 .channel2 = (chan2), \ 85 .differential = 1, \ 86 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 87 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ 88 | BIT(IIO_CHAN_INFO_OFFSET), \ 89 .scan_index = si, \ 90 .scan_type = { \ 91 .sign = 's', \ 92 .realbits = 13, \ 93 .storagebits = 16, \ 94 .shift = 3, \ 95 .endianness = IIO_BE, \ 96 }, \ 97 } 98 99 static const struct iio_chan_spec adc12132_channels[] = { 100 ADC12138_VOLTAGE_CHANNEL(0), 101 ADC12138_VOLTAGE_CHANNEL(1), 102 ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 2), 103 ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 3), 104 IIO_CHAN_SOFT_TIMESTAMP(4), 105 }; 106 107 static const struct iio_chan_spec adc12138_channels[] = { 108 ADC12138_VOLTAGE_CHANNEL(0), 109 ADC12138_VOLTAGE_CHANNEL(1), 110 ADC12138_VOLTAGE_CHANNEL(2), 111 ADC12138_VOLTAGE_CHANNEL(3), 112 ADC12138_VOLTAGE_CHANNEL(4), 113 ADC12138_VOLTAGE_CHANNEL(5), 114 ADC12138_VOLTAGE_CHANNEL(6), 115 ADC12138_VOLTAGE_CHANNEL(7), 116 ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 8), 117 ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 9), 118 ADC12138_VOLTAGE_CHANNEL_DIFF(2, 3, 10), 119 ADC12138_VOLTAGE_CHANNEL_DIFF(3, 2, 11), 120 ADC12138_VOLTAGE_CHANNEL_DIFF(4, 5, 12), 121 ADC12138_VOLTAGE_CHANNEL_DIFF(5, 4, 13), 122 ADC12138_VOLTAGE_CHANNEL_DIFF(6, 7, 14), 123 ADC12138_VOLTAGE_CHANNEL_DIFF(7, 6, 15), 124 IIO_CHAN_SOFT_TIMESTAMP(16), 125 }; 126 127 static int adc12138_mode_programming(struct adc12138 *adc, u8 mode, 128 void *rx_buf, int len) 129 { 130 struct spi_transfer xfer = { 131 .tx_buf = adc->tx_buf, 132 .rx_buf = adc->rx_buf, 133 .len = len, 134 }; 135 int ret; 136 137 /* Skip unused bits for ADC12130 and ADC12132 */ 138 if (adc->id != adc12138) 139 mode = (mode & 0xc0) | ((mode & 0x0f) << 2); 140 141 adc->tx_buf[0] = mode; 142 143 ret = spi_sync_transfer(adc->spi, &xfer, 1); 144 if (ret) 145 return ret; 146 147 memcpy(rx_buf, adc->rx_buf, len); 148 149 return 0; 150 } 151 152 static int adc12138_read_status(struct adc12138 *adc) 153 { 154 u8 rx_buf[2]; 155 int ret; 156 157 ret = adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS, 158 rx_buf, 2); 159 if (ret) 160 return ret; 161 162 return (rx_buf[0] << 1) | (rx_buf[1] >> 7); 163 } 164 165 static int __adc12138_start_conv(struct adc12138 *adc, 166 struct iio_chan_spec const *channel, 167 void *data, int len) 168 169 { 170 static const u8 ch_to_mux[] = { 0, 4, 1, 5, 2, 6, 3, 7 }; 171 u8 mode = (ch_to_mux[channel->channel] << 4) | 172 (channel->differential ? 0 : 0x80); 173 174 return adc12138_mode_programming(adc, mode, data, len); 175 } 176 177 static int adc12138_start_conv(struct adc12138 *adc, 178 struct iio_chan_spec const *channel) 179 { 180 u8 trash; 181 182 return __adc12138_start_conv(adc, channel, &trash, 1); 183 } 184 185 static int adc12138_start_and_read_conv(struct adc12138 *adc, 186 struct iio_chan_spec const *channel, 187 __be16 *data) 188 { 189 return __adc12138_start_conv(adc, channel, data, 2); 190 } 191 192 static int adc12138_read_conv_data(struct adc12138 *adc, __be16 *value) 193 { 194 /* Issue a read status instruction and read previous conversion data */ 195 return adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS, 196 value, sizeof(*value)); 197 } 198 199 static int adc12138_wait_eoc(struct adc12138 *adc, unsigned long timeout) 200 { 201 if (!wait_for_completion_timeout(&adc->complete, timeout)) 202 return -ETIMEDOUT; 203 204 return 0; 205 } 206 207 static int adc12138_adc_conversion(struct adc12138 *adc, 208 struct iio_chan_spec const *channel, 209 __be16 *value) 210 { 211 int ret; 212 213 reinit_completion(&adc->complete); 214 215 ret = adc12138_start_conv(adc, channel); 216 if (ret) 217 return ret; 218 219 ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100)); 220 if (ret) 221 return ret; 222 223 return adc12138_read_conv_data(adc, value); 224 } 225 226 static int adc12138_read_raw(struct iio_dev *iio, 227 struct iio_chan_spec const *channel, int *value, 228 int *shift, long mask) 229 { 230 struct adc12138 *adc = iio_priv(iio); 231 int ret; 232 __be16 data; 233 234 switch (mask) { 235 case IIO_CHAN_INFO_RAW: 236 mutex_lock(&adc->lock); 237 ret = adc12138_adc_conversion(adc, channel, &data); 238 mutex_unlock(&adc->lock); 239 if (ret) 240 return ret; 241 242 *value = sign_extend32(be16_to_cpu(data) >> 3, 12); 243 244 return IIO_VAL_INT; 245 case IIO_CHAN_INFO_SCALE: 246 ret = regulator_get_voltage(adc->vref_p); 247 if (ret < 0) 248 return ret; 249 *value = ret; 250 251 if (!IS_ERR(adc->vref_n)) { 252 ret = regulator_get_voltage(adc->vref_n); 253 if (ret < 0) 254 return ret; 255 *value -= ret; 256 } 257 258 /* convert regulator output voltage to mV */ 259 *value /= 1000; 260 *shift = channel->scan_type.realbits - 1; 261 262 return IIO_VAL_FRACTIONAL_LOG2; 263 case IIO_CHAN_INFO_OFFSET: 264 if (!IS_ERR(adc->vref_n)) { 265 *value = regulator_get_voltage(adc->vref_n); 266 if (*value < 0) 267 return *value; 268 } else { 269 *value = 0; 270 } 271 272 /* convert regulator output voltage to mV */ 273 *value /= 1000; 274 275 return IIO_VAL_INT; 276 } 277 278 return -EINVAL; 279 } 280 281 static const struct iio_info adc12138_info = { 282 .read_raw = adc12138_read_raw, 283 }; 284 285 static int adc12138_init(struct adc12138 *adc) 286 { 287 int ret; 288 int status; 289 u8 mode; 290 u8 trash; 291 292 reinit_completion(&adc->complete); 293 294 ret = adc12138_mode_programming(adc, ADC12138_MODE_AUTO_CAL, &trash, 1); 295 if (ret) 296 return ret; 297 298 /* data output at this time has no significance */ 299 status = adc12138_read_status(adc); 300 if (status < 0) 301 return status; 302 303 adc12138_wait_eoc(adc, msecs_to_jiffies(100)); 304 305 status = adc12138_read_status(adc); 306 if (status & ADC12138_STATUS_CAL) { 307 dev_warn(&adc->spi->dev, 308 "Auto Cal sequence is still in progress: %#x\n", 309 status); 310 return -EIO; 311 } 312 313 switch (adc->acquisition_time) { 314 case 6: 315 mode = ADC12138_MODE_ACQUISITION_TIME_6; 316 break; 317 case 10: 318 mode = ADC12138_MODE_ACQUISITION_TIME_10; 319 break; 320 case 18: 321 mode = ADC12138_MODE_ACQUISITION_TIME_18; 322 break; 323 case 34: 324 mode = ADC12138_MODE_ACQUISITION_TIME_34; 325 break; 326 default: 327 return -EINVAL; 328 } 329 330 return adc12138_mode_programming(adc, mode, &trash, 1); 331 } 332 333 static irqreturn_t adc12138_trigger_handler(int irq, void *p) 334 { 335 struct iio_poll_func *pf = p; 336 struct iio_dev *indio_dev = pf->indio_dev; 337 struct adc12138 *adc = iio_priv(indio_dev); 338 __be16 trash; 339 int ret; 340 int scan_index; 341 int i = 0; 342 343 mutex_lock(&adc->lock); 344 345 for_each_set_bit(scan_index, indio_dev->active_scan_mask, 346 indio_dev->masklength) { 347 const struct iio_chan_spec *scan_chan = 348 &indio_dev->channels[scan_index]; 349 350 reinit_completion(&adc->complete); 351 352 ret = adc12138_start_and_read_conv(adc, scan_chan, 353 i ? &adc->data[i - 1] : &trash); 354 if (ret) { 355 dev_warn(&adc->spi->dev, 356 "failed to start conversion\n"); 357 goto out; 358 } 359 360 ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100)); 361 if (ret) { 362 dev_warn(&adc->spi->dev, "wait eoc timeout\n"); 363 goto out; 364 } 365 366 i++; 367 } 368 369 if (i) { 370 ret = adc12138_read_conv_data(adc, &adc->data[i - 1]); 371 if (ret) { 372 dev_warn(&adc->spi->dev, 373 "failed to get conversion data\n"); 374 goto out; 375 } 376 } 377 378 iio_push_to_buffers_with_timestamp(indio_dev, adc->data, 379 iio_get_time_ns(indio_dev)); 380 out: 381 mutex_unlock(&adc->lock); 382 383 iio_trigger_notify_done(indio_dev->trig); 384 385 return IRQ_HANDLED; 386 } 387 388 static irqreturn_t adc12138_eoc_handler(int irq, void *p) 389 { 390 struct iio_dev *indio_dev = p; 391 struct adc12138 *adc = iio_priv(indio_dev); 392 393 complete(&adc->complete); 394 395 return IRQ_HANDLED; 396 } 397 398 static int adc12138_probe(struct spi_device *spi) 399 { 400 struct iio_dev *indio_dev; 401 struct adc12138 *adc; 402 int ret; 403 404 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); 405 if (!indio_dev) 406 return -ENOMEM; 407 408 adc = iio_priv(indio_dev); 409 adc->spi = spi; 410 adc->id = spi_get_device_id(spi)->driver_data; 411 mutex_init(&adc->lock); 412 init_completion(&adc->complete); 413 414 indio_dev->name = spi_get_device_id(spi)->name; 415 indio_dev->info = &adc12138_info; 416 indio_dev->modes = INDIO_DIRECT_MODE; 417 418 switch (adc->id) { 419 case adc12130: 420 case adc12132: 421 indio_dev->channels = adc12132_channels; 422 indio_dev->num_channels = ARRAY_SIZE(adc12132_channels); 423 break; 424 case adc12138: 425 indio_dev->channels = adc12138_channels; 426 indio_dev->num_channels = ARRAY_SIZE(adc12138_channels); 427 break; 428 default: 429 return -EINVAL; 430 } 431 432 ret = of_property_read_u32(spi->dev.of_node, "ti,acquisition-time", 433 &adc->acquisition_time); 434 if (ret) 435 adc->acquisition_time = 10; 436 437 adc->cclk = devm_clk_get(&spi->dev, NULL); 438 if (IS_ERR(adc->cclk)) 439 return PTR_ERR(adc->cclk); 440 441 adc->vref_p = devm_regulator_get(&spi->dev, "vref-p"); 442 if (IS_ERR(adc->vref_p)) 443 return PTR_ERR(adc->vref_p); 444 445 adc->vref_n = devm_regulator_get_optional(&spi->dev, "vref-n"); 446 if (IS_ERR(adc->vref_n)) { 447 /* 448 * Assume vref_n is 0V if an optional regulator is not 449 * specified, otherwise return the error code. 450 */ 451 ret = PTR_ERR(adc->vref_n); 452 if (ret != -ENODEV) 453 return ret; 454 } 455 456 ret = devm_request_irq(&spi->dev, spi->irq, adc12138_eoc_handler, 457 IRQF_TRIGGER_RISING, indio_dev->name, indio_dev); 458 if (ret) 459 return ret; 460 461 ret = clk_prepare_enable(adc->cclk); 462 if (ret) 463 return ret; 464 465 ret = regulator_enable(adc->vref_p); 466 if (ret) 467 goto err_clk_disable; 468 469 if (!IS_ERR(adc->vref_n)) { 470 ret = regulator_enable(adc->vref_n); 471 if (ret) 472 goto err_vref_p_disable; 473 } 474 475 ret = adc12138_init(adc); 476 if (ret) 477 goto err_vref_n_disable; 478 479 spi_set_drvdata(spi, indio_dev); 480 481 ret = iio_triggered_buffer_setup(indio_dev, NULL, 482 adc12138_trigger_handler, NULL); 483 if (ret) 484 goto err_vref_n_disable; 485 486 ret = iio_device_register(indio_dev); 487 if (ret) 488 goto err_buffer_cleanup; 489 490 return 0; 491 err_buffer_cleanup: 492 iio_triggered_buffer_cleanup(indio_dev); 493 err_vref_n_disable: 494 if (!IS_ERR(adc->vref_n)) 495 regulator_disable(adc->vref_n); 496 err_vref_p_disable: 497 regulator_disable(adc->vref_p); 498 err_clk_disable: 499 clk_disable_unprepare(adc->cclk); 500 501 return ret; 502 } 503 504 static int adc12138_remove(struct spi_device *spi) 505 { 506 struct iio_dev *indio_dev = spi_get_drvdata(spi); 507 struct adc12138 *adc = iio_priv(indio_dev); 508 509 iio_device_unregister(indio_dev); 510 iio_triggered_buffer_cleanup(indio_dev); 511 if (!IS_ERR(adc->vref_n)) 512 regulator_disable(adc->vref_n); 513 regulator_disable(adc->vref_p); 514 clk_disable_unprepare(adc->cclk); 515 516 return 0; 517 } 518 519 #ifdef CONFIG_OF 520 521 static const struct of_device_id adc12138_dt_ids[] = { 522 { .compatible = "ti,adc12130", }, 523 { .compatible = "ti,adc12132", }, 524 { .compatible = "ti,adc12138", }, 525 {} 526 }; 527 MODULE_DEVICE_TABLE(of, adc12138_dt_ids); 528 529 #endif 530 531 static const struct spi_device_id adc12138_id[] = { 532 { "adc12130", adc12130 }, 533 { "adc12132", adc12132 }, 534 { "adc12138", adc12138 }, 535 {} 536 }; 537 MODULE_DEVICE_TABLE(spi, adc12138_id); 538 539 static struct spi_driver adc12138_driver = { 540 .driver = { 541 .name = "adc12138", 542 .of_match_table = of_match_ptr(adc12138_dt_ids), 543 }, 544 .probe = adc12138_probe, 545 .remove = adc12138_remove, 546 .id_table = adc12138_id, 547 }; 548 module_spi_driver(adc12138_driver); 549 550 MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>"); 551 MODULE_DESCRIPTION("ADC12130/ADC12132/ADC12138 driver"); 552 MODULE_LICENSE("GPL v2"); 553