136edc939SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2efc945fbSAkinobu Mita /*
3efc945fbSAkinobu Mita * ADC0831/ADC0832/ADC0834/ADC0838 8-bit ADC driver
4efc945fbSAkinobu Mita *
5efc945fbSAkinobu Mita * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
6efc945fbSAkinobu Mita *
73593cd53SAlexander A. Klimov * Datasheet: https://www.ti.com/lit/ds/symlink/adc0832-n.pdf
8efc945fbSAkinobu Mita */
9efc945fbSAkinobu Mita
10efc945fbSAkinobu Mita #include <linux/module.h>
110896ffddSJonathan Cameron #include <linux/mod_devicetable.h>
12efc945fbSAkinobu Mita #include <linux/spi/spi.h>
13efc945fbSAkinobu Mita #include <linux/iio/iio.h>
14efc945fbSAkinobu Mita #include <linux/regulator/consumer.h>
15815bbc87SAkinobu Mita #include <linux/iio/buffer.h>
16815bbc87SAkinobu Mita #include <linux/iio/trigger.h>
17815bbc87SAkinobu Mita #include <linux/iio/triggered_buffer.h>
18815bbc87SAkinobu Mita #include <linux/iio/trigger_consumer.h>
19efc945fbSAkinobu Mita
20efc945fbSAkinobu Mita enum {
21efc945fbSAkinobu Mita adc0831,
22efc945fbSAkinobu Mita adc0832,
23efc945fbSAkinobu Mita adc0834,
24efc945fbSAkinobu Mita adc0838,
25efc945fbSAkinobu Mita };
26efc945fbSAkinobu Mita
27efc945fbSAkinobu Mita struct adc0832 {
28efc945fbSAkinobu Mita struct spi_device *spi;
29efc945fbSAkinobu Mita struct regulator *reg;
30efc945fbSAkinobu Mita struct mutex lock;
31efc945fbSAkinobu Mita u8 mux_bits;
3239e91f3bSJonathan Cameron /*
3339e91f3bSJonathan Cameron * Max size needed: 16x 1 byte ADC data + 8 bytes timestamp
3439e91f3bSJonathan Cameron * May be shorter if not all channels are enabled subject
3539e91f3bSJonathan Cameron * to the timestamp remaining 8 byte aligned.
3639e91f3bSJonathan Cameron */
3739e91f3bSJonathan Cameron u8 data[24] __aligned(8);
38efc945fbSAkinobu Mita
39*1e6bb81cSJonathan Cameron u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN);
40efc945fbSAkinobu Mita u8 rx_buf[2];
41efc945fbSAkinobu Mita };
42efc945fbSAkinobu Mita
43efc945fbSAkinobu Mita #define ADC0832_VOLTAGE_CHANNEL(chan) \
44efc945fbSAkinobu Mita { \
45efc945fbSAkinobu Mita .type = IIO_VOLTAGE, \
46efc945fbSAkinobu Mita .indexed = 1, \
47efc945fbSAkinobu Mita .channel = chan, \
48efc945fbSAkinobu Mita .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
49815bbc87SAkinobu Mita .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
50815bbc87SAkinobu Mita .scan_index = chan, \
51815bbc87SAkinobu Mita .scan_type = { \
52815bbc87SAkinobu Mita .sign = 'u', \
53815bbc87SAkinobu Mita .realbits = 8, \
54815bbc87SAkinobu Mita .storagebits = 8, \
55815bbc87SAkinobu Mita }, \
56efc945fbSAkinobu Mita }
57efc945fbSAkinobu Mita
58815bbc87SAkinobu Mita #define ADC0832_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \
59efc945fbSAkinobu Mita { \
60efc945fbSAkinobu Mita .type = IIO_VOLTAGE, \
61efc945fbSAkinobu Mita .indexed = 1, \
62efc945fbSAkinobu Mita .channel = (chan1), \
63efc945fbSAkinobu Mita .channel2 = (chan2), \
64efc945fbSAkinobu Mita .differential = 1, \
65efc945fbSAkinobu Mita .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
66815bbc87SAkinobu Mita .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
67815bbc87SAkinobu Mita .scan_index = si, \
68815bbc87SAkinobu Mita .scan_type = { \
69815bbc87SAkinobu Mita .sign = 'u', \
70815bbc87SAkinobu Mita .realbits = 8, \
71815bbc87SAkinobu Mita .storagebits = 8, \
72815bbc87SAkinobu Mita }, \
73efc945fbSAkinobu Mita }
74efc945fbSAkinobu Mita
75efc945fbSAkinobu Mita static const struct iio_chan_spec adc0831_channels[] = {
76815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 0),
77815bbc87SAkinobu Mita IIO_CHAN_SOFT_TIMESTAMP(1),
78efc945fbSAkinobu Mita };
79efc945fbSAkinobu Mita
80efc945fbSAkinobu Mita static const struct iio_chan_spec adc0832_channels[] = {
81efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(0),
82efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(1),
83815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 2),
84815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 3),
85815bbc87SAkinobu Mita IIO_CHAN_SOFT_TIMESTAMP(4),
86efc945fbSAkinobu Mita };
87efc945fbSAkinobu Mita
88efc945fbSAkinobu Mita static const struct iio_chan_spec adc0834_channels[] = {
89efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(0),
90efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(1),
91efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(2),
92efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(3),
93815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 4),
94815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 5),
95815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3, 6),
96815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2, 7),
97815bbc87SAkinobu Mita IIO_CHAN_SOFT_TIMESTAMP(8),
98efc945fbSAkinobu Mita };
99efc945fbSAkinobu Mita
100efc945fbSAkinobu Mita static const struct iio_chan_spec adc0838_channels[] = {
101efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(0),
102efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(1),
103efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(2),
104efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(3),
105efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(4),
106efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(5),
107efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(6),
108efc945fbSAkinobu Mita ADC0832_VOLTAGE_CHANNEL(7),
109815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
110815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 9),
111815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3, 10),
112815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2, 11),
113815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(4, 5, 12),
114815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(5, 4, 13),
115815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(6, 7, 14),
116815bbc87SAkinobu Mita ADC0832_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
117815bbc87SAkinobu Mita IIO_CHAN_SOFT_TIMESTAMP(16),
118efc945fbSAkinobu Mita };
119efc945fbSAkinobu Mita
adc0831_adc_conversion(struct adc0832 * adc)120efc945fbSAkinobu Mita static int adc0831_adc_conversion(struct adc0832 *adc)
121efc945fbSAkinobu Mita {
122efc945fbSAkinobu Mita struct spi_device *spi = adc->spi;
123efc945fbSAkinobu Mita int ret;
124efc945fbSAkinobu Mita
125efc945fbSAkinobu Mita ret = spi_read(spi, &adc->rx_buf, 2);
126efc945fbSAkinobu Mita if (ret)
127efc945fbSAkinobu Mita return ret;
128efc945fbSAkinobu Mita
129efc945fbSAkinobu Mita /*
130efc945fbSAkinobu Mita * Skip TRI-STATE and a leading zero
131efc945fbSAkinobu Mita */
132efc945fbSAkinobu Mita return (adc->rx_buf[0] << 2 & 0xff) | (adc->rx_buf[1] >> 6);
133efc945fbSAkinobu Mita }
134efc945fbSAkinobu Mita
adc0832_adc_conversion(struct adc0832 * adc,int channel,bool differential)135efc945fbSAkinobu Mita static int adc0832_adc_conversion(struct adc0832 *adc, int channel,
136efc945fbSAkinobu Mita bool differential)
137efc945fbSAkinobu Mita {
138efc945fbSAkinobu Mita struct spi_device *spi = adc->spi;
139efc945fbSAkinobu Mita struct spi_transfer xfer = {
140efc945fbSAkinobu Mita .tx_buf = adc->tx_buf,
141efc945fbSAkinobu Mita .rx_buf = adc->rx_buf,
142efc945fbSAkinobu Mita .len = 2,
143efc945fbSAkinobu Mita };
144efc945fbSAkinobu Mita int ret;
145efc945fbSAkinobu Mita
146efc945fbSAkinobu Mita if (!adc->mux_bits)
147efc945fbSAkinobu Mita return adc0831_adc_conversion(adc);
148efc945fbSAkinobu Mita
149efc945fbSAkinobu Mita /* start bit */
150efc945fbSAkinobu Mita adc->tx_buf[0] = 1 << (adc->mux_bits + 1);
151efc945fbSAkinobu Mita /* single-ended or differential */
152efc945fbSAkinobu Mita adc->tx_buf[0] |= differential ? 0 : (1 << adc->mux_bits);
153efc945fbSAkinobu Mita /* odd / sign */
154efc945fbSAkinobu Mita adc->tx_buf[0] |= (channel % 2) << (adc->mux_bits - 1);
155efc945fbSAkinobu Mita /* select */
156efc945fbSAkinobu Mita if (adc->mux_bits > 1)
157efc945fbSAkinobu Mita adc->tx_buf[0] |= channel / 2;
158efc945fbSAkinobu Mita
159efc945fbSAkinobu Mita /* align Data output BIT7 (MSB) to 8-bit boundary */
160efc945fbSAkinobu Mita adc->tx_buf[0] <<= 1;
161efc945fbSAkinobu Mita
162efc945fbSAkinobu Mita ret = spi_sync_transfer(spi, &xfer, 1);
163efc945fbSAkinobu Mita if (ret)
164efc945fbSAkinobu Mita return ret;
165efc945fbSAkinobu Mita
166efc945fbSAkinobu Mita return adc->rx_buf[1];
167efc945fbSAkinobu Mita }
168efc945fbSAkinobu Mita
adc0832_read_raw(struct iio_dev * iio,struct iio_chan_spec const * channel,int * value,int * shift,long mask)169efc945fbSAkinobu Mita static int adc0832_read_raw(struct iio_dev *iio,
170efc945fbSAkinobu Mita struct iio_chan_spec const *channel, int *value,
171efc945fbSAkinobu Mita int *shift, long mask)
172efc945fbSAkinobu Mita {
173efc945fbSAkinobu Mita struct adc0832 *adc = iio_priv(iio);
174efc945fbSAkinobu Mita
175efc945fbSAkinobu Mita switch (mask) {
176efc945fbSAkinobu Mita case IIO_CHAN_INFO_RAW:
177efc945fbSAkinobu Mita mutex_lock(&adc->lock);
178efc945fbSAkinobu Mita *value = adc0832_adc_conversion(adc, channel->channel,
179efc945fbSAkinobu Mita channel->differential);
180efc945fbSAkinobu Mita mutex_unlock(&adc->lock);
181efc945fbSAkinobu Mita if (*value < 0)
182efc945fbSAkinobu Mita return *value;
183efc945fbSAkinobu Mita
184efc945fbSAkinobu Mita return IIO_VAL_INT;
185efc945fbSAkinobu Mita case IIO_CHAN_INFO_SCALE:
186efc945fbSAkinobu Mita *value = regulator_get_voltage(adc->reg);
187efc945fbSAkinobu Mita if (*value < 0)
188efc945fbSAkinobu Mita return *value;
189efc945fbSAkinobu Mita
190efc945fbSAkinobu Mita /* convert regulator output voltage to mV */
191efc945fbSAkinobu Mita *value /= 1000;
192efc945fbSAkinobu Mita *shift = 8;
193efc945fbSAkinobu Mita
194efc945fbSAkinobu Mita return IIO_VAL_FRACTIONAL_LOG2;
195efc945fbSAkinobu Mita }
196efc945fbSAkinobu Mita
197efc945fbSAkinobu Mita return -EINVAL;
198efc945fbSAkinobu Mita }
199efc945fbSAkinobu Mita
200efc945fbSAkinobu Mita static const struct iio_info adc0832_info = {
201efc945fbSAkinobu Mita .read_raw = adc0832_read_raw,
202efc945fbSAkinobu Mita };
203efc945fbSAkinobu Mita
adc0832_trigger_handler(int irq,void * p)204815bbc87SAkinobu Mita static irqreturn_t adc0832_trigger_handler(int irq, void *p)
205815bbc87SAkinobu Mita {
206815bbc87SAkinobu Mita struct iio_poll_func *pf = p;
207815bbc87SAkinobu Mita struct iio_dev *indio_dev = pf->indio_dev;
208815bbc87SAkinobu Mita struct adc0832 *adc = iio_priv(indio_dev);
209815bbc87SAkinobu Mita int scan_index;
210815bbc87SAkinobu Mita int i = 0;
211815bbc87SAkinobu Mita
212815bbc87SAkinobu Mita mutex_lock(&adc->lock);
213815bbc87SAkinobu Mita
214815bbc87SAkinobu Mita for_each_set_bit(scan_index, indio_dev->active_scan_mask,
215815bbc87SAkinobu Mita indio_dev->masklength) {
216815bbc87SAkinobu Mita const struct iio_chan_spec *scan_chan =
217815bbc87SAkinobu Mita &indio_dev->channels[scan_index];
218815bbc87SAkinobu Mita int ret = adc0832_adc_conversion(adc, scan_chan->channel,
219815bbc87SAkinobu Mita scan_chan->differential);
220815bbc87SAkinobu Mita if (ret < 0) {
221815bbc87SAkinobu Mita dev_warn(&adc->spi->dev,
222815bbc87SAkinobu Mita "failed to get conversion data\n");
223815bbc87SAkinobu Mita goto out;
224815bbc87SAkinobu Mita }
225815bbc87SAkinobu Mita
22639e91f3bSJonathan Cameron adc->data[i] = ret;
227815bbc87SAkinobu Mita i++;
228815bbc87SAkinobu Mita }
22939e91f3bSJonathan Cameron iio_push_to_buffers_with_timestamp(indio_dev, adc->data,
230815bbc87SAkinobu Mita iio_get_time_ns(indio_dev));
231815bbc87SAkinobu Mita out:
232815bbc87SAkinobu Mita mutex_unlock(&adc->lock);
233815bbc87SAkinobu Mita
234815bbc87SAkinobu Mita iio_trigger_notify_done(indio_dev->trig);
235815bbc87SAkinobu Mita
236815bbc87SAkinobu Mita return IRQ_HANDLED;
237815bbc87SAkinobu Mita }
238815bbc87SAkinobu Mita
adc0832_reg_disable(void * reg)23955364f73SJonathan Cameron static void adc0832_reg_disable(void *reg)
24055364f73SJonathan Cameron {
24155364f73SJonathan Cameron regulator_disable(reg);
24255364f73SJonathan Cameron }
24355364f73SJonathan Cameron
adc0832_probe(struct spi_device * spi)244efc945fbSAkinobu Mita static int adc0832_probe(struct spi_device *spi)
245efc945fbSAkinobu Mita {
246efc945fbSAkinobu Mita struct iio_dev *indio_dev;
247efc945fbSAkinobu Mita struct adc0832 *adc;
248efc945fbSAkinobu Mita int ret;
249efc945fbSAkinobu Mita
250efc945fbSAkinobu Mita indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
251efc945fbSAkinobu Mita if (!indio_dev)
252efc945fbSAkinobu Mita return -ENOMEM;
253efc945fbSAkinobu Mita
254efc945fbSAkinobu Mita adc = iio_priv(indio_dev);
255efc945fbSAkinobu Mita adc->spi = spi;
256efc945fbSAkinobu Mita mutex_init(&adc->lock);
257efc945fbSAkinobu Mita
258efc945fbSAkinobu Mita indio_dev->name = spi_get_device_id(spi)->name;
259efc945fbSAkinobu Mita indio_dev->info = &adc0832_info;
260efc945fbSAkinobu Mita indio_dev->modes = INDIO_DIRECT_MODE;
261efc945fbSAkinobu Mita
262efc945fbSAkinobu Mita switch (spi_get_device_id(spi)->driver_data) {
263efc945fbSAkinobu Mita case adc0831:
264efc945fbSAkinobu Mita adc->mux_bits = 0;
265efc945fbSAkinobu Mita indio_dev->channels = adc0831_channels;
266efc945fbSAkinobu Mita indio_dev->num_channels = ARRAY_SIZE(adc0831_channels);
267efc945fbSAkinobu Mita break;
268efc945fbSAkinobu Mita case adc0832:
269efc945fbSAkinobu Mita adc->mux_bits = 1;
270efc945fbSAkinobu Mita indio_dev->channels = adc0832_channels;
271efc945fbSAkinobu Mita indio_dev->num_channels = ARRAY_SIZE(adc0832_channels);
272efc945fbSAkinobu Mita break;
273efc945fbSAkinobu Mita case adc0834:
274efc945fbSAkinobu Mita adc->mux_bits = 2;
275efc945fbSAkinobu Mita indio_dev->channels = adc0834_channels;
276efc945fbSAkinobu Mita indio_dev->num_channels = ARRAY_SIZE(adc0834_channels);
277efc945fbSAkinobu Mita break;
278efc945fbSAkinobu Mita case adc0838:
279efc945fbSAkinobu Mita adc->mux_bits = 3;
280efc945fbSAkinobu Mita indio_dev->channels = adc0838_channels;
281efc945fbSAkinobu Mita indio_dev->num_channels = ARRAY_SIZE(adc0838_channels);
282efc945fbSAkinobu Mita break;
283efc945fbSAkinobu Mita default:
284efc945fbSAkinobu Mita return -EINVAL;
285efc945fbSAkinobu Mita }
286efc945fbSAkinobu Mita
287efc945fbSAkinobu Mita adc->reg = devm_regulator_get(&spi->dev, "vref");
288efc945fbSAkinobu Mita if (IS_ERR(adc->reg))
289efc945fbSAkinobu Mita return PTR_ERR(adc->reg);
290efc945fbSAkinobu Mita
291efc945fbSAkinobu Mita ret = regulator_enable(adc->reg);
292efc945fbSAkinobu Mita if (ret)
293efc945fbSAkinobu Mita return ret;
294efc945fbSAkinobu Mita
29555364f73SJonathan Cameron ret = devm_add_action_or_reset(&spi->dev, adc0832_reg_disable,
29655364f73SJonathan Cameron adc->reg);
29755364f73SJonathan Cameron if (ret)
29855364f73SJonathan Cameron return ret;
299efc945fbSAkinobu Mita
30055364f73SJonathan Cameron ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
301815bbc87SAkinobu Mita adc0832_trigger_handler, NULL);
302815bbc87SAkinobu Mita if (ret)
303efc945fbSAkinobu Mita return ret;
304efc945fbSAkinobu Mita
30555364f73SJonathan Cameron return devm_iio_device_register(&spi->dev, indio_dev);
306efc945fbSAkinobu Mita }
307efc945fbSAkinobu Mita
308efc945fbSAkinobu Mita static const struct of_device_id adc0832_dt_ids[] = {
309efc945fbSAkinobu Mita { .compatible = "ti,adc0831", },
310efc945fbSAkinobu Mita { .compatible = "ti,adc0832", },
311efc945fbSAkinobu Mita { .compatible = "ti,adc0834", },
312efc945fbSAkinobu Mita { .compatible = "ti,adc0838", },
313efc945fbSAkinobu Mita {}
314efc945fbSAkinobu Mita };
315efc945fbSAkinobu Mita MODULE_DEVICE_TABLE(of, adc0832_dt_ids);
316efc945fbSAkinobu Mita
317efc945fbSAkinobu Mita static const struct spi_device_id adc0832_id[] = {
318efc945fbSAkinobu Mita { "adc0831", adc0831 },
319efc945fbSAkinobu Mita { "adc0832", adc0832 },
320efc945fbSAkinobu Mita { "adc0834", adc0834 },
321efc945fbSAkinobu Mita { "adc0838", adc0838 },
322efc945fbSAkinobu Mita {}
323efc945fbSAkinobu Mita };
324efc945fbSAkinobu Mita MODULE_DEVICE_TABLE(spi, adc0832_id);
325efc945fbSAkinobu Mita
326efc945fbSAkinobu Mita static struct spi_driver adc0832_driver = {
327efc945fbSAkinobu Mita .driver = {
328efc945fbSAkinobu Mita .name = "adc0832",
3290896ffddSJonathan Cameron .of_match_table = adc0832_dt_ids,
330efc945fbSAkinobu Mita },
331efc945fbSAkinobu Mita .probe = adc0832_probe,
332efc945fbSAkinobu Mita .id_table = adc0832_id,
333efc945fbSAkinobu Mita };
334efc945fbSAkinobu Mita module_spi_driver(adc0832_driver);
335efc945fbSAkinobu Mita
336efc945fbSAkinobu Mita MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
337efc945fbSAkinobu Mita MODULE_DESCRIPTION("ADC0831/ADC0832/ADC0834/ADC0838 driver");
338efc945fbSAkinobu Mita MODULE_LICENSE("GPL v2");
339