1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * GPADC driver for sunxi platforms (D1, T113-S3 and R329)
4  * Copyright (c) 2023 Maksim Kiselev <bigunclemax@gmail.com>
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/property.h>
16 #include <linux/reset.h>
17 
18 #include <linux/iio/iio.h>
19 
20 #define SUN20I_GPADC_DRIVER_NAME	"sun20i-gpadc"
21 
22 /* Register map definition */
23 #define SUN20I_GPADC_SR			0x00
24 #define SUN20I_GPADC_CTRL		0x04
25 #define SUN20I_GPADC_CS_EN		0x08
26 #define SUN20I_GPADC_FIFO_INTC		0x0c
27 #define SUN20I_GPADC_FIFO_INTS		0x10
28 #define SUN20I_GPADC_FIFO_DATA		0X14
29 #define SUN20I_GPADC_CB_DATA		0X18
30 #define SUN20I_GPADC_DATAL_INTC		0x20
31 #define SUN20I_GPADC_DATAH_INTC		0x24
32 #define SUN20I_GPADC_DATA_INTC		0x28
33 #define SUN20I_GPADC_DATAL_INTS		0x30
34 #define SUN20I_GPADC_DATAH_INTS		0x34
35 #define SUN20I_GPADC_DATA_INTS		0x38
36 #define SUN20I_GPADC_CH_CMP_DATA(x)	(0x40 + (x) * 4)
37 #define SUN20I_GPADC_CH_DATA(x)		(0x80 + (x) * 4)
38 
39 #define SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK		BIT(23)
40 #define SUN20I_GPADC_CTRL_WORK_MODE_MASK		GENMASK(19, 18)
41 #define SUN20I_GPADC_CTRL_ADC_EN_MASK			BIT(16)
42 #define SUN20I_GPADC_CS_EN_ADC_CH(x)			BIT(x)
43 #define SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(x)	BIT(x)
44 
45 #define SUN20I_GPADC_WORK_MODE_SINGLE			0
46 
47 struct sun20i_gpadc_iio {
48 	void __iomem		*regs;
49 	struct completion	completion;
50 	int			last_channel;
51 	/*
52 	 * Lock to protect the device state during a potential concurrent
53 	 * read access from userspace. Reading a raw value requires a sequence
54 	 * of register writes, then a wait for a completion callback,
55 	 * and finally a register read, during which userspace could issue
56 	 * another read request. This lock protects a read access from
57 	 * ocurring before another one has finished.
58 	 */
59 	struct mutex		lock;
60 };
61 
62 static int sun20i_gpadc_adc_read(struct sun20i_gpadc_iio *info,
63 				 struct iio_chan_spec const *chan, int *val)
64 {
65 	u32 ctrl;
66 	int ret = IIO_VAL_INT;
67 
68 	mutex_lock(&info->lock);
69 
70 	reinit_completion(&info->completion);
71 
72 	if (info->last_channel != chan->channel) {
73 		info->last_channel = chan->channel;
74 
75 		/* enable the analog input channel */
76 		writel(SUN20I_GPADC_CS_EN_ADC_CH(chan->channel),
77 		       info->regs + SUN20I_GPADC_CS_EN);
78 
79 		/* enable the data irq for input channel */
80 		writel(SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(chan->channel),
81 		       info->regs + SUN20I_GPADC_DATA_INTC);
82 	}
83 
84 	/* enable the ADC function */
85 	ctrl = readl(info->regs + SUN20I_GPADC_CTRL);
86 	ctrl |= FIELD_PREP(SUN20I_GPADC_CTRL_ADC_EN_MASK, 1);
87 	writel(ctrl, info->regs + SUN20I_GPADC_CTRL);
88 
89 	/*
90 	 * According to the datasheet maximum acquire time(TACQ) can be
91 	 * (65535+1)/24Mhz and conversion time(CONV_TIME) is always constant
92 	 * and equal to 14/24Mhz, so (TACQ+CONV_TIME) <= 2.73125ms.
93 	 * A 10ms delay should be enough to make sure an interrupt occurs in
94 	 * normal conditions. If it doesn't occur, then there is a timeout.
95 	 */
96 	if (!wait_for_completion_timeout(&info->completion, msecs_to_jiffies(10))) {
97 		ret = -ETIMEDOUT;
98 		goto err_unlock;
99 	}
100 
101 	/* read the ADC data */
102 	*val = readl(info->regs + SUN20I_GPADC_CH_DATA(chan->channel));
103 
104 err_unlock:
105 	mutex_unlock(&info->lock);
106 
107 	return ret;
108 }
109 
110 static int sun20i_gpadc_read_raw(struct iio_dev *indio_dev,
111 				 struct iio_chan_spec const *chan, int *val,
112 				 int *val2, long mask)
113 {
114 	struct sun20i_gpadc_iio *info = iio_priv(indio_dev);
115 
116 	switch (mask) {
117 	case IIO_CHAN_INFO_RAW:
118 		return sun20i_gpadc_adc_read(info, chan, val);
119 	case IIO_CHAN_INFO_SCALE:
120 		/* value in mv = 1800mV / 4096 raw */
121 		*val = 1800;
122 		*val2 = 12;
123 		return IIO_VAL_FRACTIONAL_LOG2;
124 	default:
125 		return -EINVAL;
126 	}
127 }
128 
129 static irqreturn_t sun20i_gpadc_irq_handler(int irq, void *data)
130 {
131 	struct sun20i_gpadc_iio *info = data;
132 
133 	/* clear data interrupt status register */
134 	writel(GENMASK(31, 0), info->regs + SUN20I_GPADC_DATA_INTS);
135 
136 	complete(&info->completion);
137 
138 	return IRQ_HANDLED;
139 }
140 
141 static const struct iio_info sun20i_gpadc_iio_info = {
142 	.read_raw = sun20i_gpadc_read_raw,
143 };
144 
145 static void sun20i_gpadc_reset_assert(void *data)
146 {
147 	struct reset_control *rst = data;
148 
149 	reset_control_assert(rst);
150 }
151 
152 static int sun20i_gpadc_alloc_channels(struct iio_dev *indio_dev,
153 				       struct device *dev)
154 {
155 	unsigned int channel;
156 	int num_channels, i, ret;
157 	struct iio_chan_spec *channels;
158 	struct fwnode_handle *node;
159 
160 	num_channels = device_get_child_node_count(dev);
161 	if (num_channels == 0)
162 		return dev_err_probe(dev, -ENODEV, "no channel children\n");
163 
164 	channels = devm_kcalloc(dev, num_channels, sizeof(*channels),
165 				GFP_KERNEL);
166 	if (!channels)
167 		return -ENOMEM;
168 
169 	i = 0;
170 	device_for_each_child_node(dev, node) {
171 		ret = fwnode_property_read_u32(node, "reg", &channel);
172 		if (ret) {
173 			fwnode_handle_put(node);
174 			return dev_err_probe(dev, ret, "invalid channel number\n");
175 		}
176 
177 		channels[i].type = IIO_VOLTAGE;
178 		channels[i].indexed = 1;
179 		channels[i].channel = channel;
180 		channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
181 		channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
182 
183 		i++;
184 	}
185 
186 	indio_dev->channels = channels;
187 	indio_dev->num_channels = num_channels;
188 
189 	return 0;
190 }
191 
192 static int sun20i_gpadc_probe(struct platform_device *pdev)
193 {
194 	struct device *dev = &pdev->dev;
195 	struct iio_dev *indio_dev;
196 	struct sun20i_gpadc_iio *info;
197 	struct reset_control *rst;
198 	struct clk *clk;
199 	int irq;
200 	int ret;
201 
202 	indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
203 	if (!indio_dev)
204 		return -ENOMEM;
205 
206 	info = iio_priv(indio_dev);
207 	info->last_channel = -1;
208 
209 	mutex_init(&info->lock);
210 	init_completion(&info->completion);
211 
212 	ret = sun20i_gpadc_alloc_channels(indio_dev, dev);
213 	if (ret)
214 		return ret;
215 
216 	indio_dev->info = &sun20i_gpadc_iio_info;
217 	indio_dev->name = SUN20I_GPADC_DRIVER_NAME;
218 
219 	info->regs = devm_platform_ioremap_resource(pdev, 0);
220 	if (IS_ERR(info->regs))
221 		return PTR_ERR(info->regs);
222 
223 	clk = devm_clk_get_enabled(dev, NULL);
224 	if (IS_ERR(clk))
225 		return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock\n");
226 
227 	rst = devm_reset_control_get_exclusive(dev, NULL);
228 	if (IS_ERR(rst))
229 		return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n");
230 
231 	ret = reset_control_deassert(rst);
232 	if (ret)
233 		return dev_err_probe(dev, ret, "failed to deassert reset\n");
234 
235 	ret = devm_add_action_or_reset(dev, sun20i_gpadc_reset_assert, rst);
236 	if (ret)
237 		return ret;
238 
239 	irq = platform_get_irq(pdev, 0);
240 	if (irq < 0)
241 		return irq;
242 
243 	ret = devm_request_irq(dev, irq, sun20i_gpadc_irq_handler, 0,
244 			       dev_name(dev), info);
245 	if (ret)
246 		return dev_err_probe(dev, ret, "failed requesting irq %d\n", irq);
247 
248 	writel(FIELD_PREP(SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK, 1) |
249 	       FIELD_PREP(SUN20I_GPADC_CTRL_WORK_MODE_MASK, SUN20I_GPADC_WORK_MODE_SINGLE),
250 	       info->regs + SUN20I_GPADC_CTRL);
251 
252 	ret = devm_iio_device_register(dev, indio_dev);
253 	if (ret)
254 		return dev_err_probe(dev, ret, "could not register the device\n");
255 
256 	return 0;
257 }
258 
259 static const struct of_device_id sun20i_gpadc_of_id[] = {
260 	{ .compatible = "allwinner,sun20i-d1-gpadc" },
261 	{ /* sentinel */ }
262 };
263 MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id);
264 
265 static struct platform_driver sun20i_gpadc_driver = {
266 	.driver = {
267 		.name = SUN20I_GPADC_DRIVER_NAME,
268 		.of_match_table = sun20i_gpadc_of_id,
269 	},
270 	.probe = sun20i_gpadc_probe,
271 };
272 module_platform_driver(sun20i_gpadc_driver);
273 
274 MODULE_DESCRIPTION("ADC driver for sunxi platforms");
275 MODULE_AUTHOR("Maksim Kiselev <bigunclemax@gmail.com>");
276 MODULE_LICENSE("GPL");
277