1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * STMicroelectronics STMPE811 IIO ADC Driver 4 * 5 * 4 channel, 10/12-bit ADC 6 * 7 * Copyright (C) 2013-2018 Toradex AG <stefan.agner@toradex.com> 8 */ 9 10 #include <linux/completion.h> 11 #include <linux/err.h> 12 #include <linux/iio/iio.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/mfd/stmpe.h> 16 #include <linux/module.h> 17 #include <linux/of_platform.h> 18 #include <linux/platform_device.h> 19 #include <linux/device.h> 20 21 #define STMPE_REG_INT_STA 0x0B 22 #define STMPE_REG_ADC_INT_EN 0x0E 23 #define STMPE_REG_ADC_INT_STA 0x0F 24 25 #define STMPE_REG_ADC_CTRL1 0x20 26 #define STMPE_REG_ADC_CTRL2 0x21 27 #define STMPE_REG_ADC_CAPT 0x22 28 #define STMPE_REG_ADC_DATA_CH(channel) (0x30 + 2 * (channel)) 29 30 #define STMPE_REG_TEMP_CTRL 0x60 31 #define STMPE_TEMP_CTRL_ENABLE BIT(0) 32 #define STMPE_TEMP_CTRL_ACQ BIT(1) 33 #define STMPE_TEMP_CTRL_THRES_EN BIT(3) 34 #define STMPE_START_ONE_TEMP_CONV (STMPE_TEMP_CTRL_ENABLE | \ 35 STMPE_TEMP_CTRL_ACQ | \ 36 STMPE_TEMP_CTRL_THRES_EN) 37 #define STMPE_REG_TEMP_DATA 0x61 38 #define STMPE_REG_TEMP_TH 0x63 39 #define STMPE_ADC_LAST_NR 7 40 #define STMPE_TEMP_CHANNEL (STMPE_ADC_LAST_NR + 1) 41 42 #define STMPE_ADC_CH(channel) ((1 << (channel)) & 0xff) 43 44 #define STMPE_ADC_TIMEOUT msecs_to_jiffies(1000) 45 46 struct stmpe_adc { 47 struct stmpe *stmpe; 48 struct clk *clk; 49 struct device *dev; 50 struct mutex lock; 51 52 /* We are allocating plus one for the temperature channel */ 53 struct iio_chan_spec stmpe_adc_iio_channels[STMPE_ADC_LAST_NR + 2]; 54 55 struct completion completion; 56 57 u8 channel; 58 u32 value; 59 }; 60 61 static int stmpe_read_voltage(struct stmpe_adc *info, 62 struct iio_chan_spec const *chan, int *val) 63 { 64 unsigned long ret; 65 66 mutex_lock(&info->lock); 67 68 reinit_completion(&info->completion); 69 70 info->channel = (u8)chan->channel; 71 72 if (info->channel > STMPE_ADC_LAST_NR) { 73 mutex_unlock(&info->lock); 74 return -EINVAL; 75 } 76 77 stmpe_reg_write(info->stmpe, STMPE_REG_ADC_CAPT, 78 STMPE_ADC_CH(info->channel)); 79 80 ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT); 81 82 if (ret == 0) { 83 stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, 84 STMPE_ADC_CH(info->channel)); 85 mutex_unlock(&info->lock); 86 return -ETIMEDOUT; 87 } 88 89 *val = info->value; 90 91 mutex_unlock(&info->lock); 92 93 return 0; 94 } 95 96 static int stmpe_read_temp(struct stmpe_adc *info, 97 struct iio_chan_spec const *chan, int *val) 98 { 99 unsigned long ret; 100 101 mutex_lock(&info->lock); 102 103 reinit_completion(&info->completion); 104 105 info->channel = (u8)chan->channel; 106 107 if (info->channel != STMPE_TEMP_CHANNEL) { 108 mutex_unlock(&info->lock); 109 return -EINVAL; 110 } 111 112 stmpe_reg_write(info->stmpe, STMPE_REG_TEMP_CTRL, 113 STMPE_START_ONE_TEMP_CONV); 114 115 ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT); 116 117 if (ret == 0) { 118 mutex_unlock(&info->lock); 119 return -ETIMEDOUT; 120 } 121 122 /* 123 * absolute temp = +V3.3 * value /7.51 [K] 124 * scale to [milli °C] 125 */ 126 *val = ((449960l * info->value) / 1024l) - 273150; 127 128 mutex_unlock(&info->lock); 129 130 return 0; 131 } 132 133 static int stmpe_read_raw(struct iio_dev *indio_dev, 134 struct iio_chan_spec const *chan, 135 int *val, 136 int *val2, 137 long mask) 138 { 139 struct stmpe_adc *info = iio_priv(indio_dev); 140 long ret; 141 142 switch (mask) { 143 case IIO_CHAN_INFO_RAW: 144 case IIO_CHAN_INFO_PROCESSED: 145 146 switch (chan->type) { 147 case IIO_VOLTAGE: 148 ret = stmpe_read_voltage(info, chan, val); 149 break; 150 151 case IIO_TEMP: 152 ret = stmpe_read_temp(info, chan, val); 153 break; 154 default: 155 return -EINVAL; 156 } 157 158 if (ret < 0) 159 return ret; 160 161 return IIO_VAL_INT; 162 163 case IIO_CHAN_INFO_SCALE: 164 *val = 3300; 165 *val2 = info->stmpe->mod_12b ? 12 : 10; 166 return IIO_VAL_FRACTIONAL_LOG2; 167 168 default: 169 break; 170 } 171 172 return -EINVAL; 173 } 174 175 static irqreturn_t stmpe_adc_isr(int irq, void *dev_id) 176 { 177 struct stmpe_adc *info = (struct stmpe_adc *)dev_id; 178 __be16 data; 179 180 if (info->channel <= STMPE_ADC_LAST_NR) { 181 int int_sta; 182 183 int_sta = stmpe_reg_read(info->stmpe, STMPE_REG_ADC_INT_STA); 184 185 /* Is the interrupt relevant */ 186 if (!(int_sta & STMPE_ADC_CH(info->channel))) 187 return IRQ_NONE; 188 189 /* Read value */ 190 stmpe_block_read(info->stmpe, 191 STMPE_REG_ADC_DATA_CH(info->channel), 2, (u8 *) &data); 192 193 stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, int_sta); 194 } else if (info->channel == STMPE_TEMP_CHANNEL) { 195 /* Read value */ 196 stmpe_block_read(info->stmpe, STMPE_REG_TEMP_DATA, 2, 197 (u8 *) &data); 198 } else { 199 return IRQ_NONE; 200 } 201 202 info->value = (u32) be16_to_cpu(data); 203 complete(&info->completion); 204 205 return IRQ_HANDLED; 206 } 207 208 static const struct iio_info stmpe_adc_iio_info = { 209 .read_raw = &stmpe_read_raw, 210 }; 211 212 static void stmpe_adc_voltage_chan(struct iio_chan_spec *ics, int chan) 213 { 214 ics->type = IIO_VOLTAGE; 215 ics->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 216 ics->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 217 ics->indexed = 1; 218 ics->channel = chan; 219 } 220 221 static void stmpe_adc_temp_chan(struct iio_chan_spec *ics, int chan) 222 { 223 ics->type = IIO_TEMP; 224 ics->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); 225 ics->indexed = 1; 226 ics->channel = chan; 227 } 228 229 static int stmpe_adc_init_hw(struct stmpe_adc *adc) 230 { 231 int ret; 232 struct stmpe *stmpe = adc->stmpe; 233 234 ret = stmpe_enable(stmpe, STMPE_BLOCK_ADC); 235 if (ret) { 236 dev_err(stmpe->dev, "Could not enable clock for ADC\n"); 237 return ret; 238 } 239 240 ret = stmpe811_adc_common_init(stmpe); 241 if (ret) { 242 stmpe_disable(stmpe, STMPE_BLOCK_ADC); 243 return ret; 244 } 245 246 /* use temp irq for each conversion completion */ 247 stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH, 0); 248 stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH + 1, 0); 249 250 return 0; 251 } 252 253 static int stmpe_adc_probe(struct platform_device *pdev) 254 { 255 struct iio_dev *indio_dev; 256 struct stmpe_adc *info; 257 struct device_node *np; 258 u32 norequest_mask = 0; 259 unsigned long bits; 260 int irq_temp, irq_adc; 261 int num_chan = 0; 262 int i = 0; 263 int ret; 264 265 irq_adc = platform_get_irq_byname(pdev, "STMPE_ADC"); 266 if (irq_adc < 0) 267 return irq_adc; 268 269 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct stmpe_adc)); 270 if (!indio_dev) { 271 dev_err(&pdev->dev, "failed allocating iio device\n"); 272 return -ENOMEM; 273 } 274 275 info = iio_priv(indio_dev); 276 mutex_init(&info->lock); 277 278 init_completion(&info->completion); 279 ret = devm_request_threaded_irq(&pdev->dev, irq_adc, NULL, 280 stmpe_adc_isr, IRQF_ONESHOT, 281 "stmpe-adc", info); 282 if (ret < 0) { 283 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", 284 irq_adc); 285 return ret; 286 } 287 288 irq_temp = platform_get_irq_byname(pdev, "STMPE_TEMP_SENS"); 289 if (irq_temp >= 0) { 290 ret = devm_request_threaded_irq(&pdev->dev, irq_temp, NULL, 291 stmpe_adc_isr, IRQF_ONESHOT, 292 "stmpe-adc", info); 293 if (ret < 0) 294 dev_warn(&pdev->dev, "failed requesting irq for" 295 " temp sensor, irq = %d\n", irq_temp); 296 } 297 298 platform_set_drvdata(pdev, indio_dev); 299 300 indio_dev->name = dev_name(&pdev->dev); 301 indio_dev->info = &stmpe_adc_iio_info; 302 indio_dev->modes = INDIO_DIRECT_MODE; 303 304 info->stmpe = dev_get_drvdata(pdev->dev.parent); 305 306 np = pdev->dev.of_node; 307 308 if (!np) 309 dev_err(&pdev->dev, "no device tree node found\n"); 310 311 of_property_read_u32(np, "st,norequest-mask", &norequest_mask); 312 313 bits = norequest_mask; 314 for_each_clear_bit(i, &bits, (STMPE_ADC_LAST_NR + 1)) { 315 stmpe_adc_voltage_chan(&info->stmpe_adc_iio_channels[num_chan], i); 316 num_chan++; 317 } 318 stmpe_adc_temp_chan(&info->stmpe_adc_iio_channels[num_chan], i); 319 num_chan++; 320 indio_dev->channels = info->stmpe_adc_iio_channels; 321 indio_dev->num_channels = num_chan; 322 323 ret = stmpe_adc_init_hw(info); 324 if (ret) 325 return ret; 326 327 stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_EN, 328 ~(norequest_mask & 0xFF)); 329 330 stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, 331 ~(norequest_mask & 0xFF)); 332 333 return devm_iio_device_register(&pdev->dev, indio_dev); 334 } 335 336 static int stmpe_adc_resume(struct device *dev) 337 { 338 struct iio_dev *indio_dev = dev_get_drvdata(dev); 339 struct stmpe_adc *info = iio_priv(indio_dev); 340 341 stmpe_adc_init_hw(info); 342 343 return 0; 344 } 345 346 static DEFINE_SIMPLE_DEV_PM_OPS(stmpe_adc_pm_ops, NULL, stmpe_adc_resume); 347 348 static const struct of_device_id stmpe_adc_ids[] = { 349 { .compatible = "st,stmpe-adc", }, 350 { }, 351 }; 352 MODULE_DEVICE_TABLE(of, stmpe_adc_ids); 353 354 static struct platform_driver stmpe_adc_driver = { 355 .probe = stmpe_adc_probe, 356 .driver = { 357 .name = "stmpe-adc", 358 .pm = pm_sleep_ptr(&stmpe_adc_pm_ops), 359 .of_match_table = stmpe_adc_ids, 360 }, 361 }; 362 module_platform_driver(stmpe_adc_driver); 363 364 MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>"); 365 MODULE_DESCRIPTION("STMPEXXX ADC driver"); 366 MODULE_LICENSE("GPL v2"); 367 MODULE_ALIAS("platform:stmpe-adc"); 368