1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * This file is part the core part STM32 DFSDM driver
4  *
5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6  * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/iio/iio.h>
11 #include <linux/iio/sysfs.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 
20 #include "stm32-dfsdm.h"
21 
22 struct stm32_dfsdm_dev_data {
23 	unsigned int num_filters;
24 	unsigned int num_channels;
25 	const struct regmap_config *regmap_cfg;
26 };
27 
28 #define STM32H7_DFSDM_NUM_FILTERS	4
29 #define STM32H7_DFSDM_NUM_CHANNELS	8
30 #define STM32MP1_DFSDM_NUM_FILTERS	6
31 #define STM32MP1_DFSDM_NUM_CHANNELS	8
32 
33 static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
34 {
35 	if (reg < DFSDM_FILTER_BASE_ADR)
36 		return false;
37 
38 	/*
39 	 * Mask is done on register to avoid to list registers of all
40 	 * filter instances.
41 	 */
42 	switch (reg & DFSDM_FILTER_REG_MASK) {
43 	case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
44 	case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
45 	case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
46 	case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
47 		return true;
48 	}
49 
50 	return false;
51 }
52 
53 static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
54 	.reg_bits = 32,
55 	.val_bits = 32,
56 	.reg_stride = sizeof(u32),
57 	.max_register = 0x2B8,
58 	.volatile_reg = stm32_dfsdm_volatile_reg,
59 	.fast_io = true,
60 };
61 
62 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
63 	.num_filters = STM32H7_DFSDM_NUM_FILTERS,
64 	.num_channels = STM32H7_DFSDM_NUM_CHANNELS,
65 	.regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
66 };
67 
68 static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = {
69 	.reg_bits = 32,
70 	.val_bits = 32,
71 	.reg_stride = sizeof(u32),
72 	.max_register = 0x7fc,
73 	.volatile_reg = stm32_dfsdm_volatile_reg,
74 	.fast_io = true,
75 };
76 
77 static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = {
78 	.num_filters = STM32MP1_DFSDM_NUM_FILTERS,
79 	.num_channels = STM32MP1_DFSDM_NUM_CHANNELS,
80 	.regmap_cfg = &stm32mp1_dfsdm_regmap_cfg,
81 };
82 
83 struct dfsdm_priv {
84 	struct platform_device *pdev; /* platform device */
85 
86 	struct stm32_dfsdm dfsdm; /* common data exported for all instances */
87 
88 	unsigned int spi_clk_out_div; /* SPI clkout divider value */
89 	atomic_t n_active_ch;	/* number of current active channels */
90 
91 	struct clk *clk; /* DFSDM clock */
92 	struct clk *aclk; /* audio clock */
93 };
94 
95 static inline struct dfsdm_priv *to_stm32_dfsdm_priv(struct stm32_dfsdm *dfsdm)
96 {
97 	return container_of(dfsdm, struct dfsdm_priv, dfsdm);
98 }
99 
100 static int stm32_dfsdm_clk_prepare_enable(struct stm32_dfsdm *dfsdm)
101 {
102 	struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
103 	int ret;
104 
105 	ret = clk_prepare_enable(priv->clk);
106 	if (ret || !priv->aclk)
107 		return ret;
108 
109 	ret = clk_prepare_enable(priv->aclk);
110 	if (ret)
111 		clk_disable_unprepare(priv->clk);
112 
113 	return ret;
114 }
115 
116 static void stm32_dfsdm_clk_disable_unprepare(struct stm32_dfsdm *dfsdm)
117 {
118 	struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
119 
120 	clk_disable_unprepare(priv->aclk);
121 	clk_disable_unprepare(priv->clk);
122 }
123 
124 /**
125  * stm32_dfsdm_start_dfsdm - start global dfsdm interface.
126  *
127  * Enable interface if n_active_ch is not null.
128  * @dfsdm: Handle used to retrieve dfsdm context.
129  */
130 int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
131 {
132 	struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
133 	struct device *dev = &priv->pdev->dev;
134 	unsigned int clk_div = priv->spi_clk_out_div, clk_src;
135 	int ret;
136 
137 	if (atomic_inc_return(&priv->n_active_ch) == 1) {
138 		ret = pm_runtime_get_sync(dev);
139 		if (ret < 0) {
140 			pm_runtime_put_noidle(dev);
141 			goto error_ret;
142 		}
143 
144 		/* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
145 		clk_src = priv->aclk ? 1 : 0;
146 		ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
147 					 DFSDM_CHCFGR1_CKOUTSRC_MASK,
148 					 DFSDM_CHCFGR1_CKOUTSRC(clk_src));
149 		if (ret < 0)
150 			goto pm_put;
151 
152 		/* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
153 		ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
154 					 DFSDM_CHCFGR1_CKOUTDIV_MASK,
155 					 DFSDM_CHCFGR1_CKOUTDIV(clk_div));
156 		if (ret < 0)
157 			goto pm_put;
158 
159 		/* Global enable of DFSDM interface */
160 		ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
161 					 DFSDM_CHCFGR1_DFSDMEN_MASK,
162 					 DFSDM_CHCFGR1_DFSDMEN(1));
163 		if (ret < 0)
164 			goto pm_put;
165 	}
166 
167 	dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
168 		atomic_read(&priv->n_active_ch));
169 
170 	return 0;
171 
172 pm_put:
173 	pm_runtime_put_sync(dev);
174 error_ret:
175 	atomic_dec(&priv->n_active_ch);
176 
177 	return ret;
178 }
179 EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
180 
181 /**
182  * stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
183  *
184  * Disable interface if n_active_ch is null
185  * @dfsdm: Handle used to retrieve dfsdm context.
186  */
187 int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
188 {
189 	struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
190 	int ret;
191 
192 	if (atomic_dec_and_test(&priv->n_active_ch)) {
193 		/* Global disable of DFSDM interface */
194 		ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
195 					 DFSDM_CHCFGR1_DFSDMEN_MASK,
196 					 DFSDM_CHCFGR1_DFSDMEN(0));
197 		if (ret < 0)
198 			return ret;
199 
200 		/* Stop SPI CLKOUT */
201 		ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
202 					 DFSDM_CHCFGR1_CKOUTDIV_MASK,
203 					 DFSDM_CHCFGR1_CKOUTDIV(0));
204 		if (ret < 0)
205 			return ret;
206 
207 		pm_runtime_put_sync(&priv->pdev->dev);
208 	}
209 	dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
210 		atomic_read(&priv->n_active_ch));
211 
212 	return 0;
213 }
214 EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
215 
216 static int stm32_dfsdm_parse_of(struct platform_device *pdev,
217 				struct dfsdm_priv *priv)
218 {
219 	struct device_node *node = pdev->dev.of_node;
220 	struct resource *res;
221 	unsigned long clk_freq, divider;
222 	unsigned int spi_freq, rem;
223 	int ret;
224 
225 	if (!node)
226 		return -EINVAL;
227 
228 	priv->dfsdm.base = devm_platform_get_and_ioremap_resource(pdev, 0,
229 							&res);
230 	if (IS_ERR(priv->dfsdm.base))
231 		return PTR_ERR(priv->dfsdm.base);
232 
233 	priv->dfsdm.phys_base = res->start;
234 
235 	/*
236 	 * "dfsdm" clock is mandatory for DFSDM peripheral clocking.
237 	 * "dfsdm" or "audio" clocks can be used as source clock for
238 	 * the SPI clock out signal and internal processing, depending
239 	 * on use case.
240 	 */
241 	priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
242 	if (IS_ERR(priv->clk))
243 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
244 				     "Failed to get clock\n");
245 
246 	priv->aclk = devm_clk_get(&pdev->dev, "audio");
247 	if (IS_ERR(priv->aclk))
248 		priv->aclk = NULL;
249 
250 	if (priv->aclk)
251 		clk_freq = clk_get_rate(priv->aclk);
252 	else
253 		clk_freq = clk_get_rate(priv->clk);
254 
255 	/* SPI clock out frequency */
256 	ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
257 				   &spi_freq);
258 	if (ret < 0) {
259 		/* No SPI master mode */
260 		return 0;
261 	}
262 
263 	divider = div_u64_rem(clk_freq, spi_freq, &rem);
264 	/* Round up divider when ckout isn't precise, not to exceed spi_freq */
265 	if (rem)
266 		divider++;
267 
268 	/* programmable divider is in range of [2:256] */
269 	if (divider < 2 || divider > 256) {
270 		dev_err(&pdev->dev, "spi-max-frequency not achievable\n");
271 		return -EINVAL;
272 	}
273 
274 	/* SPI clock output divider is: divider = CKOUTDIV + 1 */
275 	priv->spi_clk_out_div = divider - 1;
276 	priv->dfsdm.spi_master_freq = clk_freq / (priv->spi_clk_out_div + 1);
277 
278 	if (rem) {
279 		dev_warn(&pdev->dev, "SPI clock not accurate\n");
280 		dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
281 			 clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
282 	}
283 
284 	return 0;
285 };
286 
287 static const struct of_device_id stm32_dfsdm_of_match[] = {
288 	{
289 		.compatible = "st,stm32h7-dfsdm",
290 		.data = &stm32h7_dfsdm_data,
291 	},
292 	{
293 		.compatible = "st,stm32mp1-dfsdm",
294 		.data = &stm32mp1_dfsdm_data,
295 	},
296 	{}
297 };
298 MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
299 
300 static int stm32_dfsdm_probe(struct platform_device *pdev)
301 {
302 	struct dfsdm_priv *priv;
303 	const struct stm32_dfsdm_dev_data *dev_data;
304 	struct stm32_dfsdm *dfsdm;
305 	int ret;
306 
307 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
308 	if (!priv)
309 		return -ENOMEM;
310 
311 	priv->pdev = pdev;
312 
313 	dev_data = of_device_get_match_data(&pdev->dev);
314 
315 	dfsdm = &priv->dfsdm;
316 	dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
317 				      sizeof(*dfsdm->fl_list), GFP_KERNEL);
318 	if (!dfsdm->fl_list)
319 		return -ENOMEM;
320 
321 	dfsdm->num_fls = dev_data->num_filters;
322 	dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
323 				      sizeof(*dfsdm->ch_list),
324 				      GFP_KERNEL);
325 	if (!dfsdm->ch_list)
326 		return -ENOMEM;
327 	dfsdm->num_chs = dev_data->num_channels;
328 
329 	ret = stm32_dfsdm_parse_of(pdev, priv);
330 	if (ret < 0)
331 		return ret;
332 
333 	dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
334 						  dfsdm->base,
335 						  dev_data->regmap_cfg);
336 	if (IS_ERR(dfsdm->regmap)) {
337 		ret = PTR_ERR(dfsdm->regmap);
338 		dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
339 			__func__, ret);
340 		return ret;
341 	}
342 
343 	platform_set_drvdata(pdev, dfsdm);
344 
345 	ret = stm32_dfsdm_clk_prepare_enable(dfsdm);
346 	if (ret) {
347 		dev_err(&pdev->dev, "Failed to start clock\n");
348 		return ret;
349 	}
350 
351 	pm_runtime_get_noresume(&pdev->dev);
352 	pm_runtime_set_active(&pdev->dev);
353 	pm_runtime_enable(&pdev->dev);
354 
355 	ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
356 	if (ret)
357 		goto pm_put;
358 
359 	pm_runtime_put(&pdev->dev);
360 
361 	return 0;
362 
363 pm_put:
364 	pm_runtime_disable(&pdev->dev);
365 	pm_runtime_set_suspended(&pdev->dev);
366 	pm_runtime_put_noidle(&pdev->dev);
367 	stm32_dfsdm_clk_disable_unprepare(dfsdm);
368 
369 	return ret;
370 }
371 
372 static int stm32_dfsdm_core_remove(struct platform_device *pdev)
373 {
374 	struct stm32_dfsdm *dfsdm = platform_get_drvdata(pdev);
375 
376 	pm_runtime_get_sync(&pdev->dev);
377 	of_platform_depopulate(&pdev->dev);
378 	pm_runtime_disable(&pdev->dev);
379 	pm_runtime_set_suspended(&pdev->dev);
380 	pm_runtime_put_noidle(&pdev->dev);
381 	stm32_dfsdm_clk_disable_unprepare(dfsdm);
382 
383 	return 0;
384 }
385 
386 static int __maybe_unused stm32_dfsdm_core_suspend(struct device *dev)
387 {
388 	struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
389 	struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
390 	int ret;
391 
392 	ret = pm_runtime_force_suspend(dev);
393 	if (ret)
394 		return ret;
395 
396 	/* Balance devm_regmap_init_mmio_clk() clk_prepare() */
397 	clk_unprepare(priv->clk);
398 
399 	return pinctrl_pm_select_sleep_state(dev);
400 }
401 
402 static int __maybe_unused stm32_dfsdm_core_resume(struct device *dev)
403 {
404 	struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
405 	struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
406 	int ret;
407 
408 	ret = pinctrl_pm_select_default_state(dev);
409 	if (ret)
410 		return ret;
411 
412 	ret = clk_prepare(priv->clk);
413 	if (ret)
414 		return ret;
415 
416 	return pm_runtime_force_resume(dev);
417 }
418 
419 static int __maybe_unused stm32_dfsdm_core_runtime_suspend(struct device *dev)
420 {
421 	struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
422 
423 	stm32_dfsdm_clk_disable_unprepare(dfsdm);
424 
425 	return 0;
426 }
427 
428 static int __maybe_unused stm32_dfsdm_core_runtime_resume(struct device *dev)
429 {
430 	struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
431 
432 	return stm32_dfsdm_clk_prepare_enable(dfsdm);
433 }
434 
435 static const struct dev_pm_ops stm32_dfsdm_core_pm_ops = {
436 	SET_SYSTEM_SLEEP_PM_OPS(stm32_dfsdm_core_suspend,
437 				stm32_dfsdm_core_resume)
438 	SET_RUNTIME_PM_OPS(stm32_dfsdm_core_runtime_suspend,
439 			   stm32_dfsdm_core_runtime_resume,
440 			   NULL)
441 };
442 
443 static struct platform_driver stm32_dfsdm_driver = {
444 	.probe = stm32_dfsdm_probe,
445 	.remove = stm32_dfsdm_core_remove,
446 	.driver = {
447 		.name = "stm32-dfsdm",
448 		.of_match_table = stm32_dfsdm_of_match,
449 		.pm = &stm32_dfsdm_core_pm_ops,
450 	},
451 };
452 
453 module_platform_driver(stm32_dfsdm_driver);
454 
455 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
456 MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
457 MODULE_LICENSE("GPL v2");
458