1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is the ADC part of the STM32 DFSDM driver 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>. 7 */ 8 9 #include <linux/dmaengine.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/iio/buffer.h> 13 #include <linux/iio/hw-consumer.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 22 #include "stm32-dfsdm.h" 23 24 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE) 25 26 /* Conversion timeout */ 27 #define DFSDM_TIMEOUT_US 100000 28 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000)) 29 30 /* Oversampling attribute default */ 31 #define DFSDM_DEFAULT_OVERSAMPLING 100 32 33 /* Oversampling max values */ 34 #define DFSDM_MAX_INT_OVERSAMPLING 256 35 #define DFSDM_MAX_FL_OVERSAMPLING 1024 36 37 /* Max sample resolutions */ 38 #define DFSDM_MAX_RES BIT(31) 39 #define DFSDM_DATA_RES BIT(23) 40 41 enum sd_converter_type { 42 DFSDM_AUDIO, 43 DFSDM_IIO, 44 }; 45 46 struct stm32_dfsdm_dev_data { 47 int type; 48 int (*init)(struct iio_dev *indio_dev); 49 unsigned int num_channels; 50 const struct regmap_config *regmap_cfg; 51 }; 52 53 struct stm32_dfsdm_adc { 54 struct stm32_dfsdm *dfsdm; 55 const struct stm32_dfsdm_dev_data *dev_data; 56 unsigned int fl_id; 57 58 /* ADC specific */ 59 unsigned int oversamp; 60 struct iio_hw_consumer *hwc; 61 struct completion completion; 62 u32 *buffer; 63 64 /* Audio specific */ 65 unsigned int spi_freq; /* SPI bus clock frequency */ 66 unsigned int sample_freq; /* Sample frequency after filter decimation */ 67 int (*cb)(const void *data, size_t size, void *cb_priv); 68 void *cb_priv; 69 70 /* DMA */ 71 u8 *rx_buf; 72 unsigned int bufi; /* Buffer current position */ 73 unsigned int buf_sz; /* Buffer size */ 74 struct dma_chan *dma_chan; 75 dma_addr_t dma_buf; 76 }; 77 78 struct stm32_dfsdm_str2field { 79 const char *name; 80 unsigned int val; 81 }; 82 83 /* DFSDM channel serial interface type */ 84 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = { 85 { "SPI_R", 0 }, /* SPI with data on rising edge */ 86 { "SPI_F", 1 }, /* SPI with data on falling edge */ 87 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */ 88 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */ 89 {}, 90 }; 91 92 /* DFSDM channel clock source */ 93 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = { 94 /* External SPI clock (CLKIN x) */ 95 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL }, 96 /* Internal SPI clock (CLKOUT) */ 97 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL }, 98 /* Internal SPI clock divided by 2 (falling edge) */ 99 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING }, 100 /* Internal SPI clock divided by 2 (falling edge) */ 101 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING }, 102 {}, 103 }; 104 105 static int stm32_dfsdm_str2val(const char *str, 106 const struct stm32_dfsdm_str2field *list) 107 { 108 const struct stm32_dfsdm_str2field *p = list; 109 110 for (p = list; p && p->name; p++) 111 if (!strcmp(p->name, str)) 112 return p->val; 113 114 return -EINVAL; 115 } 116 117 static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl, 118 unsigned int fast, unsigned int oversamp) 119 { 120 unsigned int i, d, fosr, iosr; 121 u64 res; 122 s64 delta; 123 unsigned int m = 1; /* multiplication factor */ 124 unsigned int p = fl->ford; /* filter order (ford) */ 125 126 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp); 127 /* 128 * This function tries to compute filter oversampling and integrator 129 * oversampling, base on oversampling ratio requested by user. 130 * 131 * Decimation d depends on the filter order and the oversampling ratios. 132 * ford: filter order 133 * fosr: filter over sampling ratio 134 * iosr: integrator over sampling ratio 135 */ 136 if (fl->ford == DFSDM_FASTSINC_ORDER) { 137 m = 2; 138 p = 2; 139 } 140 141 /* 142 * Look for filter and integrator oversampling ratios which allows 143 * to reach 24 bits data output resolution. 144 * Leave as soon as if exact resolution if reached. 145 * Otherwise the higher resolution below 32 bits is kept. 146 */ 147 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) { 148 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) { 149 if (fast) 150 d = fosr * iosr; 151 else if (fl->ford == DFSDM_FASTSINC_ORDER) 152 d = fosr * (iosr + 3) + 2; 153 else 154 d = fosr * (iosr - 1 + p) + p; 155 156 if (d > oversamp) 157 break; 158 else if (d != oversamp) 159 continue; 160 /* 161 * Check resolution (limited to signed 32 bits) 162 * res <= 2^31 163 * Sincx filters: 164 * res = m * fosr^p x iosr (with m=1, p=ford) 165 * FastSinc filter 166 * res = m * fosr^p x iosr (with m=2, p=2) 167 */ 168 res = fosr; 169 for (i = p - 1; i > 0; i--) { 170 res = res * (u64)fosr; 171 if (res > DFSDM_MAX_RES) 172 break; 173 } 174 if (res > DFSDM_MAX_RES) 175 continue; 176 res = res * (u64)m * (u64)iosr; 177 if (res > DFSDM_MAX_RES) 178 continue; 179 180 delta = res - DFSDM_DATA_RES; 181 182 if (res >= fl->res) { 183 fl->res = res; 184 fl->fosr = fosr; 185 fl->iosr = iosr; 186 fl->fast = fast; 187 pr_debug("%s: fosr = %d, iosr = %d\n", 188 __func__, fl->fosr, fl->iosr); 189 } 190 191 if (!delta) 192 return 0; 193 } 194 } 195 196 if (!fl->fosr) 197 return -EINVAL; 198 199 return 0; 200 } 201 202 static int stm32_dfsdm_start_channel(struct stm32_dfsdm *dfsdm, 203 unsigned int ch_id) 204 { 205 return regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id), 206 DFSDM_CHCFGR1_CHEN_MASK, 207 DFSDM_CHCFGR1_CHEN(1)); 208 } 209 210 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm *dfsdm, 211 unsigned int ch_id) 212 { 213 regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id), 214 DFSDM_CHCFGR1_CHEN_MASK, DFSDM_CHCFGR1_CHEN(0)); 215 } 216 217 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm, 218 struct stm32_dfsdm_channel *ch) 219 { 220 unsigned int id = ch->id; 221 struct regmap *regmap = dfsdm->regmap; 222 int ret; 223 224 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 225 DFSDM_CHCFGR1_SITP_MASK, 226 DFSDM_CHCFGR1_SITP(ch->type)); 227 if (ret < 0) 228 return ret; 229 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 230 DFSDM_CHCFGR1_SPICKSEL_MASK, 231 DFSDM_CHCFGR1_SPICKSEL(ch->src)); 232 if (ret < 0) 233 return ret; 234 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 235 DFSDM_CHCFGR1_CHINSEL_MASK, 236 DFSDM_CHCFGR1_CHINSEL(ch->alt_si)); 237 } 238 239 static int stm32_dfsdm_start_filter(struct stm32_dfsdm *dfsdm, 240 unsigned int fl_id) 241 { 242 int ret; 243 244 /* Enable filter */ 245 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 246 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1)); 247 if (ret < 0) 248 return ret; 249 250 /* Start conversion */ 251 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 252 DFSDM_CR1_RSWSTART_MASK, 253 DFSDM_CR1_RSWSTART(1)); 254 } 255 256 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm, unsigned int fl_id) 257 { 258 /* Disable conversion */ 259 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 260 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0)); 261 } 262 263 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm *dfsdm, 264 unsigned int fl_id, unsigned int ch_id) 265 { 266 struct regmap *regmap = dfsdm->regmap; 267 struct stm32_dfsdm_filter *fl = &dfsdm->fl_list[fl_id]; 268 int ret; 269 270 /* Average integrator oversampling */ 271 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK, 272 DFSDM_FCR_IOSR(fl->iosr - 1)); 273 if (ret) 274 return ret; 275 276 /* Filter order and Oversampling */ 277 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK, 278 DFSDM_FCR_FOSR(fl->fosr - 1)); 279 if (ret) 280 return ret; 281 282 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK, 283 DFSDM_FCR_FORD(fl->ford)); 284 if (ret) 285 return ret; 286 287 /* No scan mode supported for the moment */ 288 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_RCH_MASK, 289 DFSDM_CR1_RCH(ch_id)); 290 if (ret) 291 return ret; 292 293 return regmap_update_bits(regmap, DFSDM_CR1(fl_id), 294 DFSDM_CR1_RSYNC_MASK, 295 DFSDM_CR1_RSYNC(fl->sync_mode)); 296 } 297 298 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm, 299 struct iio_dev *indio_dev, 300 struct iio_chan_spec *ch) 301 { 302 struct stm32_dfsdm_channel *df_ch; 303 const char *of_str; 304 int chan_idx = ch->scan_index; 305 int ret, val; 306 307 ret = of_property_read_u32_index(indio_dev->dev.of_node, 308 "st,adc-channels", chan_idx, 309 &ch->channel); 310 if (ret < 0) { 311 dev_err(&indio_dev->dev, 312 " Error parsing 'st,adc-channels' for idx %d\n", 313 chan_idx); 314 return ret; 315 } 316 if (ch->channel >= dfsdm->num_chs) { 317 dev_err(&indio_dev->dev, 318 " Error bad channel number %d (max = %d)\n", 319 ch->channel, dfsdm->num_chs); 320 return -EINVAL; 321 } 322 323 ret = of_property_read_string_index(indio_dev->dev.of_node, 324 "st,adc-channel-names", chan_idx, 325 &ch->datasheet_name); 326 if (ret < 0) { 327 dev_err(&indio_dev->dev, 328 " Error parsing 'st,adc-channel-names' for idx %d\n", 329 chan_idx); 330 return ret; 331 } 332 333 df_ch = &dfsdm->ch_list[ch->channel]; 334 df_ch->id = ch->channel; 335 336 ret = of_property_read_string_index(indio_dev->dev.of_node, 337 "st,adc-channel-types", chan_idx, 338 &of_str); 339 if (!ret) { 340 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type); 341 if (val < 0) 342 return val; 343 } else { 344 val = 0; 345 } 346 df_ch->type = val; 347 348 ret = of_property_read_string_index(indio_dev->dev.of_node, 349 "st,adc-channel-clk-src", chan_idx, 350 &of_str); 351 if (!ret) { 352 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src); 353 if (val < 0) 354 return val; 355 } else { 356 val = 0; 357 } 358 df_ch->src = val; 359 360 ret = of_property_read_u32_index(indio_dev->dev.of_node, 361 "st,adc-alt-channel", chan_idx, 362 &df_ch->alt_si); 363 if (ret < 0) 364 df_ch->alt_si = 0; 365 366 return 0; 367 } 368 369 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev, 370 uintptr_t priv, 371 const struct iio_chan_spec *chan, 372 char *buf) 373 { 374 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 375 376 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq); 377 } 378 379 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev, 380 uintptr_t priv, 381 const struct iio_chan_spec *chan, 382 const char *buf, size_t len) 383 { 384 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 385 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; 386 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel]; 387 unsigned int sample_freq = adc->sample_freq; 388 unsigned int spi_freq; 389 int ret; 390 391 dev_err(&indio_dev->dev, "enter %s\n", __func__); 392 /* If DFSDM is master on SPI, SPI freq can not be updated */ 393 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) 394 return -EPERM; 395 396 ret = kstrtoint(buf, 0, &spi_freq); 397 if (ret) 398 return ret; 399 400 if (!spi_freq) 401 return -EINVAL; 402 403 if (sample_freq) { 404 if (spi_freq % sample_freq) 405 dev_warn(&indio_dev->dev, 406 "Sampling rate not accurate (%d)\n", 407 spi_freq / (spi_freq / sample_freq)); 408 409 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / sample_freq)); 410 if (ret < 0) { 411 dev_err(&indio_dev->dev, 412 "No filter parameters that match!\n"); 413 return ret; 414 } 415 } 416 adc->spi_freq = spi_freq; 417 418 return len; 419 } 420 421 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, 422 const struct iio_chan_spec *chan, 423 bool dma) 424 { 425 struct regmap *regmap = adc->dfsdm->regmap; 426 int ret; 427 unsigned int dma_en = 0, cont_en = 0; 428 429 ret = stm32_dfsdm_start_channel(adc->dfsdm, chan->channel); 430 if (ret < 0) 431 return ret; 432 433 ret = stm32_dfsdm_filter_configure(adc->dfsdm, adc->fl_id, 434 chan->channel); 435 if (ret < 0) 436 goto stop_channels; 437 438 if (dma) { 439 /* Enable DMA transfer*/ 440 dma_en = DFSDM_CR1_RDMAEN(1); 441 /* Enable conversion triggered by SPI clock*/ 442 cont_en = DFSDM_CR1_RCONT(1); 443 } 444 /* Enable DMA transfer*/ 445 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 446 DFSDM_CR1_RDMAEN_MASK, dma_en); 447 if (ret < 0) 448 goto stop_channels; 449 450 /* Enable conversion triggered by SPI clock*/ 451 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 452 DFSDM_CR1_RCONT_MASK, cont_en); 453 if (ret < 0) 454 goto stop_channels; 455 456 ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id); 457 if (ret < 0) 458 goto stop_channels; 459 460 return 0; 461 462 stop_channels: 463 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 464 DFSDM_CR1_RDMAEN_MASK, 0); 465 466 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 467 DFSDM_CR1_RCONT_MASK, 0); 468 stm32_dfsdm_stop_channel(adc->dfsdm, chan->channel); 469 470 return ret; 471 } 472 473 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc, 474 const struct iio_chan_spec *chan) 475 { 476 struct regmap *regmap = adc->dfsdm->regmap; 477 478 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id); 479 480 /* Clean conversion options */ 481 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 482 DFSDM_CR1_RDMAEN_MASK, 0); 483 484 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 485 DFSDM_CR1_RCONT_MASK, 0); 486 487 stm32_dfsdm_stop_channel(adc->dfsdm, chan->channel); 488 } 489 490 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev, 491 unsigned int val) 492 { 493 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 494 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2; 495 496 /* 497 * DMA cyclic transfers are used, buffer is split into two periods. 498 * There should be : 499 * - always one buffer (period) DMA is working on 500 * - one buffer (period) driver pushed to ASoC side. 501 */ 502 watermark = min(watermark, val * (unsigned int)(sizeof(u32))); 503 adc->buf_sz = watermark * 2; 504 505 return 0; 506 } 507 508 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc) 509 { 510 struct dma_tx_state state; 511 enum dma_status status; 512 513 status = dmaengine_tx_status(adc->dma_chan, 514 adc->dma_chan->cookie, 515 &state); 516 if (status == DMA_IN_PROGRESS) { 517 /* Residue is size in bytes from end of buffer */ 518 unsigned int i = adc->buf_sz - state.residue; 519 unsigned int size; 520 521 /* Return available bytes */ 522 if (i >= adc->bufi) 523 size = i - adc->bufi; 524 else 525 size = adc->buf_sz + i - adc->bufi; 526 527 return size; 528 } 529 530 return 0; 531 } 532 533 static void stm32_dfsdm_audio_dma_buffer_done(void *data) 534 { 535 struct iio_dev *indio_dev = data; 536 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 537 int available = stm32_dfsdm_adc_dma_residue(adc); 538 size_t old_pos; 539 540 /* 541 * FIXME: In Kernel interface does not support cyclic DMA buffer,and 542 * offers only an interface to push data samples per samples. 543 * For this reason IIO buffer interface is not used and interface is 544 * bypassed using a private callback registered by ASoC. 545 * This should be a temporary solution waiting a cyclic DMA engine 546 * support in IIO. 547 */ 548 549 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__, 550 adc->bufi, available); 551 old_pos = adc->bufi; 552 553 while (available >= indio_dev->scan_bytes) { 554 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi]; 555 556 /* Mask 8 LSB that contains the channel ID */ 557 *buffer = (*buffer & 0xFFFFFF00) << 8; 558 available -= indio_dev->scan_bytes; 559 adc->bufi += indio_dev->scan_bytes; 560 if (adc->bufi >= adc->buf_sz) { 561 if (adc->cb) 562 adc->cb(&adc->rx_buf[old_pos], 563 adc->buf_sz - old_pos, adc->cb_priv); 564 adc->bufi = 0; 565 old_pos = 0; 566 } 567 } 568 if (adc->cb) 569 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos, 570 adc->cb_priv); 571 } 572 573 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev) 574 { 575 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 576 struct dma_async_tx_descriptor *desc; 577 dma_cookie_t cookie; 578 int ret; 579 580 if (!adc->dma_chan) 581 return -EINVAL; 582 583 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 584 adc->buf_sz, adc->buf_sz / 2); 585 586 /* Prepare a DMA cyclic transaction */ 587 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 588 adc->dma_buf, 589 adc->buf_sz, adc->buf_sz / 2, 590 DMA_DEV_TO_MEM, 591 DMA_PREP_INTERRUPT); 592 if (!desc) 593 return -EBUSY; 594 595 desc->callback = stm32_dfsdm_audio_dma_buffer_done; 596 desc->callback_param = indio_dev; 597 598 cookie = dmaengine_submit(desc); 599 ret = dma_submit_error(cookie); 600 if (ret) { 601 dmaengine_terminate_all(adc->dma_chan); 602 return ret; 603 } 604 605 /* Issue pending DMA requests */ 606 dma_async_issue_pending(adc->dma_chan); 607 608 return 0; 609 } 610 611 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev) 612 { 613 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 614 const struct iio_chan_spec *chan = &indio_dev->channels[0]; 615 int ret; 616 617 /* Reset adc buffer index */ 618 adc->bufi = 0; 619 620 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm); 621 if (ret < 0) 622 return ret; 623 624 ret = stm32_dfsdm_start_conv(adc, chan, true); 625 if (ret) { 626 dev_err(&indio_dev->dev, "Can't start conversion\n"); 627 goto stop_dfsdm; 628 } 629 630 if (adc->dma_chan) { 631 ret = stm32_dfsdm_adc_dma_start(indio_dev); 632 if (ret) { 633 dev_err(&indio_dev->dev, "Can't start DMA\n"); 634 goto err_stop_conv; 635 } 636 } 637 638 return 0; 639 640 err_stop_conv: 641 stm32_dfsdm_stop_conv(adc, chan); 642 stop_dfsdm: 643 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 644 645 return ret; 646 } 647 648 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev) 649 { 650 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 651 const struct iio_chan_spec *chan = &indio_dev->channels[0]; 652 653 if (adc->dma_chan) 654 dmaengine_terminate_all(adc->dma_chan); 655 656 stm32_dfsdm_stop_conv(adc, chan); 657 658 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 659 660 return 0; 661 } 662 663 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = { 664 .postenable = &stm32_dfsdm_postenable, 665 .predisable = &stm32_dfsdm_predisable, 666 }; 667 668 /** 669 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when 670 * DMA transfer period is achieved. 671 * 672 * @iio_dev: Handle to IIO device. 673 * @cb: Pointer to callback function: 674 * - data: pointer to data buffer 675 * - size: size in byte of the data buffer 676 * - private: pointer to consumer private structure. 677 * @private: Pointer to consumer private structure. 678 */ 679 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev, 680 int (*cb)(const void *data, size_t size, 681 void *private), 682 void *private) 683 { 684 struct stm32_dfsdm_adc *adc; 685 686 if (!iio_dev) 687 return -EINVAL; 688 adc = iio_priv(iio_dev); 689 690 adc->cb = cb; 691 adc->cb_priv = private; 692 693 return 0; 694 } 695 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb); 696 697 /** 698 * stm32_dfsdm_release_buff_cb - unregister buffer callback 699 * 700 * @iio_dev: Handle to IIO device. 701 */ 702 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev) 703 { 704 struct stm32_dfsdm_adc *adc; 705 706 if (!iio_dev) 707 return -EINVAL; 708 adc = iio_priv(iio_dev); 709 710 adc->cb = NULL; 711 adc->cb_priv = NULL; 712 713 return 0; 714 } 715 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb); 716 717 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev, 718 const struct iio_chan_spec *chan, int *res) 719 { 720 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 721 long timeout; 722 int ret; 723 724 reinit_completion(&adc->completion); 725 726 adc->buffer = res; 727 728 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm); 729 if (ret < 0) 730 return ret; 731 732 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 733 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1)); 734 if (ret < 0) 735 goto stop_dfsdm; 736 737 ret = stm32_dfsdm_start_conv(adc, chan, false); 738 if (ret < 0) { 739 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 740 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0)); 741 goto stop_dfsdm; 742 } 743 744 timeout = wait_for_completion_interruptible_timeout(&adc->completion, 745 DFSDM_TIMEOUT); 746 747 /* Mask IRQ for regular conversion achievement*/ 748 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 749 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0)); 750 751 if (timeout == 0) 752 ret = -ETIMEDOUT; 753 else if (timeout < 0) 754 ret = timeout; 755 else 756 ret = IIO_VAL_INT; 757 758 stm32_dfsdm_stop_conv(adc, chan); 759 760 stop_dfsdm: 761 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 762 763 return ret; 764 } 765 766 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev, 767 struct iio_chan_spec const *chan, 768 int val, int val2, long mask) 769 { 770 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 771 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; 772 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel]; 773 unsigned int spi_freq = adc->spi_freq; 774 int ret = -EINVAL; 775 776 switch (mask) { 777 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 778 ret = stm32_dfsdm_set_osrs(fl, 0, val); 779 if (!ret) 780 adc->oversamp = val; 781 782 return ret; 783 784 case IIO_CHAN_INFO_SAMP_FREQ: 785 if (!val) 786 return -EINVAL; 787 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) 788 spi_freq = adc->dfsdm->spi_master_freq; 789 790 if (spi_freq % val) 791 dev_warn(&indio_dev->dev, 792 "Sampling rate not accurate (%d)\n", 793 spi_freq / (spi_freq / val)); 794 795 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / val)); 796 if (ret < 0) { 797 dev_err(&indio_dev->dev, 798 "Not able to find parameter that match!\n"); 799 return ret; 800 } 801 adc->sample_freq = val; 802 803 return 0; 804 } 805 806 return -EINVAL; 807 } 808 809 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev, 810 struct iio_chan_spec const *chan, int *val, 811 int *val2, long mask) 812 { 813 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 814 int ret; 815 816 switch (mask) { 817 case IIO_CHAN_INFO_RAW: 818 ret = iio_hw_consumer_enable(adc->hwc); 819 if (ret < 0) { 820 dev_err(&indio_dev->dev, 821 "%s: IIO enable failed (channel %d)\n", 822 __func__, chan->channel); 823 return ret; 824 } 825 ret = stm32_dfsdm_single_conv(indio_dev, chan, val); 826 iio_hw_consumer_disable(adc->hwc); 827 if (ret < 0) { 828 dev_err(&indio_dev->dev, 829 "%s: Conversion failed (channel %d)\n", 830 __func__, chan->channel); 831 return ret; 832 } 833 return IIO_VAL_INT; 834 835 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 836 *val = adc->oversamp; 837 838 return IIO_VAL_INT; 839 840 case IIO_CHAN_INFO_SAMP_FREQ: 841 *val = adc->sample_freq; 842 843 return IIO_VAL_INT; 844 } 845 846 return -EINVAL; 847 } 848 849 static const struct iio_info stm32_dfsdm_info_audio = { 850 .hwfifo_set_watermark = stm32_dfsdm_set_watermark, 851 .read_raw = stm32_dfsdm_read_raw, 852 .write_raw = stm32_dfsdm_write_raw, 853 }; 854 855 static const struct iio_info stm32_dfsdm_info_adc = { 856 .read_raw = stm32_dfsdm_read_raw, 857 .write_raw = stm32_dfsdm_write_raw, 858 }; 859 860 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg) 861 { 862 struct stm32_dfsdm_adc *adc = arg; 863 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 864 struct regmap *regmap = adc->dfsdm->regmap; 865 unsigned int status, int_en; 866 867 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status); 868 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en); 869 870 if (status & DFSDM_ISR_REOCF_MASK) { 871 /* Read the data register clean the IRQ status */ 872 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer); 873 complete(&adc->completion); 874 } 875 876 if (status & DFSDM_ISR_ROVRF_MASK) { 877 if (int_en & DFSDM_CR2_ROVRIE_MASK) 878 dev_warn(&indio_dev->dev, "Overrun detected\n"); 879 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id), 880 DFSDM_ICR_CLRROVRF_MASK, 881 DFSDM_ICR_CLRROVRF_MASK); 882 } 883 884 return IRQ_HANDLED; 885 } 886 887 /* 888 * Define external info for SPI Frequency and audio sampling rate that can be 889 * configured by ASoC driver through consumer.h API 890 */ 891 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = { 892 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */ 893 { 894 .name = "spi_clk_freq", 895 .shared = IIO_SHARED_BY_TYPE, 896 .read = dfsdm_adc_audio_get_spiclk, 897 .write = dfsdm_adc_audio_set_spiclk, 898 }, 899 {}, 900 }; 901 902 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev) 903 { 904 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 905 906 if (adc->dma_chan) { 907 dma_free_coherent(adc->dma_chan->device->dev, 908 DFSDM_DMA_BUFFER_SIZE, 909 adc->rx_buf, adc->dma_buf); 910 dma_release_channel(adc->dma_chan); 911 } 912 } 913 914 static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev) 915 { 916 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 917 struct dma_slave_config config = { 918 .src_addr = (dma_addr_t)adc->dfsdm->phys_base + 919 DFSDM_RDATAR(adc->fl_id), 920 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 921 }; 922 int ret; 923 924 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx"); 925 if (!adc->dma_chan) 926 return -EINVAL; 927 928 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 929 DFSDM_DMA_BUFFER_SIZE, 930 &adc->dma_buf, GFP_KERNEL); 931 if (!adc->rx_buf) { 932 ret = -ENOMEM; 933 goto err_release; 934 } 935 936 ret = dmaengine_slave_config(adc->dma_chan, &config); 937 if (ret) 938 goto err_free; 939 940 return 0; 941 942 err_free: 943 dma_free_coherent(adc->dma_chan->device->dev, DFSDM_DMA_BUFFER_SIZE, 944 adc->rx_buf, adc->dma_buf); 945 err_release: 946 dma_release_channel(adc->dma_chan); 947 948 return ret; 949 } 950 951 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, 952 struct iio_chan_spec *ch) 953 { 954 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 955 int ret; 956 957 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch); 958 if (ret < 0) 959 return ret; 960 961 ch->type = IIO_VOLTAGE; 962 ch->indexed = 1; 963 964 /* 965 * IIO_CHAN_INFO_RAW: used to compute regular conversion 966 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling 967 */ 968 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 969 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); 970 971 if (adc->dev_data->type == DFSDM_AUDIO) { 972 ch->scan_type.sign = 's'; 973 ch->ext_info = dfsdm_adc_audio_ext_info; 974 } else { 975 ch->scan_type.sign = 'u'; 976 } 977 ch->scan_type.realbits = 24; 978 ch->scan_type.storagebits = 32; 979 980 return stm32_dfsdm_chan_configure(adc->dfsdm, 981 &adc->dfsdm->ch_list[ch->channel]); 982 } 983 984 static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev) 985 { 986 struct iio_chan_spec *ch; 987 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 988 struct stm32_dfsdm_channel *d_ch; 989 int ret; 990 991 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 992 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops; 993 994 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL); 995 if (!ch) 996 return -ENOMEM; 997 998 ch->scan_index = 0; 999 1000 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch); 1001 if (ret < 0) { 1002 dev_err(&indio_dev->dev, "Channels init failed\n"); 1003 return ret; 1004 } 1005 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ); 1006 1007 d_ch = &adc->dfsdm->ch_list[ch->channel]; 1008 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) 1009 adc->spi_freq = adc->dfsdm->spi_master_freq; 1010 1011 indio_dev->num_channels = 1; 1012 indio_dev->channels = ch; 1013 1014 return stm32_dfsdm_dma_request(indio_dev); 1015 } 1016 1017 static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev) 1018 { 1019 struct iio_chan_spec *ch; 1020 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1021 int num_ch; 1022 int ret, chan_idx; 1023 1024 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING; 1025 ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0, 1026 adc->oversamp); 1027 if (ret < 0) 1028 return ret; 1029 1030 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node, 1031 "st,adc-channels"); 1032 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) { 1033 dev_err(&indio_dev->dev, "Bad st,adc-channels\n"); 1034 return num_ch < 0 ? num_ch : -EINVAL; 1035 } 1036 1037 /* Bind to SD modulator IIO device */ 1038 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev); 1039 if (IS_ERR(adc->hwc)) 1040 return -EPROBE_DEFER; 1041 1042 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch), 1043 GFP_KERNEL); 1044 if (!ch) 1045 return -ENOMEM; 1046 1047 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) { 1048 ch[chan_idx].scan_index = chan_idx; 1049 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]); 1050 if (ret < 0) { 1051 dev_err(&indio_dev->dev, "Channels init failed\n"); 1052 return ret; 1053 } 1054 } 1055 1056 indio_dev->num_channels = num_ch; 1057 indio_dev->channels = ch; 1058 1059 init_completion(&adc->completion); 1060 1061 return 0; 1062 } 1063 1064 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = { 1065 .type = DFSDM_IIO, 1066 .init = stm32_dfsdm_adc_init, 1067 }; 1068 1069 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = { 1070 .type = DFSDM_AUDIO, 1071 .init = stm32_dfsdm_audio_init, 1072 }; 1073 1074 static const struct of_device_id stm32_dfsdm_adc_match[] = { 1075 { 1076 .compatible = "st,stm32-dfsdm-adc", 1077 .data = &stm32h7_dfsdm_adc_data, 1078 }, 1079 { 1080 .compatible = "st,stm32-dfsdm-dmic", 1081 .data = &stm32h7_dfsdm_audio_data, 1082 }, 1083 {} 1084 }; 1085 1086 static int stm32_dfsdm_adc_probe(struct platform_device *pdev) 1087 { 1088 struct device *dev = &pdev->dev; 1089 struct stm32_dfsdm_adc *adc; 1090 struct device_node *np = dev->of_node; 1091 const struct stm32_dfsdm_dev_data *dev_data; 1092 struct iio_dev *iio; 1093 char *name; 1094 int ret, irq, val; 1095 1096 1097 dev_data = of_device_get_match_data(dev); 1098 iio = devm_iio_device_alloc(dev, sizeof(*adc)); 1099 if (!iio) { 1100 dev_err(dev, "%s: Failed to allocate IIO\n", __func__); 1101 return -ENOMEM; 1102 } 1103 1104 adc = iio_priv(iio); 1105 adc->dfsdm = dev_get_drvdata(dev->parent); 1106 1107 iio->dev.parent = dev; 1108 iio->dev.of_node = np; 1109 iio->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1110 1111 platform_set_drvdata(pdev, adc); 1112 1113 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id); 1114 if (ret != 0) { 1115 dev_err(dev, "Missing reg property\n"); 1116 return -EINVAL; 1117 } 1118 1119 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL); 1120 if (!name) 1121 return -ENOMEM; 1122 if (dev_data->type == DFSDM_AUDIO) { 1123 iio->info = &stm32_dfsdm_info_audio; 1124 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id); 1125 } else { 1126 iio->info = &stm32_dfsdm_info_adc; 1127 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id); 1128 } 1129 iio->name = name; 1130 1131 /* 1132 * In a first step IRQs generated for channels are not treated. 1133 * So IRQ associated to filter instance 0 is dedicated to the Filter 0. 1134 */ 1135 irq = platform_get_irq(pdev, 0); 1136 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq, 1137 0, pdev->name, adc); 1138 if (ret < 0) { 1139 dev_err(dev, "Failed to request IRQ\n"); 1140 return ret; 1141 } 1142 1143 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val); 1144 if (ret < 0) { 1145 dev_err(dev, "Failed to set filter order\n"); 1146 return ret; 1147 } 1148 1149 adc->dfsdm->fl_list[adc->fl_id].ford = val; 1150 1151 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val); 1152 if (!ret) 1153 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val; 1154 1155 adc->dev_data = dev_data; 1156 ret = dev_data->init(iio); 1157 if (ret < 0) 1158 return ret; 1159 1160 ret = iio_device_register(iio); 1161 if (ret < 0) 1162 goto err_cleanup; 1163 1164 dev_err(dev, "of_platform_populate\n"); 1165 if (dev_data->type == DFSDM_AUDIO) { 1166 ret = of_platform_populate(np, NULL, NULL, dev); 1167 if (ret < 0) { 1168 dev_err(dev, "Failed to find an audio DAI\n"); 1169 goto err_unregister; 1170 } 1171 } 1172 1173 return 0; 1174 1175 err_unregister: 1176 iio_device_unregister(iio); 1177 err_cleanup: 1178 stm32_dfsdm_dma_release(iio); 1179 1180 return ret; 1181 } 1182 1183 static int stm32_dfsdm_adc_remove(struct platform_device *pdev) 1184 { 1185 struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev); 1186 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1187 1188 if (adc->dev_data->type == DFSDM_AUDIO) 1189 of_platform_depopulate(&pdev->dev); 1190 iio_device_unregister(indio_dev); 1191 stm32_dfsdm_dma_release(indio_dev); 1192 1193 return 0; 1194 } 1195 1196 static struct platform_driver stm32_dfsdm_adc_driver = { 1197 .driver = { 1198 .name = "stm32-dfsdm-adc", 1199 .of_match_table = stm32_dfsdm_adc_match, 1200 }, 1201 .probe = stm32_dfsdm_adc_probe, 1202 .remove = stm32_dfsdm_adc_remove, 1203 }; 1204 module_platform_driver(stm32_dfsdm_adc_driver); 1205 1206 MODULE_DESCRIPTION("STM32 sigma delta ADC"); 1207 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>"); 1208 MODULE_LICENSE("GPL v2"); 1209