1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is the ADC part of the STM32 DFSDM driver 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>. 7 */ 8 9 #include <linux/dmaengine.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/iio/buffer.h> 13 #include <linux/iio/hw-consumer.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 22 #include "stm32-dfsdm.h" 23 24 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE) 25 26 /* Conversion timeout */ 27 #define DFSDM_TIMEOUT_US 100000 28 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000)) 29 30 /* Oversampling attribute default */ 31 #define DFSDM_DEFAULT_OVERSAMPLING 100 32 33 /* Oversampling max values */ 34 #define DFSDM_MAX_INT_OVERSAMPLING 256 35 #define DFSDM_MAX_FL_OVERSAMPLING 1024 36 37 /* Max sample resolutions */ 38 #define DFSDM_MAX_RES BIT(31) 39 #define DFSDM_DATA_RES BIT(23) 40 41 enum sd_converter_type { 42 DFSDM_AUDIO, 43 DFSDM_IIO, 44 }; 45 46 struct stm32_dfsdm_dev_data { 47 int type; 48 int (*init)(struct iio_dev *indio_dev); 49 unsigned int num_channels; 50 const struct regmap_config *regmap_cfg; 51 }; 52 53 struct stm32_dfsdm_adc { 54 struct stm32_dfsdm *dfsdm; 55 const struct stm32_dfsdm_dev_data *dev_data; 56 unsigned int fl_id; 57 unsigned int ch_id; 58 59 /* ADC specific */ 60 unsigned int oversamp; 61 struct iio_hw_consumer *hwc; 62 struct completion completion; 63 u32 *buffer; 64 65 /* Audio specific */ 66 unsigned int spi_freq; /* SPI bus clock frequency */ 67 unsigned int sample_freq; /* Sample frequency after filter decimation */ 68 int (*cb)(const void *data, size_t size, void *cb_priv); 69 void *cb_priv; 70 71 /* DMA */ 72 u8 *rx_buf; 73 unsigned int bufi; /* Buffer current position */ 74 unsigned int buf_sz; /* Buffer size */ 75 struct dma_chan *dma_chan; 76 dma_addr_t dma_buf; 77 }; 78 79 struct stm32_dfsdm_str2field { 80 const char *name; 81 unsigned int val; 82 }; 83 84 /* DFSDM channel serial interface type */ 85 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = { 86 { "SPI_R", 0 }, /* SPI with data on rising edge */ 87 { "SPI_F", 1 }, /* SPI with data on falling edge */ 88 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */ 89 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */ 90 {}, 91 }; 92 93 /* DFSDM channel clock source */ 94 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = { 95 /* External SPI clock (CLKIN x) */ 96 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL }, 97 /* Internal SPI clock (CLKOUT) */ 98 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL }, 99 /* Internal SPI clock divided by 2 (falling edge) */ 100 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING }, 101 /* Internal SPI clock divided by 2 (falling edge) */ 102 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING }, 103 {}, 104 }; 105 106 static int stm32_dfsdm_str2val(const char *str, 107 const struct stm32_dfsdm_str2field *list) 108 { 109 const struct stm32_dfsdm_str2field *p = list; 110 111 for (p = list; p && p->name; p++) 112 if (!strcmp(p->name, str)) 113 return p->val; 114 115 return -EINVAL; 116 } 117 118 static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl, 119 unsigned int fast, unsigned int oversamp) 120 { 121 unsigned int i, d, fosr, iosr; 122 u64 res; 123 s64 delta; 124 unsigned int m = 1; /* multiplication factor */ 125 unsigned int p = fl->ford; /* filter order (ford) */ 126 127 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp); 128 /* 129 * This function tries to compute filter oversampling and integrator 130 * oversampling, base on oversampling ratio requested by user. 131 * 132 * Decimation d depends on the filter order and the oversampling ratios. 133 * ford: filter order 134 * fosr: filter over sampling ratio 135 * iosr: integrator over sampling ratio 136 */ 137 if (fl->ford == DFSDM_FASTSINC_ORDER) { 138 m = 2; 139 p = 2; 140 } 141 142 /* 143 * Look for filter and integrator oversampling ratios which allows 144 * to reach 24 bits data output resolution. 145 * Leave as soon as if exact resolution if reached. 146 * Otherwise the higher resolution below 32 bits is kept. 147 */ 148 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) { 149 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) { 150 if (fast) 151 d = fosr * iosr; 152 else if (fl->ford == DFSDM_FASTSINC_ORDER) 153 d = fosr * (iosr + 3) + 2; 154 else 155 d = fosr * (iosr - 1 + p) + p; 156 157 if (d > oversamp) 158 break; 159 else if (d != oversamp) 160 continue; 161 /* 162 * Check resolution (limited to signed 32 bits) 163 * res <= 2^31 164 * Sincx filters: 165 * res = m * fosr^p x iosr (with m=1, p=ford) 166 * FastSinc filter 167 * res = m * fosr^p x iosr (with m=2, p=2) 168 */ 169 res = fosr; 170 for (i = p - 1; i > 0; i--) { 171 res = res * (u64)fosr; 172 if (res > DFSDM_MAX_RES) 173 break; 174 } 175 if (res > DFSDM_MAX_RES) 176 continue; 177 res = res * (u64)m * (u64)iosr; 178 if (res > DFSDM_MAX_RES) 179 continue; 180 181 delta = res - DFSDM_DATA_RES; 182 183 if (res >= fl->res) { 184 fl->res = res; 185 fl->fosr = fosr; 186 fl->iosr = iosr; 187 fl->fast = fast; 188 pr_debug("%s: fosr = %d, iosr = %d\n", 189 __func__, fl->fosr, fl->iosr); 190 } 191 192 if (!delta) 193 return 0; 194 } 195 } 196 197 if (!fl->fosr) 198 return -EINVAL; 199 200 return 0; 201 } 202 203 static int stm32_dfsdm_start_channel(struct stm32_dfsdm *dfsdm, 204 unsigned int ch_id) 205 { 206 return regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id), 207 DFSDM_CHCFGR1_CHEN_MASK, 208 DFSDM_CHCFGR1_CHEN(1)); 209 } 210 211 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm *dfsdm, 212 unsigned int ch_id) 213 { 214 regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id), 215 DFSDM_CHCFGR1_CHEN_MASK, DFSDM_CHCFGR1_CHEN(0)); 216 } 217 218 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm, 219 struct stm32_dfsdm_channel *ch) 220 { 221 unsigned int id = ch->id; 222 struct regmap *regmap = dfsdm->regmap; 223 int ret; 224 225 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 226 DFSDM_CHCFGR1_SITP_MASK, 227 DFSDM_CHCFGR1_SITP(ch->type)); 228 if (ret < 0) 229 return ret; 230 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 231 DFSDM_CHCFGR1_SPICKSEL_MASK, 232 DFSDM_CHCFGR1_SPICKSEL(ch->src)); 233 if (ret < 0) 234 return ret; 235 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 236 DFSDM_CHCFGR1_CHINSEL_MASK, 237 DFSDM_CHCFGR1_CHINSEL(ch->alt_si)); 238 } 239 240 static int stm32_dfsdm_start_filter(struct stm32_dfsdm *dfsdm, 241 unsigned int fl_id) 242 { 243 int ret; 244 245 /* Enable filter */ 246 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 247 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1)); 248 if (ret < 0) 249 return ret; 250 251 /* Start conversion */ 252 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 253 DFSDM_CR1_RSWSTART_MASK, 254 DFSDM_CR1_RSWSTART(1)); 255 } 256 257 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm, unsigned int fl_id) 258 { 259 /* Disable conversion */ 260 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 261 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0)); 262 } 263 264 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm *dfsdm, 265 unsigned int fl_id, unsigned int ch_id) 266 { 267 struct regmap *regmap = dfsdm->regmap; 268 struct stm32_dfsdm_filter *fl = &dfsdm->fl_list[fl_id]; 269 int ret; 270 271 /* Average integrator oversampling */ 272 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK, 273 DFSDM_FCR_IOSR(fl->iosr - 1)); 274 if (ret) 275 return ret; 276 277 /* Filter order and Oversampling */ 278 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK, 279 DFSDM_FCR_FOSR(fl->fosr - 1)); 280 if (ret) 281 return ret; 282 283 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK, 284 DFSDM_FCR_FORD(fl->ford)); 285 if (ret) 286 return ret; 287 288 /* No scan mode supported for the moment */ 289 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_RCH_MASK, 290 DFSDM_CR1_RCH(ch_id)); 291 if (ret) 292 return ret; 293 294 return regmap_update_bits(regmap, DFSDM_CR1(fl_id), 295 DFSDM_CR1_RSYNC_MASK, 296 DFSDM_CR1_RSYNC(fl->sync_mode)); 297 } 298 299 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm, 300 struct iio_dev *indio_dev, 301 struct iio_chan_spec *ch) 302 { 303 struct stm32_dfsdm_channel *df_ch; 304 const char *of_str; 305 int chan_idx = ch->scan_index; 306 int ret, val; 307 308 ret = of_property_read_u32_index(indio_dev->dev.of_node, 309 "st,adc-channels", chan_idx, 310 &ch->channel); 311 if (ret < 0) { 312 dev_err(&indio_dev->dev, 313 " Error parsing 'st,adc-channels' for idx %d\n", 314 chan_idx); 315 return ret; 316 } 317 if (ch->channel >= dfsdm->num_chs) { 318 dev_err(&indio_dev->dev, 319 " Error bad channel number %d (max = %d)\n", 320 ch->channel, dfsdm->num_chs); 321 return -EINVAL; 322 } 323 324 ret = of_property_read_string_index(indio_dev->dev.of_node, 325 "st,adc-channel-names", chan_idx, 326 &ch->datasheet_name); 327 if (ret < 0) { 328 dev_err(&indio_dev->dev, 329 " Error parsing 'st,adc-channel-names' for idx %d\n", 330 chan_idx); 331 return ret; 332 } 333 334 df_ch = &dfsdm->ch_list[ch->channel]; 335 df_ch->id = ch->channel; 336 337 ret = of_property_read_string_index(indio_dev->dev.of_node, 338 "st,adc-channel-types", chan_idx, 339 &of_str); 340 if (!ret) { 341 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type); 342 if (val < 0) 343 return val; 344 } else { 345 val = 0; 346 } 347 df_ch->type = val; 348 349 ret = of_property_read_string_index(indio_dev->dev.of_node, 350 "st,adc-channel-clk-src", chan_idx, 351 &of_str); 352 if (!ret) { 353 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src); 354 if (val < 0) 355 return val; 356 } else { 357 val = 0; 358 } 359 df_ch->src = val; 360 361 ret = of_property_read_u32_index(indio_dev->dev.of_node, 362 "st,adc-alt-channel", chan_idx, 363 &df_ch->alt_si); 364 if (ret < 0) 365 df_ch->alt_si = 0; 366 367 return 0; 368 } 369 370 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev, 371 uintptr_t priv, 372 const struct iio_chan_spec *chan, 373 char *buf) 374 { 375 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 376 377 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq); 378 } 379 380 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev, 381 uintptr_t priv, 382 const struct iio_chan_spec *chan, 383 const char *buf, size_t len) 384 { 385 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 386 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; 387 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[adc->ch_id]; 388 unsigned int sample_freq = adc->sample_freq; 389 unsigned int spi_freq; 390 int ret; 391 392 dev_err(&indio_dev->dev, "enter %s\n", __func__); 393 /* If DFSDM is master on SPI, SPI freq can not be updated */ 394 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) 395 return -EPERM; 396 397 ret = kstrtoint(buf, 0, &spi_freq); 398 if (ret) 399 return ret; 400 401 if (!spi_freq) 402 return -EINVAL; 403 404 if (sample_freq) { 405 if (spi_freq % sample_freq) 406 dev_warn(&indio_dev->dev, 407 "Sampling rate not accurate (%d)\n", 408 spi_freq / (spi_freq / sample_freq)); 409 410 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / sample_freq)); 411 if (ret < 0) { 412 dev_err(&indio_dev->dev, 413 "No filter parameters that match!\n"); 414 return ret; 415 } 416 } 417 adc->spi_freq = spi_freq; 418 419 return len; 420 } 421 422 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, bool dma) 423 { 424 struct regmap *regmap = adc->dfsdm->regmap; 425 int ret; 426 unsigned int dma_en = 0, cont_en = 0; 427 428 ret = stm32_dfsdm_start_channel(adc->dfsdm, adc->ch_id); 429 if (ret < 0) 430 return ret; 431 432 ret = stm32_dfsdm_filter_configure(adc->dfsdm, adc->fl_id, 433 adc->ch_id); 434 if (ret < 0) 435 goto stop_channels; 436 437 if (dma) { 438 /* Enable DMA transfer*/ 439 dma_en = DFSDM_CR1_RDMAEN(1); 440 /* Enable conversion triggered by SPI clock*/ 441 cont_en = DFSDM_CR1_RCONT(1); 442 } 443 /* Enable DMA transfer*/ 444 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 445 DFSDM_CR1_RDMAEN_MASK, dma_en); 446 if (ret < 0) 447 goto stop_channels; 448 449 /* Enable conversion triggered by SPI clock*/ 450 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 451 DFSDM_CR1_RCONT_MASK, cont_en); 452 if (ret < 0) 453 goto stop_channels; 454 455 ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id); 456 if (ret < 0) 457 goto stop_channels; 458 459 return 0; 460 461 stop_channels: 462 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 463 DFSDM_CR1_RDMAEN_MASK, 0); 464 465 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 466 DFSDM_CR1_RCONT_MASK, 0); 467 stm32_dfsdm_stop_channel(adc->dfsdm, adc->fl_id); 468 469 return ret; 470 } 471 472 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc) 473 { 474 struct regmap *regmap = adc->dfsdm->regmap; 475 476 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id); 477 478 /* Clean conversion options */ 479 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 480 DFSDM_CR1_RDMAEN_MASK, 0); 481 482 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 483 DFSDM_CR1_RCONT_MASK, 0); 484 485 stm32_dfsdm_stop_channel(adc->dfsdm, adc->ch_id); 486 } 487 488 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev, 489 unsigned int val) 490 { 491 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 492 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2; 493 494 /* 495 * DMA cyclic transfers are used, buffer is split into two periods. 496 * There should be : 497 * - always one buffer (period) DMA is working on 498 * - one buffer (period) driver pushed to ASoC side. 499 */ 500 watermark = min(watermark, val * (unsigned int)(sizeof(u32))); 501 adc->buf_sz = watermark * 2; 502 503 return 0; 504 } 505 506 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc) 507 { 508 struct dma_tx_state state; 509 enum dma_status status; 510 511 status = dmaengine_tx_status(adc->dma_chan, 512 adc->dma_chan->cookie, 513 &state); 514 if (status == DMA_IN_PROGRESS) { 515 /* Residue is size in bytes from end of buffer */ 516 unsigned int i = adc->buf_sz - state.residue; 517 unsigned int size; 518 519 /* Return available bytes */ 520 if (i >= adc->bufi) 521 size = i - adc->bufi; 522 else 523 size = adc->buf_sz + i - adc->bufi; 524 525 return size; 526 } 527 528 return 0; 529 } 530 531 static void stm32_dfsdm_audio_dma_buffer_done(void *data) 532 { 533 struct iio_dev *indio_dev = data; 534 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 535 int available = stm32_dfsdm_adc_dma_residue(adc); 536 size_t old_pos; 537 538 /* 539 * FIXME: In Kernel interface does not support cyclic DMA buffer,and 540 * offers only an interface to push data samples per samples. 541 * For this reason IIO buffer interface is not used and interface is 542 * bypassed using a private callback registered by ASoC. 543 * This should be a temporary solution waiting a cyclic DMA engine 544 * support in IIO. 545 */ 546 547 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__, 548 adc->bufi, available); 549 old_pos = adc->bufi; 550 551 while (available >= indio_dev->scan_bytes) { 552 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi]; 553 554 /* Mask 8 LSB that contains the channel ID */ 555 *buffer = (*buffer & 0xFFFFFF00) << 8; 556 available -= indio_dev->scan_bytes; 557 adc->bufi += indio_dev->scan_bytes; 558 if (adc->bufi >= adc->buf_sz) { 559 if (adc->cb) 560 adc->cb(&adc->rx_buf[old_pos], 561 adc->buf_sz - old_pos, adc->cb_priv); 562 adc->bufi = 0; 563 old_pos = 0; 564 } 565 } 566 if (adc->cb) 567 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos, 568 adc->cb_priv); 569 } 570 571 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev) 572 { 573 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 574 struct dma_async_tx_descriptor *desc; 575 dma_cookie_t cookie; 576 int ret; 577 578 if (!adc->dma_chan) 579 return -EINVAL; 580 581 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 582 adc->buf_sz, adc->buf_sz / 2); 583 584 /* Prepare a DMA cyclic transaction */ 585 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 586 adc->dma_buf, 587 adc->buf_sz, adc->buf_sz / 2, 588 DMA_DEV_TO_MEM, 589 DMA_PREP_INTERRUPT); 590 if (!desc) 591 return -EBUSY; 592 593 desc->callback = stm32_dfsdm_audio_dma_buffer_done; 594 desc->callback_param = indio_dev; 595 596 cookie = dmaengine_submit(desc); 597 ret = dma_submit_error(cookie); 598 if (ret) { 599 dmaengine_terminate_all(adc->dma_chan); 600 return ret; 601 } 602 603 /* Issue pending DMA requests */ 604 dma_async_issue_pending(adc->dma_chan); 605 606 return 0; 607 } 608 609 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev) 610 { 611 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 612 int ret; 613 614 /* Reset adc buffer index */ 615 adc->bufi = 0; 616 617 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm); 618 if (ret < 0) 619 return ret; 620 621 ret = stm32_dfsdm_start_conv(adc, true); 622 if (ret) { 623 dev_err(&indio_dev->dev, "Can't start conversion\n"); 624 goto stop_dfsdm; 625 } 626 627 if (adc->dma_chan) { 628 ret = stm32_dfsdm_adc_dma_start(indio_dev); 629 if (ret) { 630 dev_err(&indio_dev->dev, "Can't start DMA\n"); 631 goto err_stop_conv; 632 } 633 } 634 635 return 0; 636 637 err_stop_conv: 638 stm32_dfsdm_stop_conv(adc); 639 stop_dfsdm: 640 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 641 642 return ret; 643 } 644 645 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev) 646 { 647 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 648 649 if (adc->dma_chan) 650 dmaengine_terminate_all(adc->dma_chan); 651 652 stm32_dfsdm_stop_conv(adc); 653 654 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 655 656 return 0; 657 } 658 659 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = { 660 .postenable = &stm32_dfsdm_postenable, 661 .predisable = &stm32_dfsdm_predisable, 662 }; 663 664 /** 665 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when 666 * DMA transfer period is achieved. 667 * 668 * @iio_dev: Handle to IIO device. 669 * @cb: Pointer to callback function: 670 * - data: pointer to data buffer 671 * - size: size in byte of the data buffer 672 * - private: pointer to consumer private structure. 673 * @private: Pointer to consumer private structure. 674 */ 675 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev, 676 int (*cb)(const void *data, size_t size, 677 void *private), 678 void *private) 679 { 680 struct stm32_dfsdm_adc *adc; 681 682 if (!iio_dev) 683 return -EINVAL; 684 adc = iio_priv(iio_dev); 685 686 adc->cb = cb; 687 adc->cb_priv = private; 688 689 return 0; 690 } 691 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb); 692 693 /** 694 * stm32_dfsdm_release_buff_cb - unregister buffer callback 695 * 696 * @iio_dev: Handle to IIO device. 697 */ 698 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev) 699 { 700 struct stm32_dfsdm_adc *adc; 701 702 if (!iio_dev) 703 return -EINVAL; 704 adc = iio_priv(iio_dev); 705 706 adc->cb = NULL; 707 adc->cb_priv = NULL; 708 709 return 0; 710 } 711 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb); 712 713 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev, 714 const struct iio_chan_spec *chan, int *res) 715 { 716 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 717 long timeout; 718 int ret; 719 720 reinit_completion(&adc->completion); 721 722 adc->buffer = res; 723 724 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm); 725 if (ret < 0) 726 return ret; 727 728 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 729 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1)); 730 if (ret < 0) 731 goto stop_dfsdm; 732 733 ret = stm32_dfsdm_start_conv(adc, false); 734 if (ret < 0) { 735 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 736 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0)); 737 goto stop_dfsdm; 738 } 739 740 timeout = wait_for_completion_interruptible_timeout(&adc->completion, 741 DFSDM_TIMEOUT); 742 743 /* Mask IRQ for regular conversion achievement*/ 744 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 745 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0)); 746 747 if (timeout == 0) 748 ret = -ETIMEDOUT; 749 else if (timeout < 0) 750 ret = timeout; 751 else 752 ret = IIO_VAL_INT; 753 754 stm32_dfsdm_stop_conv(adc); 755 756 stop_dfsdm: 757 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 758 759 return ret; 760 } 761 762 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev, 763 struct iio_chan_spec const *chan, 764 int val, int val2, long mask) 765 { 766 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 767 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; 768 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[adc->ch_id]; 769 unsigned int spi_freq = adc->spi_freq; 770 int ret = -EINVAL; 771 772 switch (mask) { 773 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 774 ret = stm32_dfsdm_set_osrs(fl, 0, val); 775 if (!ret) 776 adc->oversamp = val; 777 778 return ret; 779 780 case IIO_CHAN_INFO_SAMP_FREQ: 781 if (!val) 782 return -EINVAL; 783 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) 784 spi_freq = adc->dfsdm->spi_master_freq; 785 786 if (spi_freq % val) 787 dev_warn(&indio_dev->dev, 788 "Sampling rate not accurate (%d)\n", 789 spi_freq / (spi_freq / val)); 790 791 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / val)); 792 if (ret < 0) { 793 dev_err(&indio_dev->dev, 794 "Not able to find parameter that match!\n"); 795 return ret; 796 } 797 adc->sample_freq = val; 798 799 return 0; 800 } 801 802 return -EINVAL; 803 } 804 805 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev, 806 struct iio_chan_spec const *chan, int *val, 807 int *val2, long mask) 808 { 809 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 810 int ret; 811 812 switch (mask) { 813 case IIO_CHAN_INFO_RAW: 814 ret = iio_hw_consumer_enable(adc->hwc); 815 if (ret < 0) { 816 dev_err(&indio_dev->dev, 817 "%s: IIO enable failed (channel %d)\n", 818 __func__, chan->channel); 819 return ret; 820 } 821 ret = stm32_dfsdm_single_conv(indio_dev, chan, val); 822 iio_hw_consumer_disable(adc->hwc); 823 if (ret < 0) { 824 dev_err(&indio_dev->dev, 825 "%s: Conversion failed (channel %d)\n", 826 __func__, chan->channel); 827 return ret; 828 } 829 return IIO_VAL_INT; 830 831 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 832 *val = adc->oversamp; 833 834 return IIO_VAL_INT; 835 836 case IIO_CHAN_INFO_SAMP_FREQ: 837 *val = adc->sample_freq; 838 839 return IIO_VAL_INT; 840 } 841 842 return -EINVAL; 843 } 844 845 static const struct iio_info stm32_dfsdm_info_audio = { 846 .hwfifo_set_watermark = stm32_dfsdm_set_watermark, 847 .read_raw = stm32_dfsdm_read_raw, 848 .write_raw = stm32_dfsdm_write_raw, 849 }; 850 851 static const struct iio_info stm32_dfsdm_info_adc = { 852 .read_raw = stm32_dfsdm_read_raw, 853 .write_raw = stm32_dfsdm_write_raw, 854 }; 855 856 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg) 857 { 858 struct stm32_dfsdm_adc *adc = arg; 859 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 860 struct regmap *regmap = adc->dfsdm->regmap; 861 unsigned int status, int_en; 862 863 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status); 864 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en); 865 866 if (status & DFSDM_ISR_REOCF_MASK) { 867 /* Read the data register clean the IRQ status */ 868 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer); 869 complete(&adc->completion); 870 } 871 872 if (status & DFSDM_ISR_ROVRF_MASK) { 873 if (int_en & DFSDM_CR2_ROVRIE_MASK) 874 dev_warn(&indio_dev->dev, "Overrun detected\n"); 875 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id), 876 DFSDM_ICR_CLRROVRF_MASK, 877 DFSDM_ICR_CLRROVRF_MASK); 878 } 879 880 return IRQ_HANDLED; 881 } 882 883 /* 884 * Define external info for SPI Frequency and audio sampling rate that can be 885 * configured by ASoC driver through consumer.h API 886 */ 887 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = { 888 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */ 889 { 890 .name = "spi_clk_freq", 891 .shared = IIO_SHARED_BY_TYPE, 892 .read = dfsdm_adc_audio_get_spiclk, 893 .write = dfsdm_adc_audio_set_spiclk, 894 }, 895 {}, 896 }; 897 898 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev) 899 { 900 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 901 902 if (adc->dma_chan) { 903 dma_free_coherent(adc->dma_chan->device->dev, 904 DFSDM_DMA_BUFFER_SIZE, 905 adc->rx_buf, adc->dma_buf); 906 dma_release_channel(adc->dma_chan); 907 } 908 } 909 910 static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev) 911 { 912 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 913 struct dma_slave_config config = { 914 .src_addr = (dma_addr_t)adc->dfsdm->phys_base + 915 DFSDM_RDATAR(adc->fl_id), 916 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 917 }; 918 int ret; 919 920 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx"); 921 if (!adc->dma_chan) 922 return -EINVAL; 923 924 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 925 DFSDM_DMA_BUFFER_SIZE, 926 &adc->dma_buf, GFP_KERNEL); 927 if (!adc->rx_buf) { 928 ret = -ENOMEM; 929 goto err_release; 930 } 931 932 ret = dmaengine_slave_config(adc->dma_chan, &config); 933 if (ret) 934 goto err_free; 935 936 return 0; 937 938 err_free: 939 dma_free_coherent(adc->dma_chan->device->dev, DFSDM_DMA_BUFFER_SIZE, 940 adc->rx_buf, adc->dma_buf); 941 err_release: 942 dma_release_channel(adc->dma_chan); 943 944 return ret; 945 } 946 947 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, 948 struct iio_chan_spec *ch) 949 { 950 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 951 int ret; 952 953 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch); 954 if (ret < 0) 955 return ret; 956 957 ch->type = IIO_VOLTAGE; 958 ch->indexed = 1; 959 960 /* 961 * IIO_CHAN_INFO_RAW: used to compute regular conversion 962 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling 963 */ 964 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 965 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); 966 967 if (adc->dev_data->type == DFSDM_AUDIO) { 968 ch->scan_type.sign = 's'; 969 ch->ext_info = dfsdm_adc_audio_ext_info; 970 } else { 971 ch->scan_type.sign = 'u'; 972 } 973 ch->scan_type.realbits = 24; 974 ch->scan_type.storagebits = 32; 975 adc->ch_id = ch->channel; 976 977 return stm32_dfsdm_chan_configure(adc->dfsdm, 978 &adc->dfsdm->ch_list[ch->channel]); 979 } 980 981 static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev) 982 { 983 struct iio_chan_spec *ch; 984 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 985 struct stm32_dfsdm_channel *d_ch; 986 int ret; 987 988 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 989 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops; 990 991 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL); 992 if (!ch) 993 return -ENOMEM; 994 995 ch->scan_index = 0; 996 997 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch); 998 if (ret < 0) { 999 dev_err(&indio_dev->dev, "Channels init failed\n"); 1000 return ret; 1001 } 1002 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ); 1003 1004 d_ch = &adc->dfsdm->ch_list[adc->ch_id]; 1005 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) 1006 adc->spi_freq = adc->dfsdm->spi_master_freq; 1007 1008 indio_dev->num_channels = 1; 1009 indio_dev->channels = ch; 1010 1011 return stm32_dfsdm_dma_request(indio_dev); 1012 } 1013 1014 static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev) 1015 { 1016 struct iio_chan_spec *ch; 1017 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1018 int num_ch; 1019 int ret, chan_idx; 1020 1021 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING; 1022 ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0, 1023 adc->oversamp); 1024 if (ret < 0) 1025 return ret; 1026 1027 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node, 1028 "st,adc-channels"); 1029 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) { 1030 dev_err(&indio_dev->dev, "Bad st,adc-channels\n"); 1031 return num_ch < 0 ? num_ch : -EINVAL; 1032 } 1033 1034 /* Bind to SD modulator IIO device */ 1035 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev); 1036 if (IS_ERR(adc->hwc)) 1037 return -EPROBE_DEFER; 1038 1039 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch), 1040 GFP_KERNEL); 1041 if (!ch) 1042 return -ENOMEM; 1043 1044 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) { 1045 ch->scan_index = chan_idx; 1046 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch); 1047 if (ret < 0) { 1048 dev_err(&indio_dev->dev, "Channels init failed\n"); 1049 return ret; 1050 } 1051 } 1052 1053 indio_dev->num_channels = num_ch; 1054 indio_dev->channels = ch; 1055 1056 init_completion(&adc->completion); 1057 1058 return 0; 1059 } 1060 1061 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = { 1062 .type = DFSDM_IIO, 1063 .init = stm32_dfsdm_adc_init, 1064 }; 1065 1066 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = { 1067 .type = DFSDM_AUDIO, 1068 .init = stm32_dfsdm_audio_init, 1069 }; 1070 1071 static const struct of_device_id stm32_dfsdm_adc_match[] = { 1072 { 1073 .compatible = "st,stm32-dfsdm-adc", 1074 .data = &stm32h7_dfsdm_adc_data, 1075 }, 1076 { 1077 .compatible = "st,stm32-dfsdm-dmic", 1078 .data = &stm32h7_dfsdm_audio_data, 1079 }, 1080 {} 1081 }; 1082 1083 static int stm32_dfsdm_adc_probe(struct platform_device *pdev) 1084 { 1085 struct device *dev = &pdev->dev; 1086 struct stm32_dfsdm_adc *adc; 1087 struct device_node *np = dev->of_node; 1088 const struct stm32_dfsdm_dev_data *dev_data; 1089 struct iio_dev *iio; 1090 char *name; 1091 int ret, irq, val; 1092 1093 1094 dev_data = of_device_get_match_data(dev); 1095 iio = devm_iio_device_alloc(dev, sizeof(*adc)); 1096 if (!iio) { 1097 dev_err(dev, "%s: Failed to allocate IIO\n", __func__); 1098 return -ENOMEM; 1099 } 1100 1101 adc = iio_priv(iio); 1102 adc->dfsdm = dev_get_drvdata(dev->parent); 1103 1104 iio->dev.parent = dev; 1105 iio->dev.of_node = np; 1106 iio->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1107 1108 platform_set_drvdata(pdev, adc); 1109 1110 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id); 1111 if (ret != 0) { 1112 dev_err(dev, "Missing reg property\n"); 1113 return -EINVAL; 1114 } 1115 1116 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL); 1117 if (!name) 1118 return -ENOMEM; 1119 if (dev_data->type == DFSDM_AUDIO) { 1120 iio->info = &stm32_dfsdm_info_audio; 1121 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id); 1122 } else { 1123 iio->info = &stm32_dfsdm_info_adc; 1124 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id); 1125 } 1126 iio->name = name; 1127 1128 /* 1129 * In a first step IRQs generated for channels are not treated. 1130 * So IRQ associated to filter instance 0 is dedicated to the Filter 0. 1131 */ 1132 irq = platform_get_irq(pdev, 0); 1133 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq, 1134 0, pdev->name, adc); 1135 if (ret < 0) { 1136 dev_err(dev, "Failed to request IRQ\n"); 1137 return ret; 1138 } 1139 1140 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val); 1141 if (ret < 0) { 1142 dev_err(dev, "Failed to set filter order\n"); 1143 return ret; 1144 } 1145 1146 adc->dfsdm->fl_list[adc->fl_id].ford = val; 1147 1148 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val); 1149 if (!ret) 1150 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val; 1151 1152 adc->dev_data = dev_data; 1153 ret = dev_data->init(iio); 1154 if (ret < 0) 1155 return ret; 1156 1157 ret = iio_device_register(iio); 1158 if (ret < 0) 1159 goto err_cleanup; 1160 1161 dev_err(dev, "of_platform_populate\n"); 1162 if (dev_data->type == DFSDM_AUDIO) { 1163 ret = of_platform_populate(np, NULL, NULL, dev); 1164 if (ret < 0) { 1165 dev_err(dev, "Failed to find an audio DAI\n"); 1166 goto err_unregister; 1167 } 1168 } 1169 1170 return 0; 1171 1172 err_unregister: 1173 iio_device_unregister(iio); 1174 err_cleanup: 1175 stm32_dfsdm_dma_release(iio); 1176 1177 return ret; 1178 } 1179 1180 static int stm32_dfsdm_adc_remove(struct platform_device *pdev) 1181 { 1182 struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev); 1183 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1184 1185 if (adc->dev_data->type == DFSDM_AUDIO) 1186 of_platform_depopulate(&pdev->dev); 1187 iio_device_unregister(indio_dev); 1188 stm32_dfsdm_dma_release(indio_dev); 1189 1190 return 0; 1191 } 1192 1193 static struct platform_driver stm32_dfsdm_adc_driver = { 1194 .driver = { 1195 .name = "stm32-dfsdm-adc", 1196 .of_match_table = stm32_dfsdm_adc_match, 1197 }, 1198 .probe = stm32_dfsdm_adc_probe, 1199 .remove = stm32_dfsdm_adc_remove, 1200 }; 1201 module_platform_driver(stm32_dfsdm_adc_driver); 1202 1203 MODULE_DESCRIPTION("STM32 sigma delta ADC"); 1204 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>"); 1205 MODULE_LICENSE("GPL v2"); 1206