1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is the ADC part of the STM32 DFSDM driver 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>. 7 */ 8 9 #include <linux/dmaengine.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/iio/adc/stm32-dfsdm-adc.h> 12 #include <linux/iio/buffer.h> 13 #include <linux/iio/hw-consumer.h> 14 #include <linux/iio/sysfs.h> 15 #include <linux/iio/timer/stm32-lptim-trigger.h> 16 #include <linux/iio/timer/stm32-timer-trigger.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/iio/triggered_buffer.h> 20 #include <linux/interrupt.h> 21 #include <linux/module.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/slab.h> 26 27 #include "stm32-dfsdm.h" 28 29 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE) 30 31 /* Conversion timeout */ 32 #define DFSDM_TIMEOUT_US 100000 33 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000)) 34 35 /* Oversampling attribute default */ 36 #define DFSDM_DEFAULT_OVERSAMPLING 100 37 38 /* Oversampling max values */ 39 #define DFSDM_MAX_INT_OVERSAMPLING 256 40 #define DFSDM_MAX_FL_OVERSAMPLING 1024 41 42 /* Max sample resolutions */ 43 #define DFSDM_MAX_RES BIT(31) 44 #define DFSDM_DATA_RES BIT(23) 45 46 /* Filter configuration */ 47 #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \ 48 DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \ 49 DFSDM_CR1_JSCAN_MASK) 50 51 enum sd_converter_type { 52 DFSDM_AUDIO, 53 DFSDM_IIO, 54 }; 55 56 struct stm32_dfsdm_dev_data { 57 int type; 58 int (*init)(struct iio_dev *indio_dev); 59 unsigned int num_channels; 60 const struct regmap_config *regmap_cfg; 61 }; 62 63 struct stm32_dfsdm_adc { 64 struct stm32_dfsdm *dfsdm; 65 const struct stm32_dfsdm_dev_data *dev_data; 66 unsigned int fl_id; 67 unsigned int nconv; 68 unsigned long smask; 69 70 /* ADC specific */ 71 unsigned int oversamp; 72 struct iio_hw_consumer *hwc; 73 struct completion completion; 74 u32 *buffer; 75 76 /* Audio specific */ 77 unsigned int spi_freq; /* SPI bus clock frequency */ 78 unsigned int sample_freq; /* Sample frequency after filter decimation */ 79 int (*cb)(const void *data, size_t size, void *cb_priv); 80 void *cb_priv; 81 82 /* DMA */ 83 u8 *rx_buf; 84 unsigned int bufi; /* Buffer current position */ 85 unsigned int buf_sz; /* Buffer size */ 86 struct dma_chan *dma_chan; 87 dma_addr_t dma_buf; 88 }; 89 90 struct stm32_dfsdm_str2field { 91 const char *name; 92 unsigned int val; 93 }; 94 95 /* DFSDM channel serial interface type */ 96 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = { 97 { "SPI_R", 0 }, /* SPI with data on rising edge */ 98 { "SPI_F", 1 }, /* SPI with data on falling edge */ 99 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */ 100 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */ 101 {}, 102 }; 103 104 /* DFSDM channel clock source */ 105 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = { 106 /* External SPI clock (CLKIN x) */ 107 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL }, 108 /* Internal SPI clock (CLKOUT) */ 109 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL }, 110 /* Internal SPI clock divided by 2 (falling edge) */ 111 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING }, 112 /* Internal SPI clock divided by 2 (falling edge) */ 113 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING }, 114 {}, 115 }; 116 117 static int stm32_dfsdm_str2val(const char *str, 118 const struct stm32_dfsdm_str2field *list) 119 { 120 const struct stm32_dfsdm_str2field *p = list; 121 122 for (p = list; p && p->name; p++) 123 if (!strcmp(p->name, str)) 124 return p->val; 125 126 return -EINVAL; 127 } 128 129 /** 130 * struct stm32_dfsdm_trig_info - DFSDM trigger info 131 * @name: name of the trigger, corresponding to its source 132 * @jextsel: trigger signal selection 133 */ 134 struct stm32_dfsdm_trig_info { 135 const char *name; 136 unsigned int jextsel; 137 }; 138 139 /* hardware injected trigger enable, edge selection */ 140 enum stm32_dfsdm_jexten { 141 STM32_DFSDM_JEXTEN_DISABLED, 142 STM32_DFSDM_JEXTEN_RISING_EDGE, 143 STM32_DFSDM_JEXTEN_FALLING_EDGE, 144 STM32_DFSDM_EXTEN_BOTH_EDGES, 145 }; 146 147 static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = { 148 { TIM1_TRGO, 0 }, 149 { TIM1_TRGO2, 1 }, 150 { TIM8_TRGO, 2 }, 151 { TIM8_TRGO2, 3 }, 152 { TIM3_TRGO, 4 }, 153 { TIM4_TRGO, 5 }, 154 { TIM16_OC1, 6 }, 155 { TIM6_TRGO, 7 }, 156 { TIM7_TRGO, 8 }, 157 { LPTIM1_OUT, 26 }, 158 { LPTIM2_OUT, 27 }, 159 { LPTIM3_OUT, 28 }, 160 {}, 161 }; 162 163 static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev, 164 struct iio_trigger *trig) 165 { 166 int i; 167 168 /* lookup triggers registered by stm32 timer trigger driver */ 169 for (i = 0; stm32_dfsdm_trigs[i].name; i++) { 170 /** 171 * Checking both stm32 timer trigger type and trig name 172 * should be safe against arbitrary trigger names. 173 */ 174 if ((is_stm32_timer_trigger(trig) || 175 is_stm32_lptim_trigger(trig)) && 176 !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) { 177 return stm32_dfsdm_trigs[i].jextsel; 178 } 179 } 180 181 return -EINVAL; 182 } 183 184 static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl, 185 unsigned int fast, unsigned int oversamp) 186 { 187 unsigned int i, d, fosr, iosr; 188 u64 res; 189 s64 delta; 190 unsigned int m = 1; /* multiplication factor */ 191 unsigned int p = fl->ford; /* filter order (ford) */ 192 193 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp); 194 /* 195 * This function tries to compute filter oversampling and integrator 196 * oversampling, base on oversampling ratio requested by user. 197 * 198 * Decimation d depends on the filter order and the oversampling ratios. 199 * ford: filter order 200 * fosr: filter over sampling ratio 201 * iosr: integrator over sampling ratio 202 */ 203 if (fl->ford == DFSDM_FASTSINC_ORDER) { 204 m = 2; 205 p = 2; 206 } 207 208 /* 209 * Look for filter and integrator oversampling ratios which allows 210 * to reach 24 bits data output resolution. 211 * Leave as soon as if exact resolution if reached. 212 * Otherwise the higher resolution below 32 bits is kept. 213 */ 214 fl->res = 0; 215 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) { 216 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) { 217 if (fast) 218 d = fosr * iosr; 219 else if (fl->ford == DFSDM_FASTSINC_ORDER) 220 d = fosr * (iosr + 3) + 2; 221 else 222 d = fosr * (iosr - 1 + p) + p; 223 224 if (d > oversamp) 225 break; 226 else if (d != oversamp) 227 continue; 228 /* 229 * Check resolution (limited to signed 32 bits) 230 * res <= 2^31 231 * Sincx filters: 232 * res = m * fosr^p x iosr (with m=1, p=ford) 233 * FastSinc filter 234 * res = m * fosr^p x iosr (with m=2, p=2) 235 */ 236 res = fosr; 237 for (i = p - 1; i > 0; i--) { 238 res = res * (u64)fosr; 239 if (res > DFSDM_MAX_RES) 240 break; 241 } 242 if (res > DFSDM_MAX_RES) 243 continue; 244 res = res * (u64)m * (u64)iosr; 245 if (res > DFSDM_MAX_RES) 246 continue; 247 248 delta = res - DFSDM_DATA_RES; 249 250 if (res >= fl->res) { 251 fl->res = res; 252 fl->fosr = fosr; 253 fl->iosr = iosr; 254 fl->fast = fast; 255 pr_debug("%s: fosr = %d, iosr = %d\n", 256 __func__, fl->fosr, fl->iosr); 257 } 258 259 if (!delta) 260 return 0; 261 } 262 } 263 264 if (!fl->res) 265 return -EINVAL; 266 267 return 0; 268 } 269 270 static int stm32_dfsdm_start_channel(struct stm32_dfsdm_adc *adc) 271 { 272 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 273 struct regmap *regmap = adc->dfsdm->regmap; 274 const struct iio_chan_spec *chan; 275 unsigned int bit; 276 int ret; 277 278 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) { 279 chan = indio_dev->channels + bit; 280 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel), 281 DFSDM_CHCFGR1_CHEN_MASK, 282 DFSDM_CHCFGR1_CHEN(1)); 283 if (ret < 0) 284 return ret; 285 } 286 287 return 0; 288 } 289 290 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm_adc *adc) 291 { 292 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 293 struct regmap *regmap = adc->dfsdm->regmap; 294 const struct iio_chan_spec *chan; 295 unsigned int bit; 296 297 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) { 298 chan = indio_dev->channels + bit; 299 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel), 300 DFSDM_CHCFGR1_CHEN_MASK, 301 DFSDM_CHCFGR1_CHEN(0)); 302 } 303 } 304 305 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm, 306 struct stm32_dfsdm_channel *ch) 307 { 308 unsigned int id = ch->id; 309 struct regmap *regmap = dfsdm->regmap; 310 int ret; 311 312 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 313 DFSDM_CHCFGR1_SITP_MASK, 314 DFSDM_CHCFGR1_SITP(ch->type)); 315 if (ret < 0) 316 return ret; 317 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 318 DFSDM_CHCFGR1_SPICKSEL_MASK, 319 DFSDM_CHCFGR1_SPICKSEL(ch->src)); 320 if (ret < 0) 321 return ret; 322 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id), 323 DFSDM_CHCFGR1_CHINSEL_MASK, 324 DFSDM_CHCFGR1_CHINSEL(ch->alt_si)); 325 } 326 327 static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc, 328 unsigned int fl_id, 329 struct iio_trigger *trig) 330 { 331 struct stm32_dfsdm *dfsdm = adc->dfsdm; 332 int ret; 333 334 /* Enable filter */ 335 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 336 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1)); 337 if (ret < 0) 338 return ret; 339 340 /* Nothing more to do for injected (scan mode/triggered) conversions */ 341 if (adc->nconv > 1 || trig) 342 return 0; 343 344 /* Software start (single or continuous) regular conversion */ 345 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 346 DFSDM_CR1_RSWSTART_MASK, 347 DFSDM_CR1_RSWSTART(1)); 348 } 349 350 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm, 351 unsigned int fl_id) 352 { 353 /* Disable conversion */ 354 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id), 355 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0)); 356 } 357 358 static int stm32_dfsdm_filter_set_trig(struct stm32_dfsdm_adc *adc, 359 unsigned int fl_id, 360 struct iio_trigger *trig) 361 { 362 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 363 struct regmap *regmap = adc->dfsdm->regmap; 364 u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED; 365 int ret; 366 367 if (trig) { 368 ret = stm32_dfsdm_get_jextsel(indio_dev, trig); 369 if (ret < 0) 370 return ret; 371 372 /* set trigger source and polarity (default to rising edge) */ 373 jextsel = ret; 374 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE; 375 } 376 377 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), 378 DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK, 379 DFSDM_CR1_JEXTSEL(jextsel) | 380 DFSDM_CR1_JEXTEN(jexten)); 381 if (ret < 0) 382 return ret; 383 384 return 0; 385 } 386 387 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc, 388 unsigned int fl_id, 389 struct iio_trigger *trig) 390 { 391 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 392 struct regmap *regmap = adc->dfsdm->regmap; 393 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id]; 394 u32 cr1; 395 const struct iio_chan_spec *chan; 396 unsigned int bit, jchg = 0; 397 int ret; 398 399 /* Average integrator oversampling */ 400 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK, 401 DFSDM_FCR_IOSR(fl->iosr - 1)); 402 if (ret) 403 return ret; 404 405 /* Filter order and Oversampling */ 406 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK, 407 DFSDM_FCR_FOSR(fl->fosr - 1)); 408 if (ret) 409 return ret; 410 411 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK, 412 DFSDM_FCR_FORD(fl->ford)); 413 if (ret) 414 return ret; 415 416 ret = stm32_dfsdm_filter_set_trig(adc, fl_id, trig); 417 if (ret) 418 return ret; 419 420 /* 421 * DFSDM modes configuration W.R.T audio/iio type modes 422 * ---------------------------------------------------------------- 423 * Modes | regular | regular | injected | injected | 424 * | | continuous | | + scan | 425 * --------------|---------|--------------|----------|------------| 426 * single conv | x | | | | 427 * (1 chan) | | | | | 428 * --------------|---------|--------------|----------|------------| 429 * 1 Audio chan | | sample freq | | | 430 * | | or sync_mode | | | 431 * --------------|---------|--------------|----------|------------| 432 * 1 IIO chan | | sample freq | trigger | | 433 * | | or sync_mode | | | 434 * --------------|---------|--------------|----------|------------| 435 * 2+ IIO chans | | | | trigger or | 436 * | | | | sync_mode | 437 * ---------------------------------------------------------------- 438 */ 439 if (adc->nconv == 1 && !trig) { 440 bit = __ffs(adc->smask); 441 chan = indio_dev->channels + bit; 442 443 /* Use regular conversion for single channel without trigger */ 444 cr1 = DFSDM_CR1_RCH(chan->channel); 445 446 /* Continuous conversions triggered by SPI clk in buffer mode */ 447 if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE) 448 cr1 |= DFSDM_CR1_RCONT(1); 449 450 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode); 451 } else { 452 /* Use injected conversion for multiple channels */ 453 for_each_set_bit(bit, &adc->smask, 454 sizeof(adc->smask) * BITS_PER_BYTE) { 455 chan = indio_dev->channels + bit; 456 jchg |= BIT(chan->channel); 457 } 458 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg); 459 if (ret < 0) 460 return ret; 461 462 /* Use scan mode for multiple channels */ 463 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0); 464 465 /* 466 * Continuous conversions not supported in injected mode, 467 * either use: 468 * - conversions in sync with filter 0 469 * - triggered conversions 470 */ 471 if (!fl->sync_mode && !trig) 472 return -EINVAL; 473 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode); 474 } 475 476 return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK, 477 cr1); 478 } 479 480 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm, 481 struct iio_dev *indio_dev, 482 struct iio_chan_spec *ch) 483 { 484 struct stm32_dfsdm_channel *df_ch; 485 const char *of_str; 486 int chan_idx = ch->scan_index; 487 int ret, val; 488 489 ret = of_property_read_u32_index(indio_dev->dev.of_node, 490 "st,adc-channels", chan_idx, 491 &ch->channel); 492 if (ret < 0) { 493 dev_err(&indio_dev->dev, 494 " Error parsing 'st,adc-channels' for idx %d\n", 495 chan_idx); 496 return ret; 497 } 498 if (ch->channel >= dfsdm->num_chs) { 499 dev_err(&indio_dev->dev, 500 " Error bad channel number %d (max = %d)\n", 501 ch->channel, dfsdm->num_chs); 502 return -EINVAL; 503 } 504 505 ret = of_property_read_string_index(indio_dev->dev.of_node, 506 "st,adc-channel-names", chan_idx, 507 &ch->datasheet_name); 508 if (ret < 0) { 509 dev_err(&indio_dev->dev, 510 " Error parsing 'st,adc-channel-names' for idx %d\n", 511 chan_idx); 512 return ret; 513 } 514 515 df_ch = &dfsdm->ch_list[ch->channel]; 516 df_ch->id = ch->channel; 517 518 ret = of_property_read_string_index(indio_dev->dev.of_node, 519 "st,adc-channel-types", chan_idx, 520 &of_str); 521 if (!ret) { 522 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type); 523 if (val < 0) 524 return val; 525 } else { 526 val = 0; 527 } 528 df_ch->type = val; 529 530 ret = of_property_read_string_index(indio_dev->dev.of_node, 531 "st,adc-channel-clk-src", chan_idx, 532 &of_str); 533 if (!ret) { 534 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src); 535 if (val < 0) 536 return val; 537 } else { 538 val = 0; 539 } 540 df_ch->src = val; 541 542 ret = of_property_read_u32_index(indio_dev->dev.of_node, 543 "st,adc-alt-channel", chan_idx, 544 &df_ch->alt_si); 545 if (ret < 0) 546 df_ch->alt_si = 0; 547 548 return 0; 549 } 550 551 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev, 552 uintptr_t priv, 553 const struct iio_chan_spec *chan, 554 char *buf) 555 { 556 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 557 558 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq); 559 } 560 561 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev, 562 uintptr_t priv, 563 const struct iio_chan_spec *chan, 564 const char *buf, size_t len) 565 { 566 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 567 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; 568 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel]; 569 unsigned int sample_freq = adc->sample_freq; 570 unsigned int spi_freq; 571 int ret; 572 573 dev_err(&indio_dev->dev, "enter %s\n", __func__); 574 /* If DFSDM is master on SPI, SPI freq can not be updated */ 575 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) 576 return -EPERM; 577 578 ret = kstrtoint(buf, 0, &spi_freq); 579 if (ret) 580 return ret; 581 582 if (!spi_freq) 583 return -EINVAL; 584 585 if (sample_freq) { 586 if (spi_freq % sample_freq) 587 dev_warn(&indio_dev->dev, 588 "Sampling rate not accurate (%d)\n", 589 spi_freq / (spi_freq / sample_freq)); 590 591 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / sample_freq)); 592 if (ret < 0) { 593 dev_err(&indio_dev->dev, 594 "No filter parameters that match!\n"); 595 return ret; 596 } 597 } 598 adc->spi_freq = spi_freq; 599 600 return len; 601 } 602 603 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, 604 struct iio_trigger *trig) 605 { 606 struct regmap *regmap = adc->dfsdm->regmap; 607 int ret; 608 609 ret = stm32_dfsdm_start_channel(adc); 610 if (ret < 0) 611 return ret; 612 613 ret = stm32_dfsdm_filter_configure(adc, adc->fl_id, trig); 614 if (ret < 0) 615 goto stop_channels; 616 617 ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig); 618 if (ret < 0) 619 goto filter_unconfigure; 620 621 return 0; 622 623 filter_unconfigure: 624 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 625 DFSDM_CR1_CFG_MASK, 0); 626 stop_channels: 627 stm32_dfsdm_stop_channel(adc); 628 629 return ret; 630 } 631 632 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc) 633 { 634 struct regmap *regmap = adc->dfsdm->regmap; 635 636 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id); 637 638 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id), 639 DFSDM_CR1_CFG_MASK, 0); 640 641 stm32_dfsdm_stop_channel(adc); 642 } 643 644 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev, 645 unsigned int val) 646 { 647 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 648 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2; 649 unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE; 650 651 /* 652 * DMA cyclic transfers are used, buffer is split into two periods. 653 * There should be : 654 * - always one buffer (period) DMA is working on 655 * - one buffer (period) driver pushed to ASoC side. 656 */ 657 watermark = min(watermark, val * (unsigned int)(sizeof(u32))); 658 adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv); 659 660 return 0; 661 } 662 663 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc) 664 { 665 struct dma_tx_state state; 666 enum dma_status status; 667 668 status = dmaengine_tx_status(adc->dma_chan, 669 adc->dma_chan->cookie, 670 &state); 671 if (status == DMA_IN_PROGRESS) { 672 /* Residue is size in bytes from end of buffer */ 673 unsigned int i = adc->buf_sz - state.residue; 674 unsigned int size; 675 676 /* Return available bytes */ 677 if (i >= adc->bufi) 678 size = i - adc->bufi; 679 else 680 size = adc->buf_sz + i - adc->bufi; 681 682 return size; 683 } 684 685 return 0; 686 } 687 688 static irqreturn_t stm32_dfsdm_adc_trigger_handler(int irq, void *p) 689 { 690 struct iio_poll_func *pf = p; 691 struct iio_dev *indio_dev = pf->indio_dev; 692 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 693 int available = stm32_dfsdm_adc_dma_residue(adc); 694 695 while (available >= indio_dev->scan_bytes) { 696 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi]; 697 698 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 699 pf->timestamp); 700 available -= indio_dev->scan_bytes; 701 adc->bufi += indio_dev->scan_bytes; 702 if (adc->bufi >= adc->buf_sz) 703 adc->bufi = 0; 704 } 705 706 iio_trigger_notify_done(indio_dev->trig); 707 708 return IRQ_HANDLED; 709 } 710 711 static void stm32_dfsdm_dma_buffer_done(void *data) 712 { 713 struct iio_dev *indio_dev = data; 714 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 715 int available = stm32_dfsdm_adc_dma_residue(adc); 716 size_t old_pos; 717 718 if (indio_dev->currentmode & INDIO_BUFFER_TRIGGERED) { 719 iio_trigger_poll_chained(indio_dev->trig); 720 return; 721 } 722 723 /* 724 * FIXME: In Kernel interface does not support cyclic DMA buffer,and 725 * offers only an interface to push data samples per samples. 726 * For this reason IIO buffer interface is not used and interface is 727 * bypassed using a private callback registered by ASoC. 728 * This should be a temporary solution waiting a cyclic DMA engine 729 * support in IIO. 730 */ 731 732 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__, 733 adc->bufi, available); 734 old_pos = adc->bufi; 735 736 while (available >= indio_dev->scan_bytes) { 737 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi]; 738 739 /* Mask 8 LSB that contains the channel ID */ 740 *buffer = (*buffer & 0xFFFFFF00) << 8; 741 available -= indio_dev->scan_bytes; 742 adc->bufi += indio_dev->scan_bytes; 743 if (adc->bufi >= adc->buf_sz) { 744 if (adc->cb) 745 adc->cb(&adc->rx_buf[old_pos], 746 adc->buf_sz - old_pos, adc->cb_priv); 747 adc->bufi = 0; 748 old_pos = 0; 749 } 750 /* regular iio buffer without trigger */ 751 if (adc->dev_data->type == DFSDM_IIO) 752 iio_push_to_buffers(indio_dev, buffer); 753 } 754 if (adc->cb) 755 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos, 756 adc->cb_priv); 757 } 758 759 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev) 760 { 761 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 762 struct dma_slave_config config = { 763 .src_addr = (dma_addr_t)adc->dfsdm->phys_base, 764 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 765 }; 766 struct dma_async_tx_descriptor *desc; 767 dma_cookie_t cookie; 768 int ret; 769 770 if (!adc->dma_chan) 771 return -EINVAL; 772 773 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 774 adc->buf_sz, adc->buf_sz / 2); 775 776 if (adc->nconv == 1 && !indio_dev->trig) 777 config.src_addr += DFSDM_RDATAR(adc->fl_id); 778 else 779 config.src_addr += DFSDM_JDATAR(adc->fl_id); 780 ret = dmaengine_slave_config(adc->dma_chan, &config); 781 if (ret) 782 return ret; 783 784 /* Prepare a DMA cyclic transaction */ 785 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 786 adc->dma_buf, 787 adc->buf_sz, adc->buf_sz / 2, 788 DMA_DEV_TO_MEM, 789 DMA_PREP_INTERRUPT); 790 if (!desc) 791 return -EBUSY; 792 793 desc->callback = stm32_dfsdm_dma_buffer_done; 794 desc->callback_param = indio_dev; 795 796 cookie = dmaengine_submit(desc); 797 ret = dma_submit_error(cookie); 798 if (ret) 799 goto err_stop_dma; 800 801 /* Issue pending DMA requests */ 802 dma_async_issue_pending(adc->dma_chan); 803 804 if (adc->nconv == 1 && !indio_dev->trig) { 805 /* Enable regular DMA transfer*/ 806 ret = regmap_update_bits(adc->dfsdm->regmap, 807 DFSDM_CR1(adc->fl_id), 808 DFSDM_CR1_RDMAEN_MASK, 809 DFSDM_CR1_RDMAEN_MASK); 810 } else { 811 /* Enable injected DMA transfer*/ 812 ret = regmap_update_bits(adc->dfsdm->regmap, 813 DFSDM_CR1(adc->fl_id), 814 DFSDM_CR1_JDMAEN_MASK, 815 DFSDM_CR1_JDMAEN_MASK); 816 } 817 818 if (ret < 0) 819 goto err_stop_dma; 820 821 return 0; 822 823 err_stop_dma: 824 dmaengine_terminate_all(adc->dma_chan); 825 826 return ret; 827 } 828 829 static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev) 830 { 831 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 832 833 if (!adc->dma_chan) 834 return; 835 836 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id), 837 DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0); 838 dmaengine_terminate_all(adc->dma_chan); 839 } 840 841 static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev, 842 const unsigned long *scan_mask) 843 { 844 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 845 846 adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength); 847 adc->smask = *scan_mask; 848 849 dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask); 850 851 return 0; 852 } 853 854 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev) 855 { 856 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 857 int ret; 858 859 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) { 860 ret = iio_triggered_buffer_postenable(indio_dev); 861 if (ret < 0) 862 return ret; 863 } 864 865 /* Reset adc buffer index */ 866 adc->bufi = 0; 867 868 if (adc->hwc) { 869 ret = iio_hw_consumer_enable(adc->hwc); 870 if (ret < 0) 871 goto err_predisable; 872 } 873 874 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm); 875 if (ret < 0) 876 goto err_stop_hwc; 877 878 ret = stm32_dfsdm_adc_dma_start(indio_dev); 879 if (ret) { 880 dev_err(&indio_dev->dev, "Can't start DMA\n"); 881 goto stop_dfsdm; 882 } 883 884 ret = stm32_dfsdm_start_conv(adc, indio_dev->trig); 885 if (ret) { 886 dev_err(&indio_dev->dev, "Can't start conversion\n"); 887 goto err_stop_dma; 888 } 889 890 return 0; 891 892 err_stop_dma: 893 stm32_dfsdm_adc_dma_stop(indio_dev); 894 stop_dfsdm: 895 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 896 err_stop_hwc: 897 if (adc->hwc) 898 iio_hw_consumer_disable(adc->hwc); 899 err_predisable: 900 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 901 iio_triggered_buffer_predisable(indio_dev); 902 903 return ret; 904 } 905 906 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev) 907 { 908 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 909 910 stm32_dfsdm_stop_conv(adc); 911 912 stm32_dfsdm_adc_dma_stop(indio_dev); 913 914 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 915 916 if (adc->hwc) 917 iio_hw_consumer_disable(adc->hwc); 918 919 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 920 iio_triggered_buffer_predisable(indio_dev); 921 922 return 0; 923 } 924 925 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = { 926 .postenable = &stm32_dfsdm_postenable, 927 .predisable = &stm32_dfsdm_predisable, 928 }; 929 930 /** 931 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when 932 * DMA transfer period is achieved. 933 * 934 * @iio_dev: Handle to IIO device. 935 * @cb: Pointer to callback function: 936 * - data: pointer to data buffer 937 * - size: size in byte of the data buffer 938 * - private: pointer to consumer private structure. 939 * @private: Pointer to consumer private structure. 940 */ 941 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev, 942 int (*cb)(const void *data, size_t size, 943 void *private), 944 void *private) 945 { 946 struct stm32_dfsdm_adc *adc; 947 948 if (!iio_dev) 949 return -EINVAL; 950 adc = iio_priv(iio_dev); 951 952 adc->cb = cb; 953 adc->cb_priv = private; 954 955 return 0; 956 } 957 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb); 958 959 /** 960 * stm32_dfsdm_release_buff_cb - unregister buffer callback 961 * 962 * @iio_dev: Handle to IIO device. 963 */ 964 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev) 965 { 966 struct stm32_dfsdm_adc *adc; 967 968 if (!iio_dev) 969 return -EINVAL; 970 adc = iio_priv(iio_dev); 971 972 adc->cb = NULL; 973 adc->cb_priv = NULL; 974 975 return 0; 976 } 977 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb); 978 979 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev, 980 const struct iio_chan_spec *chan, int *res) 981 { 982 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 983 long timeout; 984 int ret; 985 986 reinit_completion(&adc->completion); 987 988 adc->buffer = res; 989 990 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm); 991 if (ret < 0) 992 return ret; 993 994 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 995 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1)); 996 if (ret < 0) 997 goto stop_dfsdm; 998 999 adc->nconv = 1; 1000 adc->smask = BIT(chan->scan_index); 1001 ret = stm32_dfsdm_start_conv(adc, NULL); 1002 if (ret < 0) { 1003 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 1004 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0)); 1005 goto stop_dfsdm; 1006 } 1007 1008 timeout = wait_for_completion_interruptible_timeout(&adc->completion, 1009 DFSDM_TIMEOUT); 1010 1011 /* Mask IRQ for regular conversion achievement*/ 1012 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), 1013 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0)); 1014 1015 if (timeout == 0) 1016 ret = -ETIMEDOUT; 1017 else if (timeout < 0) 1018 ret = timeout; 1019 else 1020 ret = IIO_VAL_INT; 1021 1022 stm32_dfsdm_stop_conv(adc); 1023 1024 stop_dfsdm: 1025 stm32_dfsdm_stop_dfsdm(adc->dfsdm); 1026 1027 return ret; 1028 } 1029 1030 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev, 1031 struct iio_chan_spec const *chan, 1032 int val, int val2, long mask) 1033 { 1034 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1035 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; 1036 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel]; 1037 unsigned int spi_freq; 1038 int ret = -EINVAL; 1039 1040 switch (mask) { 1041 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1042 ret = iio_device_claim_direct_mode(indio_dev); 1043 if (ret) 1044 return ret; 1045 ret = stm32_dfsdm_set_osrs(fl, 0, val); 1046 if (!ret) 1047 adc->oversamp = val; 1048 iio_device_release_direct_mode(indio_dev); 1049 return ret; 1050 1051 case IIO_CHAN_INFO_SAMP_FREQ: 1052 if (!val) 1053 return -EINVAL; 1054 1055 ret = iio_device_claim_direct_mode(indio_dev); 1056 if (ret) 1057 return ret; 1058 1059 switch (ch->src) { 1060 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL: 1061 spi_freq = adc->dfsdm->spi_master_freq; 1062 break; 1063 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING: 1064 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING: 1065 spi_freq = adc->dfsdm->spi_master_freq / 2; 1066 break; 1067 default: 1068 spi_freq = adc->spi_freq; 1069 } 1070 1071 if (spi_freq % val) 1072 dev_warn(&indio_dev->dev, 1073 "Sampling rate not accurate (%d)\n", 1074 spi_freq / (spi_freq / val)); 1075 1076 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / val)); 1077 if (ret < 0) { 1078 dev_err(&indio_dev->dev, 1079 "Not able to find parameter that match!\n"); 1080 iio_device_release_direct_mode(indio_dev); 1081 return ret; 1082 } 1083 adc->sample_freq = val; 1084 iio_device_release_direct_mode(indio_dev); 1085 1086 return 0; 1087 } 1088 1089 return -EINVAL; 1090 } 1091 1092 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev, 1093 struct iio_chan_spec const *chan, int *val, 1094 int *val2, long mask) 1095 { 1096 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1097 int ret; 1098 1099 switch (mask) { 1100 case IIO_CHAN_INFO_RAW: 1101 ret = iio_device_claim_direct_mode(indio_dev); 1102 if (ret) 1103 return ret; 1104 ret = iio_hw_consumer_enable(adc->hwc); 1105 if (ret < 0) { 1106 dev_err(&indio_dev->dev, 1107 "%s: IIO enable failed (channel %d)\n", 1108 __func__, chan->channel); 1109 iio_device_release_direct_mode(indio_dev); 1110 return ret; 1111 } 1112 ret = stm32_dfsdm_single_conv(indio_dev, chan, val); 1113 iio_hw_consumer_disable(adc->hwc); 1114 if (ret < 0) { 1115 dev_err(&indio_dev->dev, 1116 "%s: Conversion failed (channel %d)\n", 1117 __func__, chan->channel); 1118 iio_device_release_direct_mode(indio_dev); 1119 return ret; 1120 } 1121 iio_device_release_direct_mode(indio_dev); 1122 return IIO_VAL_INT; 1123 1124 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1125 *val = adc->oversamp; 1126 1127 return IIO_VAL_INT; 1128 1129 case IIO_CHAN_INFO_SAMP_FREQ: 1130 *val = adc->sample_freq; 1131 1132 return IIO_VAL_INT; 1133 } 1134 1135 return -EINVAL; 1136 } 1137 1138 static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev, 1139 struct iio_trigger *trig) 1140 { 1141 return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0; 1142 } 1143 1144 static const struct iio_info stm32_dfsdm_info_audio = { 1145 .hwfifo_set_watermark = stm32_dfsdm_set_watermark, 1146 .read_raw = stm32_dfsdm_read_raw, 1147 .write_raw = stm32_dfsdm_write_raw, 1148 .update_scan_mode = stm32_dfsdm_update_scan_mode, 1149 }; 1150 1151 static const struct iio_info stm32_dfsdm_info_adc = { 1152 .hwfifo_set_watermark = stm32_dfsdm_set_watermark, 1153 .read_raw = stm32_dfsdm_read_raw, 1154 .write_raw = stm32_dfsdm_write_raw, 1155 .update_scan_mode = stm32_dfsdm_update_scan_mode, 1156 .validate_trigger = stm32_dfsdm_validate_trigger, 1157 }; 1158 1159 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg) 1160 { 1161 struct stm32_dfsdm_adc *adc = arg; 1162 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1163 struct regmap *regmap = adc->dfsdm->regmap; 1164 unsigned int status, int_en; 1165 1166 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status); 1167 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en); 1168 1169 if (status & DFSDM_ISR_REOCF_MASK) { 1170 /* Read the data register clean the IRQ status */ 1171 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer); 1172 complete(&adc->completion); 1173 } 1174 1175 if (status & DFSDM_ISR_ROVRF_MASK) { 1176 if (int_en & DFSDM_CR2_ROVRIE_MASK) 1177 dev_warn(&indio_dev->dev, "Overrun detected\n"); 1178 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id), 1179 DFSDM_ICR_CLRROVRF_MASK, 1180 DFSDM_ICR_CLRROVRF_MASK); 1181 } 1182 1183 return IRQ_HANDLED; 1184 } 1185 1186 /* 1187 * Define external info for SPI Frequency and audio sampling rate that can be 1188 * configured by ASoC driver through consumer.h API 1189 */ 1190 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = { 1191 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */ 1192 { 1193 .name = "spi_clk_freq", 1194 .shared = IIO_SHARED_BY_TYPE, 1195 .read = dfsdm_adc_audio_get_spiclk, 1196 .write = dfsdm_adc_audio_set_spiclk, 1197 }, 1198 {}, 1199 }; 1200 1201 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev) 1202 { 1203 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1204 1205 if (adc->dma_chan) { 1206 dma_free_coherent(adc->dma_chan->device->dev, 1207 DFSDM_DMA_BUFFER_SIZE, 1208 adc->rx_buf, adc->dma_buf); 1209 dma_release_channel(adc->dma_chan); 1210 } 1211 } 1212 1213 static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev) 1214 { 1215 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1216 1217 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx"); 1218 if (!adc->dma_chan) 1219 return -EINVAL; 1220 1221 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 1222 DFSDM_DMA_BUFFER_SIZE, 1223 &adc->dma_buf, GFP_KERNEL); 1224 if (!adc->rx_buf) { 1225 dma_release_channel(adc->dma_chan); 1226 return -ENOMEM; 1227 } 1228 1229 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 1230 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops; 1231 1232 return 0; 1233 } 1234 1235 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, 1236 struct iio_chan_spec *ch) 1237 { 1238 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1239 int ret; 1240 1241 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch); 1242 if (ret < 0) 1243 return ret; 1244 1245 ch->type = IIO_VOLTAGE; 1246 ch->indexed = 1; 1247 1248 /* 1249 * IIO_CHAN_INFO_RAW: used to compute regular conversion 1250 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling 1251 */ 1252 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 1253 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | 1254 BIT(IIO_CHAN_INFO_SAMP_FREQ); 1255 1256 if (adc->dev_data->type == DFSDM_AUDIO) { 1257 ch->scan_type.sign = 's'; 1258 ch->ext_info = dfsdm_adc_audio_ext_info; 1259 } else { 1260 ch->scan_type.sign = 'u'; 1261 } 1262 ch->scan_type.realbits = 24; 1263 ch->scan_type.storagebits = 32; 1264 1265 return stm32_dfsdm_chan_configure(adc->dfsdm, 1266 &adc->dfsdm->ch_list[ch->channel]); 1267 } 1268 1269 static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev) 1270 { 1271 struct iio_chan_spec *ch; 1272 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1273 struct stm32_dfsdm_channel *d_ch; 1274 int ret; 1275 1276 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL); 1277 if (!ch) 1278 return -ENOMEM; 1279 1280 ch->scan_index = 0; 1281 1282 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch); 1283 if (ret < 0) { 1284 dev_err(&indio_dev->dev, "Channels init failed\n"); 1285 return ret; 1286 } 1287 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ); 1288 1289 d_ch = &adc->dfsdm->ch_list[ch->channel]; 1290 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) 1291 adc->spi_freq = adc->dfsdm->spi_master_freq; 1292 1293 indio_dev->num_channels = 1; 1294 indio_dev->channels = ch; 1295 1296 return stm32_dfsdm_dma_request(indio_dev); 1297 } 1298 1299 static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev) 1300 { 1301 struct iio_chan_spec *ch; 1302 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); 1303 int num_ch; 1304 int ret, chan_idx; 1305 1306 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING; 1307 ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0, 1308 adc->oversamp); 1309 if (ret < 0) 1310 return ret; 1311 1312 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node, 1313 "st,adc-channels"); 1314 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) { 1315 dev_err(&indio_dev->dev, "Bad st,adc-channels\n"); 1316 return num_ch < 0 ? num_ch : -EINVAL; 1317 } 1318 1319 /* Bind to SD modulator IIO device */ 1320 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev); 1321 if (IS_ERR(adc->hwc)) 1322 return -EPROBE_DEFER; 1323 1324 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch), 1325 GFP_KERNEL); 1326 if (!ch) 1327 return -ENOMEM; 1328 1329 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) { 1330 ch[chan_idx].scan_index = chan_idx; 1331 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]); 1332 if (ret < 0) { 1333 dev_err(&indio_dev->dev, "Channels init failed\n"); 1334 return ret; 1335 } 1336 } 1337 1338 indio_dev->num_channels = num_ch; 1339 indio_dev->channels = ch; 1340 1341 init_completion(&adc->completion); 1342 1343 /* Optionally request DMA */ 1344 if (stm32_dfsdm_dma_request(indio_dev)) { 1345 dev_dbg(&indio_dev->dev, "No DMA support\n"); 1346 return 0; 1347 } 1348 1349 ret = iio_triggered_buffer_setup(indio_dev, 1350 &iio_pollfunc_store_time, 1351 &stm32_dfsdm_adc_trigger_handler, 1352 &stm32_dfsdm_buffer_setup_ops); 1353 if (ret) { 1354 stm32_dfsdm_dma_release(indio_dev); 1355 dev_err(&indio_dev->dev, "buffer setup failed\n"); 1356 return ret; 1357 } 1358 1359 /* lptimer/timer hardware triggers */ 1360 indio_dev->modes |= INDIO_HARDWARE_TRIGGERED; 1361 1362 return 0; 1363 } 1364 1365 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = { 1366 .type = DFSDM_IIO, 1367 .init = stm32_dfsdm_adc_init, 1368 }; 1369 1370 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = { 1371 .type = DFSDM_AUDIO, 1372 .init = stm32_dfsdm_audio_init, 1373 }; 1374 1375 static const struct of_device_id stm32_dfsdm_adc_match[] = { 1376 { 1377 .compatible = "st,stm32-dfsdm-adc", 1378 .data = &stm32h7_dfsdm_adc_data, 1379 }, 1380 { 1381 .compatible = "st,stm32-dfsdm-dmic", 1382 .data = &stm32h7_dfsdm_audio_data, 1383 }, 1384 {} 1385 }; 1386 1387 static int stm32_dfsdm_adc_probe(struct platform_device *pdev) 1388 { 1389 struct device *dev = &pdev->dev; 1390 struct stm32_dfsdm_adc *adc; 1391 struct device_node *np = dev->of_node; 1392 const struct stm32_dfsdm_dev_data *dev_data; 1393 struct iio_dev *iio; 1394 char *name; 1395 int ret, irq, val; 1396 1397 dev_data = of_device_get_match_data(dev); 1398 iio = devm_iio_device_alloc(dev, sizeof(*adc)); 1399 if (!iio) { 1400 dev_err(dev, "%s: Failed to allocate IIO\n", __func__); 1401 return -ENOMEM; 1402 } 1403 1404 adc = iio_priv(iio); 1405 adc->dfsdm = dev_get_drvdata(dev->parent); 1406 1407 iio->dev.parent = dev; 1408 iio->dev.of_node = np; 1409 iio->modes = INDIO_DIRECT_MODE; 1410 1411 platform_set_drvdata(pdev, adc); 1412 1413 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id); 1414 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) { 1415 dev_err(dev, "Missing or bad reg property\n"); 1416 return -EINVAL; 1417 } 1418 1419 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL); 1420 if (!name) 1421 return -ENOMEM; 1422 if (dev_data->type == DFSDM_AUDIO) { 1423 iio->info = &stm32_dfsdm_info_audio; 1424 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id); 1425 } else { 1426 iio->info = &stm32_dfsdm_info_adc; 1427 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id); 1428 } 1429 iio->name = name; 1430 1431 /* 1432 * In a first step IRQs generated for channels are not treated. 1433 * So IRQ associated to filter instance 0 is dedicated to the Filter 0. 1434 */ 1435 irq = platform_get_irq(pdev, 0); 1436 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq, 1437 0, pdev->name, adc); 1438 if (ret < 0) { 1439 dev_err(dev, "Failed to request IRQ\n"); 1440 return ret; 1441 } 1442 1443 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val); 1444 if (ret < 0) { 1445 dev_err(dev, "Failed to set filter order\n"); 1446 return ret; 1447 } 1448 1449 adc->dfsdm->fl_list[adc->fl_id].ford = val; 1450 1451 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val); 1452 if (!ret) 1453 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val; 1454 1455 adc->dev_data = dev_data; 1456 ret = dev_data->init(iio); 1457 if (ret < 0) 1458 return ret; 1459 1460 ret = iio_device_register(iio); 1461 if (ret < 0) 1462 goto err_cleanup; 1463 1464 if (dev_data->type == DFSDM_AUDIO) { 1465 ret = of_platform_populate(np, NULL, NULL, dev); 1466 if (ret < 0) { 1467 dev_err(dev, "Failed to find an audio DAI\n"); 1468 goto err_unregister; 1469 } 1470 } 1471 1472 return 0; 1473 1474 err_unregister: 1475 iio_device_unregister(iio); 1476 err_cleanup: 1477 stm32_dfsdm_dma_release(iio); 1478 1479 return ret; 1480 } 1481 1482 static int stm32_dfsdm_adc_remove(struct platform_device *pdev) 1483 { 1484 struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev); 1485 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1486 1487 if (adc->dev_data->type == DFSDM_AUDIO) 1488 of_platform_depopulate(&pdev->dev); 1489 iio_device_unregister(indio_dev); 1490 stm32_dfsdm_dma_release(indio_dev); 1491 1492 return 0; 1493 } 1494 1495 static struct platform_driver stm32_dfsdm_adc_driver = { 1496 .driver = { 1497 .name = "stm32-dfsdm-adc", 1498 .of_match_table = stm32_dfsdm_adc_match, 1499 }, 1500 .probe = stm32_dfsdm_adc_probe, 1501 .remove = stm32_dfsdm_adc_remove, 1502 }; 1503 module_platform_driver(stm32_dfsdm_adc_driver); 1504 1505 MODULE_DESCRIPTION("STM32 sigma delta ADC"); 1506 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>"); 1507 MODULE_LICENSE("GPL v2"); 1508