1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/iio/iio.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/timer/stm32-lptim-trigger.h> 16 #include <linux/iio/timer/stm32-timer-trigger.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/iio/triggered_buffer.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 28 #include "stm32-adc-core.h" 29 30 /* STM32F4 - Registers for each ADC instance */ 31 #define STM32F4_ADC_SR 0x00 32 #define STM32F4_ADC_CR1 0x04 33 #define STM32F4_ADC_CR2 0x08 34 #define STM32F4_ADC_SMPR1 0x0C 35 #define STM32F4_ADC_SMPR2 0x10 36 #define STM32F4_ADC_HTR 0x24 37 #define STM32F4_ADC_LTR 0x28 38 #define STM32F4_ADC_SQR1 0x2C 39 #define STM32F4_ADC_SQR2 0x30 40 #define STM32F4_ADC_SQR3 0x34 41 #define STM32F4_ADC_JSQR 0x38 42 #define STM32F4_ADC_JDR1 0x3C 43 #define STM32F4_ADC_JDR2 0x40 44 #define STM32F4_ADC_JDR3 0x44 45 #define STM32F4_ADC_JDR4 0x48 46 #define STM32F4_ADC_DR 0x4C 47 48 /* STM32F4_ADC_SR - bit fields */ 49 #define STM32F4_STRT BIT(4) 50 #define STM32F4_EOC BIT(1) 51 52 /* STM32F4_ADC_CR1 - bit fields */ 53 #define STM32F4_RES_SHIFT 24 54 #define STM32F4_RES_MASK GENMASK(25, 24) 55 #define STM32F4_SCAN BIT(8) 56 #define STM32F4_EOCIE BIT(5) 57 58 /* STM32F4_ADC_CR2 - bit fields */ 59 #define STM32F4_SWSTART BIT(30) 60 #define STM32F4_EXTEN_SHIFT 28 61 #define STM32F4_EXTEN_MASK GENMASK(29, 28) 62 #define STM32F4_EXTSEL_SHIFT 24 63 #define STM32F4_EXTSEL_MASK GENMASK(27, 24) 64 #define STM32F4_EOCS BIT(10) 65 #define STM32F4_DDS BIT(9) 66 #define STM32F4_DMA BIT(8) 67 #define STM32F4_ADON BIT(0) 68 69 /* STM32H7 - Registers for each ADC instance */ 70 #define STM32H7_ADC_ISR 0x00 71 #define STM32H7_ADC_IER 0x04 72 #define STM32H7_ADC_CR 0x08 73 #define STM32H7_ADC_CFGR 0x0C 74 #define STM32H7_ADC_SMPR1 0x14 75 #define STM32H7_ADC_SMPR2 0x18 76 #define STM32H7_ADC_PCSEL 0x1C 77 #define STM32H7_ADC_SQR1 0x30 78 #define STM32H7_ADC_SQR2 0x34 79 #define STM32H7_ADC_SQR3 0x38 80 #define STM32H7_ADC_SQR4 0x3C 81 #define STM32H7_ADC_DR 0x40 82 #define STM32H7_ADC_DIFSEL 0xC0 83 #define STM32H7_ADC_CALFACT 0xC4 84 #define STM32H7_ADC_CALFACT2 0xC8 85 86 /* STM32H7_ADC_ISR - bit fields */ 87 #define STM32MP1_VREGREADY BIT(12) 88 #define STM32H7_EOC BIT(2) 89 #define STM32H7_ADRDY BIT(0) 90 91 /* STM32H7_ADC_IER - bit fields */ 92 #define STM32H7_EOCIE STM32H7_EOC 93 94 /* STM32H7_ADC_CR - bit fields */ 95 #define STM32H7_ADCAL BIT(31) 96 #define STM32H7_ADCALDIF BIT(30) 97 #define STM32H7_DEEPPWD BIT(29) 98 #define STM32H7_ADVREGEN BIT(28) 99 #define STM32H7_LINCALRDYW6 BIT(27) 100 #define STM32H7_LINCALRDYW5 BIT(26) 101 #define STM32H7_LINCALRDYW4 BIT(25) 102 #define STM32H7_LINCALRDYW3 BIT(24) 103 #define STM32H7_LINCALRDYW2 BIT(23) 104 #define STM32H7_LINCALRDYW1 BIT(22) 105 #define STM32H7_ADCALLIN BIT(16) 106 #define STM32H7_BOOST BIT(8) 107 #define STM32H7_ADSTP BIT(4) 108 #define STM32H7_ADSTART BIT(2) 109 #define STM32H7_ADDIS BIT(1) 110 #define STM32H7_ADEN BIT(0) 111 112 /* STM32H7_ADC_CFGR bit fields */ 113 #define STM32H7_EXTEN_SHIFT 10 114 #define STM32H7_EXTEN_MASK GENMASK(11, 10) 115 #define STM32H7_EXTSEL_SHIFT 5 116 #define STM32H7_EXTSEL_MASK GENMASK(9, 5) 117 #define STM32H7_RES_SHIFT 2 118 #define STM32H7_RES_MASK GENMASK(4, 2) 119 #define STM32H7_DMNGT_SHIFT 0 120 #define STM32H7_DMNGT_MASK GENMASK(1, 0) 121 122 enum stm32h7_adc_dmngt { 123 STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ 124 STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ 125 STM32H7_DMNGT_DFSDM, /* DFSDM mode */ 126 STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ 127 }; 128 129 /* STM32H7_ADC_CALFACT - bit fields */ 130 #define STM32H7_CALFACT_D_SHIFT 16 131 #define STM32H7_CALFACT_D_MASK GENMASK(26, 16) 132 #define STM32H7_CALFACT_S_SHIFT 0 133 #define STM32H7_CALFACT_S_MASK GENMASK(10, 0) 134 135 /* STM32H7_ADC_CALFACT2 - bit fields */ 136 #define STM32H7_LINCALFACT_SHIFT 0 137 #define STM32H7_LINCALFACT_MASK GENMASK(29, 0) 138 139 /* Number of linear calibration shadow registers / LINCALRDYW control bits */ 140 #define STM32H7_LINCALFACT_NUM 6 141 142 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ 143 #define STM32H7_BOOST_CLKRATE 20000000UL 144 145 #define STM32_ADC_CH_MAX 20 /* max number of channels */ 146 #define STM32_ADC_CH_SZ 10 /* max channel name size */ 147 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ 148 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */ 149 #define STM32_ADC_TIMEOUT_US 100000 150 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) 151 152 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE 153 154 /* External trigger enable */ 155 enum stm32_adc_exten { 156 STM32_EXTEN_SWTRIG, 157 STM32_EXTEN_HWTRIG_RISING_EDGE, 158 STM32_EXTEN_HWTRIG_FALLING_EDGE, 159 STM32_EXTEN_HWTRIG_BOTH_EDGES, 160 }; 161 162 /* extsel - trigger mux selection value */ 163 enum stm32_adc_extsel { 164 STM32_EXT0, 165 STM32_EXT1, 166 STM32_EXT2, 167 STM32_EXT3, 168 STM32_EXT4, 169 STM32_EXT5, 170 STM32_EXT6, 171 STM32_EXT7, 172 STM32_EXT8, 173 STM32_EXT9, 174 STM32_EXT10, 175 STM32_EXT11, 176 STM32_EXT12, 177 STM32_EXT13, 178 STM32_EXT14, 179 STM32_EXT15, 180 STM32_EXT16, 181 STM32_EXT17, 182 STM32_EXT18, 183 STM32_EXT19, 184 STM32_EXT20, 185 }; 186 187 /** 188 * struct stm32_adc_trig_info - ADC trigger info 189 * @name: name of the trigger, corresponding to its source 190 * @extsel: trigger selection 191 */ 192 struct stm32_adc_trig_info { 193 const char *name; 194 enum stm32_adc_extsel extsel; 195 }; 196 197 /** 198 * struct stm32_adc_calib - optional adc calibration data 199 * @calfact_s: Calibration offset for single ended channels 200 * @calfact_d: Calibration offset in differential 201 * @lincalfact: Linearity calibration factor 202 */ 203 struct stm32_adc_calib { 204 u32 calfact_s; 205 u32 calfact_d; 206 u32 lincalfact[STM32H7_LINCALFACT_NUM]; 207 }; 208 209 /** 210 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc 211 * @reg: register offset 212 * @mask: bitfield mask 213 * @shift: left shift 214 */ 215 struct stm32_adc_regs { 216 int reg; 217 int mask; 218 int shift; 219 }; 220 221 /** 222 * stm32_adc_regspec - stm32 registers definition, compatible dependent data 223 * @dr: data register offset 224 * @ier_eoc: interrupt enable register & eocie bitfield 225 * @isr_eoc: interrupt status register & eoc bitfield 226 * @sqr: reference to sequence registers array 227 * @exten: trigger control register & bitfield 228 * @extsel: trigger selection register & bitfield 229 * @res: resolution selection register & bitfield 230 * @smpr: smpr1 & smpr2 registers offset array 231 * @smp_bits: smpr1 & smpr2 index and bitfields 232 */ 233 struct stm32_adc_regspec { 234 const u32 dr; 235 const struct stm32_adc_regs ier_eoc; 236 const struct stm32_adc_regs isr_eoc; 237 const struct stm32_adc_regs *sqr; 238 const struct stm32_adc_regs exten; 239 const struct stm32_adc_regs extsel; 240 const struct stm32_adc_regs res; 241 const u32 smpr[2]; 242 const struct stm32_adc_regs *smp_bits; 243 }; 244 245 struct stm32_adc; 246 247 /** 248 * stm32_adc_cfg - stm32 compatible configuration data 249 * @regs: registers descriptions 250 * @adc_info: per instance input channels definitions 251 * @trigs: external trigger sources 252 * @clk_required: clock is required 253 * @has_vregready: vregready status flag presence 254 * @selfcalib: optional routine for self-calibration 255 * @prepare: optional prepare routine (power-up, enable) 256 * @start_conv: routine to start conversions 257 * @stop_conv: routine to stop conversions 258 * @unprepare: optional unprepare routine (disable, power-down) 259 * @smp_cycles: programmable sampling time (ADC clock cycles) 260 */ 261 struct stm32_adc_cfg { 262 const struct stm32_adc_regspec *regs; 263 const struct stm32_adc_info *adc_info; 264 struct stm32_adc_trig_info *trigs; 265 bool clk_required; 266 bool has_vregready; 267 int (*selfcalib)(struct stm32_adc *); 268 int (*prepare)(struct stm32_adc *); 269 void (*start_conv)(struct stm32_adc *, bool dma); 270 void (*stop_conv)(struct stm32_adc *); 271 void (*unprepare)(struct stm32_adc *); 272 const unsigned int *smp_cycles; 273 }; 274 275 /** 276 * struct stm32_adc - private data of each ADC IIO instance 277 * @common: reference to ADC block common data 278 * @offset: ADC instance register offset in ADC block 279 * @cfg: compatible configuration data 280 * @completion: end of single conversion completion 281 * @buffer: data buffer 282 * @clk: clock for this adc instance 283 * @irq: interrupt for this adc instance 284 * @lock: spinlock 285 * @bufi: data buffer index 286 * @num_conv: expected number of scan conversions 287 * @res: data resolution (e.g. RES bitfield value) 288 * @trigger_polarity: external trigger polarity (e.g. exten) 289 * @dma_chan: dma channel 290 * @rx_buf: dma rx buffer cpu address 291 * @rx_dma_buf: dma rx buffer bus address 292 * @rx_buf_sz: dma rx buffer size 293 * @difsel bitmask to set single-ended/differential channel 294 * @pcsel bitmask to preselect channels on some devices 295 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) 296 * @cal: optional calibration data on some devices 297 * @chan_name: channel name array 298 */ 299 struct stm32_adc { 300 struct stm32_adc_common *common; 301 u32 offset; 302 const struct stm32_adc_cfg *cfg; 303 struct completion completion; 304 u16 buffer[STM32_ADC_MAX_SQ]; 305 struct clk *clk; 306 int irq; 307 spinlock_t lock; /* interrupt lock */ 308 unsigned int bufi; 309 unsigned int num_conv; 310 u32 res; 311 u32 trigger_polarity; 312 struct dma_chan *dma_chan; 313 u8 *rx_buf; 314 dma_addr_t rx_dma_buf; 315 unsigned int rx_buf_sz; 316 u32 difsel; 317 u32 pcsel; 318 u32 smpr_val[2]; 319 struct stm32_adc_calib cal; 320 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ]; 321 }; 322 323 struct stm32_adc_diff_channel { 324 u32 vinp; 325 u32 vinn; 326 }; 327 328 /** 329 * struct stm32_adc_info - stm32 ADC, per instance config data 330 * @max_channels: Number of channels 331 * @resolutions: available resolutions 332 * @num_res: number of available resolutions 333 */ 334 struct stm32_adc_info { 335 int max_channels; 336 const unsigned int *resolutions; 337 const unsigned int num_res; 338 }; 339 340 static const unsigned int stm32f4_adc_resolutions[] = { 341 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */ 342 12, 10, 8, 6, 343 }; 344 345 /* stm32f4 can have up to 16 channels */ 346 static const struct stm32_adc_info stm32f4_adc_info = { 347 .max_channels = 16, 348 .resolutions = stm32f4_adc_resolutions, 349 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 350 }; 351 352 static const unsigned int stm32h7_adc_resolutions[] = { 353 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */ 354 16, 14, 12, 10, 8, 355 }; 356 357 /* stm32h7 can have up to 20 channels */ 358 static const struct stm32_adc_info stm32h7_adc_info = { 359 .max_channels = STM32_ADC_CH_MAX, 360 .resolutions = stm32h7_adc_resolutions, 361 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), 362 }; 363 364 /** 365 * stm32f4_sq - describe regular sequence registers 366 * - L: sequence len (register & bit field) 367 * - SQ1..SQ16: sequence entries (register & bit field) 368 */ 369 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = { 370 /* L: len bit field description to be kept as first element */ 371 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 }, 372 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 373 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 }, 374 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 }, 375 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 }, 376 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 }, 377 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 }, 378 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 }, 379 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 }, 380 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 }, 381 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 }, 382 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 }, 383 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 }, 384 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 }, 385 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 }, 386 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 }, 387 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 }, 388 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 }, 389 }; 390 391 /* STM32F4 external trigger sources for all instances */ 392 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 393 { TIM1_CH1, STM32_EXT0 }, 394 { TIM1_CH2, STM32_EXT1 }, 395 { TIM1_CH3, STM32_EXT2 }, 396 { TIM2_CH2, STM32_EXT3 }, 397 { TIM2_CH3, STM32_EXT4 }, 398 { TIM2_CH4, STM32_EXT5 }, 399 { TIM2_TRGO, STM32_EXT6 }, 400 { TIM3_CH1, STM32_EXT7 }, 401 { TIM3_TRGO, STM32_EXT8 }, 402 { TIM4_CH4, STM32_EXT9 }, 403 { TIM5_CH1, STM32_EXT10 }, 404 { TIM5_CH2, STM32_EXT11 }, 405 { TIM5_CH3, STM32_EXT12 }, 406 { TIM8_CH1, STM32_EXT13 }, 407 { TIM8_TRGO, STM32_EXT14 }, 408 {}, /* sentinel */ 409 }; 410 411 /** 412 * stm32f4_smp_bits[] - describe sampling time register index & bit fields 413 * Sorted so it can be indexed by channel number. 414 */ 415 static const struct stm32_adc_regs stm32f4_smp_bits[] = { 416 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */ 417 { 1, GENMASK(2, 0), 0 }, 418 { 1, GENMASK(5, 3), 3 }, 419 { 1, GENMASK(8, 6), 6 }, 420 { 1, GENMASK(11, 9), 9 }, 421 { 1, GENMASK(14, 12), 12 }, 422 { 1, GENMASK(17, 15), 15 }, 423 { 1, GENMASK(20, 18), 18 }, 424 { 1, GENMASK(23, 21), 21 }, 425 { 1, GENMASK(26, 24), 24 }, 426 { 1, GENMASK(29, 27), 27 }, 427 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */ 428 { 0, GENMASK(2, 0), 0 }, 429 { 0, GENMASK(5, 3), 3 }, 430 { 0, GENMASK(8, 6), 6 }, 431 { 0, GENMASK(11, 9), 9 }, 432 { 0, GENMASK(14, 12), 12 }, 433 { 0, GENMASK(17, 15), 15 }, 434 { 0, GENMASK(20, 18), 18 }, 435 { 0, GENMASK(23, 21), 21 }, 436 { 0, GENMASK(26, 24), 24 }, 437 }; 438 439 /* STM32F4 programmable sampling time (ADC clock cycles) */ 440 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 441 3, 15, 28, 56, 84, 112, 144, 480, 442 }; 443 444 static const struct stm32_adc_regspec stm32f4_adc_regspec = { 445 .dr = STM32F4_ADC_DR, 446 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE }, 447 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC }, 448 .sqr = stm32f4_sq, 449 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT }, 450 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK, 451 STM32F4_EXTSEL_SHIFT }, 452 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT }, 453 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 }, 454 .smp_bits = stm32f4_smp_bits, 455 }; 456 457 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = { 458 /* L: len bit field description to be kept as first element */ 459 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 }, 460 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 461 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 }, 462 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 }, 463 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 }, 464 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 }, 465 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 }, 466 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 }, 467 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 }, 468 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 }, 469 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 }, 470 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 }, 471 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 }, 472 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 }, 473 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 }, 474 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 }, 475 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 }, 476 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 }, 477 }; 478 479 /* STM32H7 external trigger sources for all instances */ 480 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 481 { TIM1_CH1, STM32_EXT0 }, 482 { TIM1_CH2, STM32_EXT1 }, 483 { TIM1_CH3, STM32_EXT2 }, 484 { TIM2_CH2, STM32_EXT3 }, 485 { TIM3_TRGO, STM32_EXT4 }, 486 { TIM4_CH4, STM32_EXT5 }, 487 { TIM8_TRGO, STM32_EXT7 }, 488 { TIM8_TRGO2, STM32_EXT8 }, 489 { TIM1_TRGO, STM32_EXT9 }, 490 { TIM1_TRGO2, STM32_EXT10 }, 491 { TIM2_TRGO, STM32_EXT11 }, 492 { TIM4_TRGO, STM32_EXT12 }, 493 { TIM6_TRGO, STM32_EXT13 }, 494 { TIM15_TRGO, STM32_EXT14 }, 495 { TIM3_CH4, STM32_EXT15 }, 496 { LPTIM1_OUT, STM32_EXT18 }, 497 { LPTIM2_OUT, STM32_EXT19 }, 498 { LPTIM3_OUT, STM32_EXT20 }, 499 {}, 500 }; 501 502 /** 503 * stm32h7_smp_bits - describe sampling time register index & bit fields 504 * Sorted so it can be indexed by channel number. 505 */ 506 static const struct stm32_adc_regs stm32h7_smp_bits[] = { 507 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */ 508 { 0, GENMASK(2, 0), 0 }, 509 { 0, GENMASK(5, 3), 3 }, 510 { 0, GENMASK(8, 6), 6 }, 511 { 0, GENMASK(11, 9), 9 }, 512 { 0, GENMASK(14, 12), 12 }, 513 { 0, GENMASK(17, 15), 15 }, 514 { 0, GENMASK(20, 18), 18 }, 515 { 0, GENMASK(23, 21), 21 }, 516 { 0, GENMASK(26, 24), 24 }, 517 { 0, GENMASK(29, 27), 27 }, 518 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */ 519 { 1, GENMASK(2, 0), 0 }, 520 { 1, GENMASK(5, 3), 3 }, 521 { 1, GENMASK(8, 6), 6 }, 522 { 1, GENMASK(11, 9), 9 }, 523 { 1, GENMASK(14, 12), 12 }, 524 { 1, GENMASK(17, 15), 15 }, 525 { 1, GENMASK(20, 18), 18 }, 526 { 1, GENMASK(23, 21), 21 }, 527 { 1, GENMASK(26, 24), 24 }, 528 { 1, GENMASK(29, 27), 27 }, 529 }; 530 531 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */ 532 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 533 1, 2, 8, 16, 32, 64, 387, 810, 534 }; 535 536 static const struct stm32_adc_regspec stm32h7_adc_regspec = { 537 .dr = STM32H7_ADC_DR, 538 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 539 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 540 .sqr = stm32h7_sq, 541 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 542 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 543 STM32H7_EXTSEL_SHIFT }, 544 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 545 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 546 .smp_bits = stm32h7_smp_bits, 547 }; 548 549 /** 550 * STM32 ADC registers access routines 551 * @adc: stm32 adc instance 552 * @reg: reg offset in adc instance 553 * 554 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. 555 * for adc1, adc2 and adc3. 556 */ 557 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) 558 { 559 return readl_relaxed(adc->common->base + adc->offset + reg); 560 } 561 562 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr) 563 564 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ 565 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ 566 cond, sleep_us, timeout_us) 567 568 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) 569 { 570 return readw_relaxed(adc->common->base + adc->offset + reg); 571 } 572 573 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) 574 { 575 writel_relaxed(val, adc->common->base + adc->offset + reg); 576 } 577 578 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) 579 { 580 unsigned long flags; 581 582 spin_lock_irqsave(&adc->lock, flags); 583 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); 584 spin_unlock_irqrestore(&adc->lock, flags); 585 } 586 587 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) 588 { 589 unsigned long flags; 590 591 spin_lock_irqsave(&adc->lock, flags); 592 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); 593 spin_unlock_irqrestore(&adc->lock, flags); 594 } 595 596 /** 597 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt 598 * @adc: stm32 adc instance 599 */ 600 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) 601 { 602 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, 603 adc->cfg->regs->ier_eoc.mask); 604 }; 605 606 /** 607 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt 608 * @adc: stm32 adc instance 609 */ 610 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) 611 { 612 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, 613 adc->cfg->regs->ier_eoc.mask); 614 } 615 616 static void stm32_adc_set_res(struct stm32_adc *adc) 617 { 618 const struct stm32_adc_regs *res = &adc->cfg->regs->res; 619 u32 val; 620 621 val = stm32_adc_readl(adc, res->reg); 622 val = (val & ~res->mask) | (adc->res << res->shift); 623 stm32_adc_writel(adc, res->reg, val); 624 } 625 626 /** 627 * stm32f4_adc_start_conv() - Start conversions for regular channels. 628 * @adc: stm32 adc instance 629 * @dma: use dma to transfer conversion result 630 * 631 * Start conversions for regular channels. 632 * Also take care of normal or DMA mode. Circular DMA may be used for regular 633 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct 634 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). 635 */ 636 static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma) 637 { 638 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 639 640 if (dma) 641 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, 642 STM32F4_DMA | STM32F4_DDS); 643 644 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); 645 646 /* Wait for Power-up time (tSTAB from datasheet) */ 647 usleep_range(2, 3); 648 649 /* Software start ? (e.g. trigger detection disabled ?) */ 650 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) 651 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); 652 } 653 654 static void stm32f4_adc_stop_conv(struct stm32_adc *adc) 655 { 656 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 657 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); 658 659 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 660 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, 661 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); 662 } 663 664 static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma) 665 { 666 enum stm32h7_adc_dmngt dmngt; 667 unsigned long flags; 668 u32 val; 669 670 if (dma) 671 dmngt = STM32H7_DMNGT_DMA_CIRC; 672 else 673 dmngt = STM32H7_DMNGT_DR_ONLY; 674 675 spin_lock_irqsave(&adc->lock, flags); 676 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); 677 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); 678 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); 679 spin_unlock_irqrestore(&adc->lock, flags); 680 681 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 682 } 683 684 static void stm32h7_adc_stop_conv(struct stm32_adc *adc) 685 { 686 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 687 int ret; 688 u32 val; 689 690 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); 691 692 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 693 !(val & (STM32H7_ADSTART)), 694 100, STM32_ADC_TIMEOUT_US); 695 if (ret) 696 dev_warn(&indio_dev->dev, "stop failed\n"); 697 698 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); 699 } 700 701 static int stm32h7_adc_exit_pwr_down(struct stm32_adc *adc) 702 { 703 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 704 int ret; 705 u32 val; 706 707 /* Exit deep power down, then enable ADC voltage regulator */ 708 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 709 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); 710 711 if (adc->common->rate > STM32H7_BOOST_CLKRATE) 712 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 713 714 /* Wait for startup time */ 715 if (!adc->cfg->has_vregready) { 716 usleep_range(10, 20); 717 return 0; 718 } 719 720 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 721 val & STM32MP1_VREGREADY, 100, 722 STM32_ADC_TIMEOUT_US); 723 if (ret) { 724 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 725 dev_err(&indio_dev->dev, "Failed to exit power down\n"); 726 } 727 728 return ret; 729 } 730 731 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) 732 { 733 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 734 735 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ 736 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 737 } 738 739 static int stm32h7_adc_enable(struct stm32_adc *adc) 740 { 741 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 742 int ret; 743 u32 val; 744 745 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); 746 747 /* Poll for ADRDY to be set (after adc startup time) */ 748 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 749 val & STM32H7_ADRDY, 750 100, STM32_ADC_TIMEOUT_US); 751 if (ret) { 752 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 753 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); 754 } else { 755 /* Clear ADRDY by writing one */ 756 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); 757 } 758 759 return ret; 760 } 761 762 static void stm32h7_adc_disable(struct stm32_adc *adc) 763 { 764 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 765 int ret; 766 u32 val; 767 768 /* Disable ADC and wait until it's effectively disabled */ 769 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 770 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 771 !(val & STM32H7_ADEN), 100, 772 STM32_ADC_TIMEOUT_US); 773 if (ret) 774 dev_warn(&indio_dev->dev, "Failed to disable\n"); 775 } 776 777 /** 778 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result 779 * @adc: stm32 adc instance 780 */ 781 static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc) 782 { 783 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 784 int i, ret; 785 u32 lincalrdyw_mask, val; 786 787 /* Enable adc so LINCALRDYW1..6 bits are writable */ 788 ret = stm32h7_adc_enable(adc); 789 if (ret) 790 return ret; 791 792 /* Read linearity calibration */ 793 lincalrdyw_mask = STM32H7_LINCALRDYW6; 794 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 795 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */ 796 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 797 798 /* Poll: wait calib data to be ready in CALFACT2 register */ 799 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 800 !(val & lincalrdyw_mask), 801 100, STM32_ADC_TIMEOUT_US); 802 if (ret) { 803 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 804 goto disable; 805 } 806 807 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 808 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); 809 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; 810 811 lincalrdyw_mask >>= 1; 812 } 813 814 /* Read offset calibration */ 815 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); 816 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); 817 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; 818 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); 819 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; 820 821 disable: 822 stm32h7_adc_disable(adc); 823 824 return ret; 825 } 826 827 /** 828 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result 829 * @adc: stm32 adc instance 830 * Note: ADC must be enabled, with no on-going conversions. 831 */ 832 static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc) 833 { 834 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 835 int i, ret; 836 u32 lincalrdyw_mask, val; 837 838 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | 839 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); 840 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); 841 842 lincalrdyw_mask = STM32H7_LINCALRDYW6; 843 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 844 /* 845 * Write saved calibration data to shadow registers: 846 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger 847 * data write. Then poll to wait for complete transfer. 848 */ 849 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; 850 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); 851 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 852 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 853 val & lincalrdyw_mask, 854 100, STM32_ADC_TIMEOUT_US); 855 if (ret) { 856 dev_err(&indio_dev->dev, "Failed to write calfact\n"); 857 return ret; 858 } 859 860 /* 861 * Read back calibration data, has two effects: 862 * - It ensures bits LINCALRDYW[6..1] are kept cleared 863 * for next time calibration needs to be restored. 864 * - BTW, bit clear triggers a read, then check data has been 865 * correctly written. 866 */ 867 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 868 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 869 !(val & lincalrdyw_mask), 870 100, STM32_ADC_TIMEOUT_US); 871 if (ret) { 872 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 873 return ret; 874 } 875 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 876 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { 877 dev_err(&indio_dev->dev, "calfact not consistent\n"); 878 return -EIO; 879 } 880 881 lincalrdyw_mask >>= 1; 882 } 883 884 return 0; 885 } 886 887 /** 888 * Fixed timeout value for ADC calibration. 889 * worst cases: 890 * - low clock frequency 891 * - maximum prescalers 892 * Calibration requires: 893 * - 131,072 ADC clock cycle for the linear calibration 894 * - 20 ADC clock cycle for the offset calibration 895 * 896 * Set to 100ms for now 897 */ 898 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000 899 900 /** 901 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down) 902 * @adc: stm32 adc instance 903 * Exit from power down, calibrate ADC, then return to power down. 904 */ 905 static int stm32h7_adc_selfcalib(struct stm32_adc *adc) 906 { 907 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 908 int ret; 909 u32 val; 910 911 ret = stm32h7_adc_exit_pwr_down(adc); 912 if (ret) 913 return ret; 914 915 /* 916 * Select calibration mode: 917 * - Offset calibration for single ended inputs 918 * - No linearity calibration (do it later, before reading it) 919 */ 920 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); 921 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); 922 923 /* Start calibration, then wait for completion */ 924 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 925 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 926 !(val & STM32H7_ADCAL), 100, 927 STM32H7_ADC_CALIB_TIMEOUT_US); 928 if (ret) { 929 dev_err(&indio_dev->dev, "calibration failed\n"); 930 goto pwr_dwn; 931 } 932 933 /* 934 * Select calibration mode, then start calibration: 935 * - Offset calibration for differential input 936 * - Linearity calibration (needs to be done only once for single/diff) 937 * will run simultaneously with offset calibration. 938 */ 939 stm32_adc_set_bits(adc, STM32H7_ADC_CR, 940 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 941 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 942 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 943 !(val & STM32H7_ADCAL), 100, 944 STM32H7_ADC_CALIB_TIMEOUT_US); 945 if (ret) { 946 dev_err(&indio_dev->dev, "calibration failed\n"); 947 goto pwr_dwn; 948 } 949 950 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, 951 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 952 953 /* Read calibration result for future reference */ 954 ret = stm32h7_adc_read_selfcalib(adc); 955 956 pwr_dwn: 957 stm32h7_adc_enter_pwr_down(adc); 958 959 return ret; 960 } 961 962 /** 963 * stm32h7_adc_prepare() - Leave power down mode to enable ADC. 964 * @adc: stm32 adc instance 965 * Leave power down mode. 966 * Configure channels as single ended or differential before enabling ADC. 967 * Enable ADC. 968 * Restore calibration data. 969 * Pre-select channels that may be used in PCSEL (required by input MUX / IO): 970 * - Only one input is selected for single ended (e.g. 'vinp') 971 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn') 972 */ 973 static int stm32h7_adc_prepare(struct stm32_adc *adc) 974 { 975 int ret; 976 977 ret = stm32h7_adc_exit_pwr_down(adc); 978 if (ret) 979 return ret; 980 981 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); 982 983 ret = stm32h7_adc_enable(adc); 984 if (ret) 985 goto pwr_dwn; 986 987 ret = stm32h7_adc_restore_selfcalib(adc); 988 if (ret) 989 goto disable; 990 991 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 992 993 return 0; 994 995 disable: 996 stm32h7_adc_disable(adc); 997 pwr_dwn: 998 stm32h7_adc_enter_pwr_down(adc); 999 1000 return ret; 1001 } 1002 1003 static void stm32h7_adc_unprepare(struct stm32_adc *adc) 1004 { 1005 stm32h7_adc_disable(adc); 1006 stm32h7_adc_enter_pwr_down(adc); 1007 } 1008 1009 /** 1010 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence 1011 * @indio_dev: IIO device 1012 * @scan_mask: channels to be converted 1013 * 1014 * Conversion sequence : 1015 * Apply sampling time settings for all channels. 1016 * Configure ADC scan sequence based on selected channels in scan_mask. 1017 * Add channels to SQR registers, from scan_mask LSB to MSB, then 1018 * program sequence len. 1019 */ 1020 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, 1021 const unsigned long *scan_mask) 1022 { 1023 struct stm32_adc *adc = iio_priv(indio_dev); 1024 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; 1025 const struct iio_chan_spec *chan; 1026 u32 val, bit; 1027 int i = 0; 1028 1029 /* Apply sampling time settings */ 1030 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); 1031 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); 1032 1033 for_each_set_bit(bit, scan_mask, indio_dev->masklength) { 1034 chan = indio_dev->channels + bit; 1035 /* 1036 * Assign one channel per SQ entry in regular 1037 * sequence, starting with SQ1. 1038 */ 1039 i++; 1040 if (i > STM32_ADC_MAX_SQ) 1041 return -EINVAL; 1042 1043 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", 1044 __func__, chan->channel, i); 1045 1046 val = stm32_adc_readl(adc, sqr[i].reg); 1047 val &= ~sqr[i].mask; 1048 val |= chan->channel << sqr[i].shift; 1049 stm32_adc_writel(adc, sqr[i].reg, val); 1050 } 1051 1052 if (!i) 1053 return -EINVAL; 1054 1055 /* Sequence len */ 1056 val = stm32_adc_readl(adc, sqr[0].reg); 1057 val &= ~sqr[0].mask; 1058 val |= ((i - 1) << sqr[0].shift); 1059 stm32_adc_writel(adc, sqr[0].reg, val); 1060 1061 return 0; 1062 } 1063 1064 /** 1065 * stm32_adc_get_trig_extsel() - Get external trigger selection 1066 * @trig: trigger 1067 * 1068 * Returns trigger extsel value, if trig matches, -EINVAL otherwise. 1069 */ 1070 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, 1071 struct iio_trigger *trig) 1072 { 1073 struct stm32_adc *adc = iio_priv(indio_dev); 1074 int i; 1075 1076 /* lookup triggers registered by stm32 timer trigger driver */ 1077 for (i = 0; adc->cfg->trigs[i].name; i++) { 1078 /** 1079 * Checking both stm32 timer trigger type and trig name 1080 * should be safe against arbitrary trigger names. 1081 */ 1082 if ((is_stm32_timer_trigger(trig) || 1083 is_stm32_lptim_trigger(trig)) && 1084 !strcmp(adc->cfg->trigs[i].name, trig->name)) { 1085 return adc->cfg->trigs[i].extsel; 1086 } 1087 } 1088 1089 return -EINVAL; 1090 } 1091 1092 /** 1093 * stm32_adc_set_trig() - Set a regular trigger 1094 * @indio_dev: IIO device 1095 * @trig: IIO trigger 1096 * 1097 * Set trigger source/polarity (e.g. SW, or HW with polarity) : 1098 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) 1099 * - if HW trigger enabled, set source & polarity 1100 */ 1101 static int stm32_adc_set_trig(struct iio_dev *indio_dev, 1102 struct iio_trigger *trig) 1103 { 1104 struct stm32_adc *adc = iio_priv(indio_dev); 1105 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; 1106 unsigned long flags; 1107 int ret; 1108 1109 if (trig) { 1110 ret = stm32_adc_get_trig_extsel(indio_dev, trig); 1111 if (ret < 0) 1112 return ret; 1113 1114 /* set trigger source and polarity (default to rising edge) */ 1115 extsel = ret; 1116 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; 1117 } 1118 1119 spin_lock_irqsave(&adc->lock, flags); 1120 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); 1121 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); 1122 val |= exten << adc->cfg->regs->exten.shift; 1123 val |= extsel << adc->cfg->regs->extsel.shift; 1124 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); 1125 spin_unlock_irqrestore(&adc->lock, flags); 1126 1127 return 0; 1128 } 1129 1130 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, 1131 const struct iio_chan_spec *chan, 1132 unsigned int type) 1133 { 1134 struct stm32_adc *adc = iio_priv(indio_dev); 1135 1136 adc->trigger_polarity = type; 1137 1138 return 0; 1139 } 1140 1141 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, 1142 const struct iio_chan_spec *chan) 1143 { 1144 struct stm32_adc *adc = iio_priv(indio_dev); 1145 1146 return adc->trigger_polarity; 1147 } 1148 1149 static const char * const stm32_trig_pol_items[] = { 1150 "rising-edge", "falling-edge", "both-edges", 1151 }; 1152 1153 static const struct iio_enum stm32_adc_trig_pol = { 1154 .items = stm32_trig_pol_items, 1155 .num_items = ARRAY_SIZE(stm32_trig_pol_items), 1156 .get = stm32_adc_get_trig_pol, 1157 .set = stm32_adc_set_trig_pol, 1158 }; 1159 1160 /** 1161 * stm32_adc_single_conv() - Performs a single conversion 1162 * @indio_dev: IIO device 1163 * @chan: IIO channel 1164 * @res: conversion result 1165 * 1166 * The function performs a single conversion on a given channel: 1167 * - Apply sampling time settings 1168 * - Program sequencer with one channel (e.g. in SQ1 with len = 1) 1169 * - Use SW trigger 1170 * - Start conversion, then wait for interrupt completion. 1171 */ 1172 static int stm32_adc_single_conv(struct iio_dev *indio_dev, 1173 const struct iio_chan_spec *chan, 1174 int *res) 1175 { 1176 struct stm32_adc *adc = iio_priv(indio_dev); 1177 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1178 long timeout; 1179 u32 val; 1180 int ret; 1181 1182 reinit_completion(&adc->completion); 1183 1184 adc->bufi = 0; 1185 1186 if (adc->cfg->prepare) { 1187 ret = adc->cfg->prepare(adc); 1188 if (ret) 1189 return ret; 1190 } 1191 1192 /* Apply sampling time settings */ 1193 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); 1194 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); 1195 1196 /* Program chan number in regular sequence (SQ1) */ 1197 val = stm32_adc_readl(adc, regs->sqr[1].reg); 1198 val &= ~regs->sqr[1].mask; 1199 val |= chan->channel << regs->sqr[1].shift; 1200 stm32_adc_writel(adc, regs->sqr[1].reg, val); 1201 1202 /* Set regular sequence len (0 for 1 conversion) */ 1203 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); 1204 1205 /* Trigger detection disabled (conversion can be launched in SW) */ 1206 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); 1207 1208 stm32_adc_conv_irq_enable(adc); 1209 1210 adc->cfg->start_conv(adc, false); 1211 1212 timeout = wait_for_completion_interruptible_timeout( 1213 &adc->completion, STM32_ADC_TIMEOUT); 1214 if (timeout == 0) { 1215 ret = -ETIMEDOUT; 1216 } else if (timeout < 0) { 1217 ret = timeout; 1218 } else { 1219 *res = adc->buffer[0]; 1220 ret = IIO_VAL_INT; 1221 } 1222 1223 adc->cfg->stop_conv(adc); 1224 1225 stm32_adc_conv_irq_disable(adc); 1226 1227 if (adc->cfg->unprepare) 1228 adc->cfg->unprepare(adc); 1229 1230 return ret; 1231 } 1232 1233 static int stm32_adc_read_raw(struct iio_dev *indio_dev, 1234 struct iio_chan_spec const *chan, 1235 int *val, int *val2, long mask) 1236 { 1237 struct stm32_adc *adc = iio_priv(indio_dev); 1238 int ret; 1239 1240 switch (mask) { 1241 case IIO_CHAN_INFO_RAW: 1242 ret = iio_device_claim_direct_mode(indio_dev); 1243 if (ret) 1244 return ret; 1245 if (chan->type == IIO_VOLTAGE) 1246 ret = stm32_adc_single_conv(indio_dev, chan, val); 1247 else 1248 ret = -EINVAL; 1249 iio_device_release_direct_mode(indio_dev); 1250 return ret; 1251 1252 case IIO_CHAN_INFO_SCALE: 1253 if (chan->differential) { 1254 *val = adc->common->vref_mv * 2; 1255 *val2 = chan->scan_type.realbits; 1256 } else { 1257 *val = adc->common->vref_mv; 1258 *val2 = chan->scan_type.realbits; 1259 } 1260 return IIO_VAL_FRACTIONAL_LOG2; 1261 1262 case IIO_CHAN_INFO_OFFSET: 1263 if (chan->differential) 1264 /* ADC_full_scale / 2 */ 1265 *val = -((1 << chan->scan_type.realbits) / 2); 1266 else 1267 *val = 0; 1268 return IIO_VAL_INT; 1269 1270 default: 1271 return -EINVAL; 1272 } 1273 } 1274 1275 static irqreturn_t stm32_adc_isr(int irq, void *data) 1276 { 1277 struct stm32_adc *adc = data; 1278 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1279 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1280 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1281 1282 if (status & regs->isr_eoc.mask) { 1283 /* Reading DR also clears EOC status flag */ 1284 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); 1285 if (iio_buffer_enabled(indio_dev)) { 1286 adc->bufi++; 1287 if (adc->bufi >= adc->num_conv) { 1288 stm32_adc_conv_irq_disable(adc); 1289 iio_trigger_poll(indio_dev->trig); 1290 } 1291 } else { 1292 complete(&adc->completion); 1293 } 1294 return IRQ_HANDLED; 1295 } 1296 1297 return IRQ_NONE; 1298 } 1299 1300 /** 1301 * stm32_adc_validate_trigger() - validate trigger for stm32 adc 1302 * @indio_dev: IIO device 1303 * @trig: new trigger 1304 * 1305 * Returns: 0 if trig matches one of the triggers registered by stm32 adc 1306 * driver, -EINVAL otherwise. 1307 */ 1308 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, 1309 struct iio_trigger *trig) 1310 { 1311 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; 1312 } 1313 1314 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1315 { 1316 struct stm32_adc *adc = iio_priv(indio_dev); 1317 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2; 1318 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE; 1319 1320 /* 1321 * dma cyclic transfers are used, buffer is split into two periods. 1322 * There should be : 1323 * - always one buffer (period) dma is working on 1324 * - one buffer (period) driver can push with iio_trigger_poll(). 1325 */ 1326 watermark = min(watermark, val * (unsigned)(sizeof(u16))); 1327 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); 1328 1329 return 0; 1330 } 1331 1332 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, 1333 const unsigned long *scan_mask) 1334 { 1335 struct stm32_adc *adc = iio_priv(indio_dev); 1336 int ret; 1337 1338 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); 1339 1340 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask); 1341 if (ret) 1342 return ret; 1343 1344 return 0; 1345 } 1346 1347 static int stm32_adc_of_xlate(struct iio_dev *indio_dev, 1348 const struct of_phandle_args *iiospec) 1349 { 1350 int i; 1351 1352 for (i = 0; i < indio_dev->num_channels; i++) 1353 if (indio_dev->channels[i].channel == iiospec->args[0]) 1354 return i; 1355 1356 return -EINVAL; 1357 } 1358 1359 /** 1360 * stm32_adc_debugfs_reg_access - read or write register value 1361 * 1362 * To read a value from an ADC register: 1363 * echo [ADC reg offset] > direct_reg_access 1364 * cat direct_reg_access 1365 * 1366 * To write a value in a ADC register: 1367 * echo [ADC_reg_offset] [value] > direct_reg_access 1368 */ 1369 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, 1370 unsigned reg, unsigned writeval, 1371 unsigned *readval) 1372 { 1373 struct stm32_adc *adc = iio_priv(indio_dev); 1374 1375 if (!readval) 1376 stm32_adc_writel(adc, reg, writeval); 1377 else 1378 *readval = stm32_adc_readl(adc, reg); 1379 1380 return 0; 1381 } 1382 1383 static const struct iio_info stm32_adc_iio_info = { 1384 .read_raw = stm32_adc_read_raw, 1385 .validate_trigger = stm32_adc_validate_trigger, 1386 .hwfifo_set_watermark = stm32_adc_set_watermark, 1387 .update_scan_mode = stm32_adc_update_scan_mode, 1388 .debugfs_reg_access = stm32_adc_debugfs_reg_access, 1389 .of_xlate = stm32_adc_of_xlate, 1390 }; 1391 1392 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) 1393 { 1394 struct dma_tx_state state; 1395 enum dma_status status; 1396 1397 status = dmaengine_tx_status(adc->dma_chan, 1398 adc->dma_chan->cookie, 1399 &state); 1400 if (status == DMA_IN_PROGRESS) { 1401 /* Residue is size in bytes from end of buffer */ 1402 unsigned int i = adc->rx_buf_sz - state.residue; 1403 unsigned int size; 1404 1405 /* Return available bytes */ 1406 if (i >= adc->bufi) 1407 size = i - adc->bufi; 1408 else 1409 size = adc->rx_buf_sz + i - adc->bufi; 1410 1411 return size; 1412 } 1413 1414 return 0; 1415 } 1416 1417 static void stm32_adc_dma_buffer_done(void *data) 1418 { 1419 struct iio_dev *indio_dev = data; 1420 1421 iio_trigger_poll_chained(indio_dev->trig); 1422 } 1423 1424 static int stm32_adc_dma_start(struct iio_dev *indio_dev) 1425 { 1426 struct stm32_adc *adc = iio_priv(indio_dev); 1427 struct dma_async_tx_descriptor *desc; 1428 dma_cookie_t cookie; 1429 int ret; 1430 1431 if (!adc->dma_chan) 1432 return 0; 1433 1434 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 1435 adc->rx_buf_sz, adc->rx_buf_sz / 2); 1436 1437 /* Prepare a DMA cyclic transaction */ 1438 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 1439 adc->rx_dma_buf, 1440 adc->rx_buf_sz, adc->rx_buf_sz / 2, 1441 DMA_DEV_TO_MEM, 1442 DMA_PREP_INTERRUPT); 1443 if (!desc) 1444 return -EBUSY; 1445 1446 desc->callback = stm32_adc_dma_buffer_done; 1447 desc->callback_param = indio_dev; 1448 1449 cookie = dmaengine_submit(desc); 1450 ret = dma_submit_error(cookie); 1451 if (ret) { 1452 dmaengine_terminate_all(adc->dma_chan); 1453 return ret; 1454 } 1455 1456 /* Issue pending DMA requests */ 1457 dma_async_issue_pending(adc->dma_chan); 1458 1459 return 0; 1460 } 1461 1462 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) 1463 { 1464 struct stm32_adc *adc = iio_priv(indio_dev); 1465 int ret; 1466 1467 if (adc->cfg->prepare) { 1468 ret = adc->cfg->prepare(adc); 1469 if (ret) 1470 return ret; 1471 } 1472 1473 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); 1474 if (ret) { 1475 dev_err(&indio_dev->dev, "Can't set trigger\n"); 1476 goto err_unprepare; 1477 } 1478 1479 ret = stm32_adc_dma_start(indio_dev); 1480 if (ret) { 1481 dev_err(&indio_dev->dev, "Can't start dma\n"); 1482 goto err_clr_trig; 1483 } 1484 1485 ret = iio_triggered_buffer_postenable(indio_dev); 1486 if (ret < 0) 1487 goto err_stop_dma; 1488 1489 /* Reset adc buffer index */ 1490 adc->bufi = 0; 1491 1492 if (!adc->dma_chan) 1493 stm32_adc_conv_irq_enable(adc); 1494 1495 adc->cfg->start_conv(adc, !!adc->dma_chan); 1496 1497 return 0; 1498 1499 err_stop_dma: 1500 if (adc->dma_chan) 1501 dmaengine_terminate_all(adc->dma_chan); 1502 err_clr_trig: 1503 stm32_adc_set_trig(indio_dev, NULL); 1504 err_unprepare: 1505 if (adc->cfg->unprepare) 1506 adc->cfg->unprepare(adc); 1507 1508 return ret; 1509 } 1510 1511 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) 1512 { 1513 struct stm32_adc *adc = iio_priv(indio_dev); 1514 int ret; 1515 1516 adc->cfg->stop_conv(adc); 1517 if (!adc->dma_chan) 1518 stm32_adc_conv_irq_disable(adc); 1519 1520 ret = iio_triggered_buffer_predisable(indio_dev); 1521 if (ret < 0) 1522 dev_err(&indio_dev->dev, "predisable failed\n"); 1523 1524 if (adc->dma_chan) 1525 dmaengine_terminate_all(adc->dma_chan); 1526 1527 if (stm32_adc_set_trig(indio_dev, NULL)) 1528 dev_err(&indio_dev->dev, "Can't clear trigger\n"); 1529 1530 if (adc->cfg->unprepare) 1531 adc->cfg->unprepare(adc); 1532 1533 return ret; 1534 } 1535 1536 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = { 1537 .postenable = &stm32_adc_buffer_postenable, 1538 .predisable = &stm32_adc_buffer_predisable, 1539 }; 1540 1541 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) 1542 { 1543 struct iio_poll_func *pf = p; 1544 struct iio_dev *indio_dev = pf->indio_dev; 1545 struct stm32_adc *adc = iio_priv(indio_dev); 1546 1547 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1548 1549 if (!adc->dma_chan) { 1550 /* reset buffer index */ 1551 adc->bufi = 0; 1552 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, 1553 pf->timestamp); 1554 } else { 1555 int residue = stm32_adc_dma_residue(adc); 1556 1557 while (residue >= indio_dev->scan_bytes) { 1558 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1559 1560 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 1561 pf->timestamp); 1562 residue -= indio_dev->scan_bytes; 1563 adc->bufi += indio_dev->scan_bytes; 1564 if (adc->bufi >= adc->rx_buf_sz) 1565 adc->bufi = 0; 1566 } 1567 } 1568 1569 iio_trigger_notify_done(indio_dev->trig); 1570 1571 /* re-enable eoc irq */ 1572 if (!adc->dma_chan) 1573 stm32_adc_conv_irq_enable(adc); 1574 1575 return IRQ_HANDLED; 1576 } 1577 1578 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = { 1579 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), 1580 { 1581 .name = "trigger_polarity_available", 1582 .shared = IIO_SHARED_BY_ALL, 1583 .read = iio_enum_available_read, 1584 .private = (uintptr_t)&stm32_adc_trig_pol, 1585 }, 1586 {}, 1587 }; 1588 1589 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev) 1590 { 1591 struct device_node *node = indio_dev->dev.of_node; 1592 struct stm32_adc *adc = iio_priv(indio_dev); 1593 unsigned int i; 1594 u32 res; 1595 1596 if (of_property_read_u32(node, "assigned-resolution-bits", &res)) 1597 res = adc->cfg->adc_info->resolutions[0]; 1598 1599 for (i = 0; i < adc->cfg->adc_info->num_res; i++) 1600 if (res == adc->cfg->adc_info->resolutions[i]) 1601 break; 1602 if (i >= adc->cfg->adc_info->num_res) { 1603 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); 1604 return -EINVAL; 1605 } 1606 1607 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); 1608 adc->res = i; 1609 1610 return 0; 1611 } 1612 1613 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) 1614 { 1615 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; 1616 u32 period_ns, shift = smpr->shift, mask = smpr->mask; 1617 unsigned int smp, r = smpr->reg; 1618 1619 /* Determine sampling time (ADC clock cycles) */ 1620 period_ns = NSEC_PER_SEC / adc->common->rate; 1621 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++) 1622 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) 1623 break; 1624 if (smp > STM32_ADC_MAX_SMP) 1625 smp = STM32_ADC_MAX_SMP; 1626 1627 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ 1628 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); 1629 } 1630 1631 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, 1632 struct iio_chan_spec *chan, u32 vinp, 1633 u32 vinn, int scan_index, bool differential) 1634 { 1635 struct stm32_adc *adc = iio_priv(indio_dev); 1636 char *name = adc->chan_name[vinp]; 1637 1638 chan->type = IIO_VOLTAGE; 1639 chan->channel = vinp; 1640 if (differential) { 1641 chan->differential = 1; 1642 chan->channel2 = vinn; 1643 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); 1644 } else { 1645 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp); 1646 } 1647 chan->datasheet_name = name; 1648 chan->scan_index = scan_index; 1649 chan->indexed = 1; 1650 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 1651 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 1652 BIT(IIO_CHAN_INFO_OFFSET); 1653 chan->scan_type.sign = 'u'; 1654 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; 1655 chan->scan_type.storagebits = 16; 1656 chan->ext_info = stm32_adc_ext_info; 1657 1658 /* pre-build selected channels mask */ 1659 adc->pcsel |= BIT(chan->channel); 1660 if (differential) { 1661 /* pre-build diff channels mask */ 1662 adc->difsel |= BIT(chan->channel); 1663 /* Also add negative input to pre-selected channels */ 1664 adc->pcsel |= BIT(chan->channel2); 1665 } 1666 } 1667 1668 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev) 1669 { 1670 struct device_node *node = indio_dev->dev.of_node; 1671 struct stm32_adc *adc = iio_priv(indio_dev); 1672 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 1673 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; 1674 struct property *prop; 1675 const __be32 *cur; 1676 struct iio_chan_spec *channels; 1677 int scan_index = 0, num_channels = 0, num_diff = 0, ret, i; 1678 u32 val, smp = 0; 1679 1680 ret = of_property_count_u32_elems(node, "st,adc-channels"); 1681 if (ret > adc_info->max_channels) { 1682 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); 1683 return -EINVAL; 1684 } else if (ret > 0) { 1685 num_channels += ret; 1686 } 1687 1688 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels", 1689 sizeof(*diff)); 1690 if (ret > adc_info->max_channels) { 1691 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); 1692 return -EINVAL; 1693 } else if (ret > 0) { 1694 int size = ret * sizeof(*diff) / sizeof(u32); 1695 1696 num_diff = ret; 1697 num_channels += ret; 1698 ret = of_property_read_u32_array(node, "st,adc-diff-channels", 1699 (u32 *)diff, size); 1700 if (ret) 1701 return ret; 1702 } 1703 1704 if (!num_channels) { 1705 dev_err(&indio_dev->dev, "No channels configured\n"); 1706 return -ENODATA; 1707 } 1708 1709 /* Optional sample time is provided either for each, or all channels */ 1710 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs"); 1711 if (ret > 1 && ret != num_channels) { 1712 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); 1713 return -EINVAL; 1714 } 1715 1716 channels = devm_kcalloc(&indio_dev->dev, num_channels, 1717 sizeof(struct iio_chan_spec), GFP_KERNEL); 1718 if (!channels) 1719 return -ENOMEM; 1720 1721 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { 1722 if (val >= adc_info->max_channels) { 1723 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); 1724 return -EINVAL; 1725 } 1726 1727 /* Channel can't be configured both as single-ended & diff */ 1728 for (i = 0; i < num_diff; i++) { 1729 if (val == diff[i].vinp) { 1730 dev_err(&indio_dev->dev, 1731 "channel %d miss-configured\n", val); 1732 return -EINVAL; 1733 } 1734 } 1735 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 1736 0, scan_index, false); 1737 scan_index++; 1738 } 1739 1740 for (i = 0; i < num_diff; i++) { 1741 if (diff[i].vinp >= adc_info->max_channels || 1742 diff[i].vinn >= adc_info->max_channels) { 1743 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 1744 diff[i].vinp, diff[i].vinn); 1745 return -EINVAL; 1746 } 1747 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 1748 diff[i].vinp, diff[i].vinn, scan_index, 1749 true); 1750 scan_index++; 1751 } 1752 1753 for (i = 0; i < scan_index; i++) { 1754 /* 1755 * Using of_property_read_u32_index(), smp value will only be 1756 * modified if valid u32 value can be decoded. This allows to 1757 * get either no value, 1 shared value for all indexes, or one 1758 * value per channel. 1759 */ 1760 of_property_read_u32_index(node, "st,min-sample-time-nsecs", 1761 i, &smp); 1762 /* Prepare sampling time settings */ 1763 stm32_adc_smpr_init(adc, channels[i].channel, smp); 1764 } 1765 1766 indio_dev->num_channels = scan_index; 1767 indio_dev->channels = channels; 1768 1769 return 0; 1770 } 1771 1772 static int stm32_adc_dma_request(struct iio_dev *indio_dev) 1773 { 1774 struct stm32_adc *adc = iio_priv(indio_dev); 1775 struct dma_slave_config config; 1776 int ret; 1777 1778 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx"); 1779 if (!adc->dma_chan) 1780 return 0; 1781 1782 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 1783 STM32_DMA_BUFFER_SIZE, 1784 &adc->rx_dma_buf, GFP_KERNEL); 1785 if (!adc->rx_buf) { 1786 ret = -ENOMEM; 1787 goto err_release; 1788 } 1789 1790 /* Configure DMA channel to read data register */ 1791 memset(&config, 0, sizeof(config)); 1792 config.src_addr = (dma_addr_t)adc->common->phys_base; 1793 config.src_addr += adc->offset + adc->cfg->regs->dr; 1794 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1795 1796 ret = dmaengine_slave_config(adc->dma_chan, &config); 1797 if (ret) 1798 goto err_free; 1799 1800 return 0; 1801 1802 err_free: 1803 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, 1804 adc->rx_buf, adc->rx_dma_buf); 1805 err_release: 1806 dma_release_channel(adc->dma_chan); 1807 1808 return ret; 1809 } 1810 1811 static int stm32_adc_probe(struct platform_device *pdev) 1812 { 1813 struct iio_dev *indio_dev; 1814 struct device *dev = &pdev->dev; 1815 struct stm32_adc *adc; 1816 int ret; 1817 1818 if (!pdev->dev.of_node) 1819 return -ENODEV; 1820 1821 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 1822 if (!indio_dev) 1823 return -ENOMEM; 1824 1825 adc = iio_priv(indio_dev); 1826 adc->common = dev_get_drvdata(pdev->dev.parent); 1827 spin_lock_init(&adc->lock); 1828 init_completion(&adc->completion); 1829 adc->cfg = (const struct stm32_adc_cfg *) 1830 of_match_device(dev->driver->of_match_table, dev)->data; 1831 1832 indio_dev->name = dev_name(&pdev->dev); 1833 indio_dev->dev.parent = &pdev->dev; 1834 indio_dev->dev.of_node = pdev->dev.of_node; 1835 indio_dev->info = &stm32_adc_iio_info; 1836 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; 1837 1838 platform_set_drvdata(pdev, adc); 1839 1840 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset); 1841 if (ret != 0) { 1842 dev_err(&pdev->dev, "missing reg property\n"); 1843 return -EINVAL; 1844 } 1845 1846 adc->irq = platform_get_irq(pdev, 0); 1847 if (adc->irq < 0) { 1848 dev_err(&pdev->dev, "failed to get irq\n"); 1849 return adc->irq; 1850 } 1851 1852 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr, 1853 0, pdev->name, adc); 1854 if (ret) { 1855 dev_err(&pdev->dev, "failed to request IRQ\n"); 1856 return ret; 1857 } 1858 1859 adc->clk = devm_clk_get(&pdev->dev, NULL); 1860 if (IS_ERR(adc->clk)) { 1861 ret = PTR_ERR(adc->clk); 1862 if (ret == -ENOENT && !adc->cfg->clk_required) { 1863 adc->clk = NULL; 1864 } else { 1865 dev_err(&pdev->dev, "Can't get clock\n"); 1866 return ret; 1867 } 1868 } 1869 1870 if (adc->clk) { 1871 ret = clk_prepare_enable(adc->clk); 1872 if (ret < 0) { 1873 dev_err(&pdev->dev, "clk enable failed\n"); 1874 return ret; 1875 } 1876 } 1877 1878 ret = stm32_adc_of_get_resolution(indio_dev); 1879 if (ret < 0) 1880 goto err_clk_disable; 1881 stm32_adc_set_res(adc); 1882 1883 if (adc->cfg->selfcalib) { 1884 ret = adc->cfg->selfcalib(adc); 1885 if (ret) 1886 goto err_clk_disable; 1887 } 1888 1889 ret = stm32_adc_chan_of_init(indio_dev); 1890 if (ret < 0) 1891 goto err_clk_disable; 1892 1893 ret = stm32_adc_dma_request(indio_dev); 1894 if (ret < 0) 1895 goto err_clk_disable; 1896 1897 ret = iio_triggered_buffer_setup(indio_dev, 1898 &iio_pollfunc_store_time, 1899 &stm32_adc_trigger_handler, 1900 &stm32_adc_buffer_setup_ops); 1901 if (ret) { 1902 dev_err(&pdev->dev, "buffer setup failed\n"); 1903 goto err_dma_disable; 1904 } 1905 1906 ret = iio_device_register(indio_dev); 1907 if (ret) { 1908 dev_err(&pdev->dev, "iio dev register failed\n"); 1909 goto err_buffer_cleanup; 1910 } 1911 1912 return 0; 1913 1914 err_buffer_cleanup: 1915 iio_triggered_buffer_cleanup(indio_dev); 1916 1917 err_dma_disable: 1918 if (adc->dma_chan) { 1919 dma_free_coherent(adc->dma_chan->device->dev, 1920 STM32_DMA_BUFFER_SIZE, 1921 adc->rx_buf, adc->rx_dma_buf); 1922 dma_release_channel(adc->dma_chan); 1923 } 1924 err_clk_disable: 1925 if (adc->clk) 1926 clk_disable_unprepare(adc->clk); 1927 1928 return ret; 1929 } 1930 1931 static int stm32_adc_remove(struct platform_device *pdev) 1932 { 1933 struct stm32_adc *adc = platform_get_drvdata(pdev); 1934 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1935 1936 iio_device_unregister(indio_dev); 1937 iio_triggered_buffer_cleanup(indio_dev); 1938 if (adc->dma_chan) { 1939 dma_free_coherent(adc->dma_chan->device->dev, 1940 STM32_DMA_BUFFER_SIZE, 1941 adc->rx_buf, adc->rx_dma_buf); 1942 dma_release_channel(adc->dma_chan); 1943 } 1944 if (adc->clk) 1945 clk_disable_unprepare(adc->clk); 1946 1947 return 0; 1948 } 1949 1950 static const struct stm32_adc_cfg stm32f4_adc_cfg = { 1951 .regs = &stm32f4_adc_regspec, 1952 .adc_info = &stm32f4_adc_info, 1953 .trigs = stm32f4_adc_trigs, 1954 .clk_required = true, 1955 .start_conv = stm32f4_adc_start_conv, 1956 .stop_conv = stm32f4_adc_stop_conv, 1957 .smp_cycles = stm32f4_adc_smp_cycles, 1958 }; 1959 1960 static const struct stm32_adc_cfg stm32h7_adc_cfg = { 1961 .regs = &stm32h7_adc_regspec, 1962 .adc_info = &stm32h7_adc_info, 1963 .trigs = stm32h7_adc_trigs, 1964 .selfcalib = stm32h7_adc_selfcalib, 1965 .start_conv = stm32h7_adc_start_conv, 1966 .stop_conv = stm32h7_adc_stop_conv, 1967 .prepare = stm32h7_adc_prepare, 1968 .unprepare = stm32h7_adc_unprepare, 1969 .smp_cycles = stm32h7_adc_smp_cycles, 1970 }; 1971 1972 static const struct stm32_adc_cfg stm32mp1_adc_cfg = { 1973 .regs = &stm32h7_adc_regspec, 1974 .adc_info = &stm32h7_adc_info, 1975 .trigs = stm32h7_adc_trigs, 1976 .has_vregready = true, 1977 .selfcalib = stm32h7_adc_selfcalib, 1978 .start_conv = stm32h7_adc_start_conv, 1979 .stop_conv = stm32h7_adc_stop_conv, 1980 .prepare = stm32h7_adc_prepare, 1981 .unprepare = stm32h7_adc_unprepare, 1982 .smp_cycles = stm32h7_adc_smp_cycles, 1983 }; 1984 1985 static const struct of_device_id stm32_adc_of_match[] = { 1986 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, 1987 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, 1988 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg }, 1989 {}, 1990 }; 1991 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 1992 1993 static struct platform_driver stm32_adc_driver = { 1994 .probe = stm32_adc_probe, 1995 .remove = stm32_adc_remove, 1996 .driver = { 1997 .name = "stm32-adc", 1998 .of_match_table = stm32_adc_of_match, 1999 }, 2000 }; 2001 module_platform_driver(stm32_adc_driver); 2002 2003 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 2004 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver"); 2005 MODULE_LICENSE("GPL v2"); 2006 MODULE_ALIAS("platform:stm32-adc"); 2007