1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/iio/iio.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/timer/stm32-lptim-trigger.h> 16 #include <linux/iio/timer/stm32-timer-trigger.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/iio/triggered_buffer.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/module.h> 24 #include <linux/nvmem-consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 30 #include "stm32-adc-core.h" 31 32 /* Number of linear calibration shadow registers / LINCALRDYW control bits */ 33 #define STM32H7_LINCALFACT_NUM 6 34 35 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ 36 #define STM32H7_BOOST_CLKRATE 20000000UL 37 38 #define STM32_ADC_CH_MAX 20 /* max number of channels */ 39 #define STM32_ADC_CH_SZ 16 /* max channel name size */ 40 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ 41 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */ 42 #define STM32_ADC_TIMEOUT_US 100000 43 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) 44 #define STM32_ADC_HW_STOP_DELAY_MS 100 45 #define STM32_ADC_VREFINT_VOLTAGE 3300 46 47 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE 48 49 /* External trigger enable */ 50 enum stm32_adc_exten { 51 STM32_EXTEN_SWTRIG, 52 STM32_EXTEN_HWTRIG_RISING_EDGE, 53 STM32_EXTEN_HWTRIG_FALLING_EDGE, 54 STM32_EXTEN_HWTRIG_BOTH_EDGES, 55 }; 56 57 /* extsel - trigger mux selection value */ 58 enum stm32_adc_extsel { 59 STM32_EXT0, 60 STM32_EXT1, 61 STM32_EXT2, 62 STM32_EXT3, 63 STM32_EXT4, 64 STM32_EXT5, 65 STM32_EXT6, 66 STM32_EXT7, 67 STM32_EXT8, 68 STM32_EXT9, 69 STM32_EXT10, 70 STM32_EXT11, 71 STM32_EXT12, 72 STM32_EXT13, 73 STM32_EXT14, 74 STM32_EXT15, 75 STM32_EXT16, 76 STM32_EXT17, 77 STM32_EXT18, 78 STM32_EXT19, 79 STM32_EXT20, 80 }; 81 82 enum stm32_adc_int_ch { 83 STM32_ADC_INT_CH_NONE = -1, 84 STM32_ADC_INT_CH_VDDCORE, 85 STM32_ADC_INT_CH_VREFINT, 86 STM32_ADC_INT_CH_VBAT, 87 STM32_ADC_INT_CH_NB, 88 }; 89 90 /** 91 * struct stm32_adc_ic - ADC internal channels 92 * @name: name of the internal channel 93 * @idx: internal channel enum index 94 */ 95 struct stm32_adc_ic { 96 const char *name; 97 u32 idx; 98 }; 99 100 static const struct stm32_adc_ic stm32_adc_ic[STM32_ADC_INT_CH_NB] = { 101 { "vddcore", STM32_ADC_INT_CH_VDDCORE }, 102 { "vrefint", STM32_ADC_INT_CH_VREFINT }, 103 { "vbat", STM32_ADC_INT_CH_VBAT }, 104 }; 105 106 /** 107 * struct stm32_adc_trig_info - ADC trigger info 108 * @name: name of the trigger, corresponding to its source 109 * @extsel: trigger selection 110 */ 111 struct stm32_adc_trig_info { 112 const char *name; 113 enum stm32_adc_extsel extsel; 114 }; 115 116 /** 117 * struct stm32_adc_calib - optional adc calibration data 118 * @calfact_s: Calibration offset for single ended channels 119 * @calfact_d: Calibration offset in differential 120 * @lincalfact: Linearity calibration factor 121 * @calibrated: Indicates calibration status 122 */ 123 struct stm32_adc_calib { 124 u32 calfact_s; 125 u32 calfact_d; 126 u32 lincalfact[STM32H7_LINCALFACT_NUM]; 127 bool calibrated; 128 }; 129 130 /** 131 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc 132 * @reg: register offset 133 * @mask: bitfield mask 134 * @shift: left shift 135 */ 136 struct stm32_adc_regs { 137 int reg; 138 int mask; 139 int shift; 140 }; 141 142 /** 143 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data 144 * @vrefint_cal: vrefint calibration value from nvmem 145 * @vrefint_data: vrefint actual value 146 */ 147 struct stm32_adc_vrefint { 148 u32 vrefint_cal; 149 u32 vrefint_data; 150 }; 151 152 /** 153 * struct stm32_adc_regspec - stm32 registers definition 154 * @dr: data register offset 155 * @ier_eoc: interrupt enable register & eocie bitfield 156 * @ier_ovr: interrupt enable register & overrun bitfield 157 * @isr_eoc: interrupt status register & eoc bitfield 158 * @isr_ovr: interrupt status register & overrun bitfield 159 * @sqr: reference to sequence registers array 160 * @exten: trigger control register & bitfield 161 * @extsel: trigger selection register & bitfield 162 * @res: resolution selection register & bitfield 163 * @smpr: smpr1 & smpr2 registers offset array 164 * @smp_bits: smpr1 & smpr2 index and bitfields 165 * @or_vdd: option register & vddcore bitfield 166 * @ccr_vbat: common register & vbat bitfield 167 * @ccr_vref: common register & vrefint bitfield 168 */ 169 struct stm32_adc_regspec { 170 const u32 dr; 171 const struct stm32_adc_regs ier_eoc; 172 const struct stm32_adc_regs ier_ovr; 173 const struct stm32_adc_regs isr_eoc; 174 const struct stm32_adc_regs isr_ovr; 175 const struct stm32_adc_regs *sqr; 176 const struct stm32_adc_regs exten; 177 const struct stm32_adc_regs extsel; 178 const struct stm32_adc_regs res; 179 const u32 smpr[2]; 180 const struct stm32_adc_regs *smp_bits; 181 const struct stm32_adc_regs or_vdd; 182 const struct stm32_adc_regs ccr_vbat; 183 const struct stm32_adc_regs ccr_vref; 184 }; 185 186 struct stm32_adc; 187 188 /** 189 * struct stm32_adc_cfg - stm32 compatible configuration data 190 * @regs: registers descriptions 191 * @adc_info: per instance input channels definitions 192 * @trigs: external trigger sources 193 * @clk_required: clock is required 194 * @has_vregready: vregready status flag presence 195 * @prepare: optional prepare routine (power-up, enable) 196 * @start_conv: routine to start conversions 197 * @stop_conv: routine to stop conversions 198 * @unprepare: optional unprepare routine (disable, power-down) 199 * @irq_clear: routine to clear irqs 200 * @smp_cycles: programmable sampling time (ADC clock cycles) 201 * @ts_vrefint_ns: vrefint minimum sampling time in ns 202 */ 203 struct stm32_adc_cfg { 204 const struct stm32_adc_regspec *regs; 205 const struct stm32_adc_info *adc_info; 206 struct stm32_adc_trig_info *trigs; 207 bool clk_required; 208 bool has_vregready; 209 int (*prepare)(struct iio_dev *); 210 void (*start_conv)(struct iio_dev *, bool dma); 211 void (*stop_conv)(struct iio_dev *); 212 void (*unprepare)(struct iio_dev *); 213 void (*irq_clear)(struct iio_dev *indio_dev, u32 msk); 214 const unsigned int *smp_cycles; 215 const unsigned int ts_vrefint_ns; 216 }; 217 218 /** 219 * struct stm32_adc - private data of each ADC IIO instance 220 * @common: reference to ADC block common data 221 * @offset: ADC instance register offset in ADC block 222 * @cfg: compatible configuration data 223 * @completion: end of single conversion completion 224 * @buffer: data buffer + 8 bytes for timestamp if enabled 225 * @clk: clock for this adc instance 226 * @irq: interrupt for this adc instance 227 * @lock: spinlock 228 * @bufi: data buffer index 229 * @num_conv: expected number of scan conversions 230 * @res: data resolution (e.g. RES bitfield value) 231 * @trigger_polarity: external trigger polarity (e.g. exten) 232 * @dma_chan: dma channel 233 * @rx_buf: dma rx buffer cpu address 234 * @rx_dma_buf: dma rx buffer bus address 235 * @rx_buf_sz: dma rx buffer size 236 * @difsel: bitmask to set single-ended/differential channel 237 * @pcsel: bitmask to preselect channels on some devices 238 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) 239 * @cal: optional calibration data on some devices 240 * @vrefint: internal reference voltage data 241 * @chan_name: channel name array 242 * @num_diff: number of differential channels 243 * @int_ch: internal channel indexes array 244 */ 245 struct stm32_adc { 246 struct stm32_adc_common *common; 247 u32 offset; 248 const struct stm32_adc_cfg *cfg; 249 struct completion completion; 250 u16 buffer[STM32_ADC_MAX_SQ + 4] __aligned(8); 251 struct clk *clk; 252 int irq; 253 spinlock_t lock; /* interrupt lock */ 254 unsigned int bufi; 255 unsigned int num_conv; 256 u32 res; 257 u32 trigger_polarity; 258 struct dma_chan *dma_chan; 259 u8 *rx_buf; 260 dma_addr_t rx_dma_buf; 261 unsigned int rx_buf_sz; 262 u32 difsel; 263 u32 pcsel; 264 u32 smpr_val[2]; 265 struct stm32_adc_calib cal; 266 struct stm32_adc_vrefint vrefint; 267 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ]; 268 u32 num_diff; 269 int int_ch[STM32_ADC_INT_CH_NB]; 270 }; 271 272 struct stm32_adc_diff_channel { 273 u32 vinp; 274 u32 vinn; 275 }; 276 277 /** 278 * struct stm32_adc_info - stm32 ADC, per instance config data 279 * @max_channels: Number of channels 280 * @resolutions: available resolutions 281 * @num_res: number of available resolutions 282 */ 283 struct stm32_adc_info { 284 int max_channels; 285 const unsigned int *resolutions; 286 const unsigned int num_res; 287 }; 288 289 static const unsigned int stm32f4_adc_resolutions[] = { 290 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */ 291 12, 10, 8, 6, 292 }; 293 294 /* stm32f4 can have up to 16 channels */ 295 static const struct stm32_adc_info stm32f4_adc_info = { 296 .max_channels = 16, 297 .resolutions = stm32f4_adc_resolutions, 298 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 299 }; 300 301 static const unsigned int stm32h7_adc_resolutions[] = { 302 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */ 303 16, 14, 12, 10, 8, 304 }; 305 306 /* stm32h7 can have up to 20 channels */ 307 static const struct stm32_adc_info stm32h7_adc_info = { 308 .max_channels = STM32_ADC_CH_MAX, 309 .resolutions = stm32h7_adc_resolutions, 310 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), 311 }; 312 313 /* 314 * stm32f4_sq - describe regular sequence registers 315 * - L: sequence len (register & bit field) 316 * - SQ1..SQ16: sequence entries (register & bit field) 317 */ 318 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = { 319 /* L: len bit field description to be kept as first element */ 320 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 }, 321 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 322 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 }, 323 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 }, 324 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 }, 325 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 }, 326 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 }, 327 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 }, 328 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 }, 329 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 }, 330 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 }, 331 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 }, 332 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 }, 333 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 }, 334 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 }, 335 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 }, 336 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 }, 337 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 }, 338 }; 339 340 /* STM32F4 external trigger sources for all instances */ 341 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 342 { TIM1_CH1, STM32_EXT0 }, 343 { TIM1_CH2, STM32_EXT1 }, 344 { TIM1_CH3, STM32_EXT2 }, 345 { TIM2_CH2, STM32_EXT3 }, 346 { TIM2_CH3, STM32_EXT4 }, 347 { TIM2_CH4, STM32_EXT5 }, 348 { TIM2_TRGO, STM32_EXT6 }, 349 { TIM3_CH1, STM32_EXT7 }, 350 { TIM3_TRGO, STM32_EXT8 }, 351 { TIM4_CH4, STM32_EXT9 }, 352 { TIM5_CH1, STM32_EXT10 }, 353 { TIM5_CH2, STM32_EXT11 }, 354 { TIM5_CH3, STM32_EXT12 }, 355 { TIM8_CH1, STM32_EXT13 }, 356 { TIM8_TRGO, STM32_EXT14 }, 357 {}, /* sentinel */ 358 }; 359 360 /* 361 * stm32f4_smp_bits[] - describe sampling time register index & bit fields 362 * Sorted so it can be indexed by channel number. 363 */ 364 static const struct stm32_adc_regs stm32f4_smp_bits[] = { 365 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */ 366 { 1, GENMASK(2, 0), 0 }, 367 { 1, GENMASK(5, 3), 3 }, 368 { 1, GENMASK(8, 6), 6 }, 369 { 1, GENMASK(11, 9), 9 }, 370 { 1, GENMASK(14, 12), 12 }, 371 { 1, GENMASK(17, 15), 15 }, 372 { 1, GENMASK(20, 18), 18 }, 373 { 1, GENMASK(23, 21), 21 }, 374 { 1, GENMASK(26, 24), 24 }, 375 { 1, GENMASK(29, 27), 27 }, 376 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */ 377 { 0, GENMASK(2, 0), 0 }, 378 { 0, GENMASK(5, 3), 3 }, 379 { 0, GENMASK(8, 6), 6 }, 380 { 0, GENMASK(11, 9), 9 }, 381 { 0, GENMASK(14, 12), 12 }, 382 { 0, GENMASK(17, 15), 15 }, 383 { 0, GENMASK(20, 18), 18 }, 384 { 0, GENMASK(23, 21), 21 }, 385 { 0, GENMASK(26, 24), 24 }, 386 }; 387 388 /* STM32F4 programmable sampling time (ADC clock cycles) */ 389 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 390 3, 15, 28, 56, 84, 112, 144, 480, 391 }; 392 393 static const struct stm32_adc_regspec stm32f4_adc_regspec = { 394 .dr = STM32F4_ADC_DR, 395 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE }, 396 .ier_ovr = { STM32F4_ADC_CR1, STM32F4_OVRIE }, 397 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC }, 398 .isr_ovr = { STM32F4_ADC_SR, STM32F4_OVR }, 399 .sqr = stm32f4_sq, 400 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT }, 401 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK, 402 STM32F4_EXTSEL_SHIFT }, 403 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT }, 404 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 }, 405 .smp_bits = stm32f4_smp_bits, 406 }; 407 408 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = { 409 /* L: len bit field description to be kept as first element */ 410 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 }, 411 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 412 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 }, 413 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 }, 414 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 }, 415 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 }, 416 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 }, 417 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 }, 418 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 }, 419 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 }, 420 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 }, 421 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 }, 422 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 }, 423 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 }, 424 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 }, 425 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 }, 426 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 }, 427 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 }, 428 }; 429 430 /* STM32H7 external trigger sources for all instances */ 431 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 432 { TIM1_CH1, STM32_EXT0 }, 433 { TIM1_CH2, STM32_EXT1 }, 434 { TIM1_CH3, STM32_EXT2 }, 435 { TIM2_CH2, STM32_EXT3 }, 436 { TIM3_TRGO, STM32_EXT4 }, 437 { TIM4_CH4, STM32_EXT5 }, 438 { TIM8_TRGO, STM32_EXT7 }, 439 { TIM8_TRGO2, STM32_EXT8 }, 440 { TIM1_TRGO, STM32_EXT9 }, 441 { TIM1_TRGO2, STM32_EXT10 }, 442 { TIM2_TRGO, STM32_EXT11 }, 443 { TIM4_TRGO, STM32_EXT12 }, 444 { TIM6_TRGO, STM32_EXT13 }, 445 { TIM15_TRGO, STM32_EXT14 }, 446 { TIM3_CH4, STM32_EXT15 }, 447 { LPTIM1_OUT, STM32_EXT18 }, 448 { LPTIM2_OUT, STM32_EXT19 }, 449 { LPTIM3_OUT, STM32_EXT20 }, 450 {}, 451 }; 452 453 /* 454 * stm32h7_smp_bits - describe sampling time register index & bit fields 455 * Sorted so it can be indexed by channel number. 456 */ 457 static const struct stm32_adc_regs stm32h7_smp_bits[] = { 458 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */ 459 { 0, GENMASK(2, 0), 0 }, 460 { 0, GENMASK(5, 3), 3 }, 461 { 0, GENMASK(8, 6), 6 }, 462 { 0, GENMASK(11, 9), 9 }, 463 { 0, GENMASK(14, 12), 12 }, 464 { 0, GENMASK(17, 15), 15 }, 465 { 0, GENMASK(20, 18), 18 }, 466 { 0, GENMASK(23, 21), 21 }, 467 { 0, GENMASK(26, 24), 24 }, 468 { 0, GENMASK(29, 27), 27 }, 469 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */ 470 { 1, GENMASK(2, 0), 0 }, 471 { 1, GENMASK(5, 3), 3 }, 472 { 1, GENMASK(8, 6), 6 }, 473 { 1, GENMASK(11, 9), 9 }, 474 { 1, GENMASK(14, 12), 12 }, 475 { 1, GENMASK(17, 15), 15 }, 476 { 1, GENMASK(20, 18), 18 }, 477 { 1, GENMASK(23, 21), 21 }, 478 { 1, GENMASK(26, 24), 24 }, 479 { 1, GENMASK(29, 27), 27 }, 480 }; 481 482 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */ 483 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 484 1, 2, 8, 16, 32, 64, 387, 810, 485 }; 486 487 static const struct stm32_adc_regspec stm32h7_adc_regspec = { 488 .dr = STM32H7_ADC_DR, 489 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 490 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 491 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 492 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 493 .sqr = stm32h7_sq, 494 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 495 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 496 STM32H7_EXTSEL_SHIFT }, 497 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 498 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 499 .smp_bits = stm32h7_smp_bits, 500 }; 501 502 static const struct stm32_adc_regspec stm32mp1_adc_regspec = { 503 .dr = STM32H7_ADC_DR, 504 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 505 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 506 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 507 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 508 .sqr = stm32h7_sq, 509 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 510 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 511 STM32H7_EXTSEL_SHIFT }, 512 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 513 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 514 .smp_bits = stm32h7_smp_bits, 515 .or_vdd = { STM32MP1_ADC2_OR, STM32MP1_VDDCOREEN }, 516 .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, 517 .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, 518 }; 519 520 /* 521 * STM32 ADC registers access routines 522 * @adc: stm32 adc instance 523 * @reg: reg offset in adc instance 524 * 525 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. 526 * for adc1, adc2 and adc3. 527 */ 528 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) 529 { 530 return readl_relaxed(adc->common->base + adc->offset + reg); 531 } 532 533 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr) 534 535 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ 536 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ 537 cond, sleep_us, timeout_us) 538 539 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) 540 { 541 return readw_relaxed(adc->common->base + adc->offset + reg); 542 } 543 544 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) 545 { 546 writel_relaxed(val, adc->common->base + adc->offset + reg); 547 } 548 549 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) 550 { 551 unsigned long flags; 552 553 spin_lock_irqsave(&adc->lock, flags); 554 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); 555 spin_unlock_irqrestore(&adc->lock, flags); 556 } 557 558 static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) 559 { 560 spin_lock(&adc->common->lock); 561 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, 562 adc->common->base + reg); 563 spin_unlock(&adc->common->lock); 564 } 565 566 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) 567 { 568 unsigned long flags; 569 570 spin_lock_irqsave(&adc->lock, flags); 571 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); 572 spin_unlock_irqrestore(&adc->lock, flags); 573 } 574 575 static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) 576 { 577 spin_lock(&adc->common->lock); 578 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, 579 adc->common->base + reg); 580 spin_unlock(&adc->common->lock); 581 } 582 583 /** 584 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt 585 * @adc: stm32 adc instance 586 */ 587 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) 588 { 589 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, 590 adc->cfg->regs->ier_eoc.mask); 591 }; 592 593 /** 594 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt 595 * @adc: stm32 adc instance 596 */ 597 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) 598 { 599 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, 600 adc->cfg->regs->ier_eoc.mask); 601 } 602 603 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) 604 { 605 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, 606 adc->cfg->regs->ier_ovr.mask); 607 } 608 609 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) 610 { 611 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, 612 adc->cfg->regs->ier_ovr.mask); 613 } 614 615 static void stm32_adc_set_res(struct stm32_adc *adc) 616 { 617 const struct stm32_adc_regs *res = &adc->cfg->regs->res; 618 u32 val; 619 620 val = stm32_adc_readl(adc, res->reg); 621 val = (val & ~res->mask) | (adc->res << res->shift); 622 stm32_adc_writel(adc, res->reg, val); 623 } 624 625 static int stm32_adc_hw_stop(struct device *dev) 626 { 627 struct iio_dev *indio_dev = dev_get_drvdata(dev); 628 struct stm32_adc *adc = iio_priv(indio_dev); 629 630 if (adc->cfg->unprepare) 631 adc->cfg->unprepare(indio_dev); 632 633 clk_disable_unprepare(adc->clk); 634 635 return 0; 636 } 637 638 static int stm32_adc_hw_start(struct device *dev) 639 { 640 struct iio_dev *indio_dev = dev_get_drvdata(dev); 641 struct stm32_adc *adc = iio_priv(indio_dev); 642 int ret; 643 644 ret = clk_prepare_enable(adc->clk); 645 if (ret) 646 return ret; 647 648 stm32_adc_set_res(adc); 649 650 if (adc->cfg->prepare) { 651 ret = adc->cfg->prepare(indio_dev); 652 if (ret) 653 goto err_clk_dis; 654 } 655 656 return 0; 657 658 err_clk_dis: 659 clk_disable_unprepare(adc->clk); 660 661 return ret; 662 } 663 664 static void stm32_adc_int_ch_enable(struct iio_dev *indio_dev) 665 { 666 struct stm32_adc *adc = iio_priv(indio_dev); 667 u32 i; 668 669 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 670 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) 671 continue; 672 673 switch (i) { 674 case STM32_ADC_INT_CH_VDDCORE: 675 dev_dbg(&indio_dev->dev, "Enable VDDCore\n"); 676 stm32_adc_set_bits(adc, adc->cfg->regs->or_vdd.reg, 677 adc->cfg->regs->or_vdd.mask); 678 break; 679 case STM32_ADC_INT_CH_VREFINT: 680 dev_dbg(&indio_dev->dev, "Enable VREFInt\n"); 681 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, 682 adc->cfg->regs->ccr_vref.mask); 683 break; 684 case STM32_ADC_INT_CH_VBAT: 685 dev_dbg(&indio_dev->dev, "Enable VBAT\n"); 686 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, 687 adc->cfg->regs->ccr_vbat.mask); 688 break; 689 } 690 } 691 } 692 693 static void stm32_adc_int_ch_disable(struct stm32_adc *adc) 694 { 695 u32 i; 696 697 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 698 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) 699 continue; 700 701 switch (i) { 702 case STM32_ADC_INT_CH_VDDCORE: 703 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vdd.reg, 704 adc->cfg->regs->or_vdd.mask); 705 break; 706 case STM32_ADC_INT_CH_VREFINT: 707 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, 708 adc->cfg->regs->ccr_vref.mask); 709 break; 710 case STM32_ADC_INT_CH_VBAT: 711 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, 712 adc->cfg->regs->ccr_vbat.mask); 713 break; 714 } 715 } 716 } 717 718 /** 719 * stm32f4_adc_start_conv() - Start conversions for regular channels. 720 * @indio_dev: IIO device instance 721 * @dma: use dma to transfer conversion result 722 * 723 * Start conversions for regular channels. 724 * Also take care of normal or DMA mode. Circular DMA may be used for regular 725 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct 726 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). 727 */ 728 static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma) 729 { 730 struct stm32_adc *adc = iio_priv(indio_dev); 731 732 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 733 734 if (dma) 735 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, 736 STM32F4_DMA | STM32F4_DDS); 737 738 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); 739 740 /* Wait for Power-up time (tSTAB from datasheet) */ 741 usleep_range(2, 3); 742 743 /* Software start ? (e.g. trigger detection disabled ?) */ 744 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) 745 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); 746 } 747 748 static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev) 749 { 750 struct stm32_adc *adc = iio_priv(indio_dev); 751 752 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 753 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); 754 755 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 756 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, 757 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); 758 } 759 760 static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 761 { 762 struct stm32_adc *adc = iio_priv(indio_dev); 763 764 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 765 } 766 767 static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma) 768 { 769 struct stm32_adc *adc = iio_priv(indio_dev); 770 enum stm32h7_adc_dmngt dmngt; 771 unsigned long flags; 772 u32 val; 773 774 if (dma) 775 dmngt = STM32H7_DMNGT_DMA_CIRC; 776 else 777 dmngt = STM32H7_DMNGT_DR_ONLY; 778 779 spin_lock_irqsave(&adc->lock, flags); 780 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); 781 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); 782 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); 783 spin_unlock_irqrestore(&adc->lock, flags); 784 785 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 786 } 787 788 static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev) 789 { 790 struct stm32_adc *adc = iio_priv(indio_dev); 791 int ret; 792 u32 val; 793 794 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); 795 796 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 797 !(val & (STM32H7_ADSTART)), 798 100, STM32_ADC_TIMEOUT_US); 799 if (ret) 800 dev_warn(&indio_dev->dev, "stop failed\n"); 801 802 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); 803 } 804 805 static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 806 { 807 struct stm32_adc *adc = iio_priv(indio_dev); 808 /* On STM32H7 IRQs are cleared by writing 1 into ISR register */ 809 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 810 } 811 812 static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev) 813 { 814 struct stm32_adc *adc = iio_priv(indio_dev); 815 int ret; 816 u32 val; 817 818 /* Exit deep power down, then enable ADC voltage regulator */ 819 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 820 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); 821 822 if (adc->common->rate > STM32H7_BOOST_CLKRATE) 823 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 824 825 /* Wait for startup time */ 826 if (!adc->cfg->has_vregready) { 827 usleep_range(10, 20); 828 return 0; 829 } 830 831 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 832 val & STM32MP1_VREGREADY, 100, 833 STM32_ADC_TIMEOUT_US); 834 if (ret) { 835 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 836 dev_err(&indio_dev->dev, "Failed to exit power down\n"); 837 } 838 839 return ret; 840 } 841 842 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) 843 { 844 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 845 846 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ 847 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 848 } 849 850 static int stm32h7_adc_enable(struct iio_dev *indio_dev) 851 { 852 struct stm32_adc *adc = iio_priv(indio_dev); 853 int ret; 854 u32 val; 855 856 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); 857 858 /* Poll for ADRDY to be set (after adc startup time) */ 859 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 860 val & STM32H7_ADRDY, 861 100, STM32_ADC_TIMEOUT_US); 862 if (ret) { 863 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 864 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); 865 } else { 866 /* Clear ADRDY by writing one */ 867 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); 868 } 869 870 return ret; 871 } 872 873 static void stm32h7_adc_disable(struct iio_dev *indio_dev) 874 { 875 struct stm32_adc *adc = iio_priv(indio_dev); 876 int ret; 877 u32 val; 878 879 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) 880 return; 881 882 /* Disable ADC and wait until it's effectively disabled */ 883 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 884 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 885 !(val & STM32H7_ADEN), 100, 886 STM32_ADC_TIMEOUT_US); 887 if (ret) 888 dev_warn(&indio_dev->dev, "Failed to disable\n"); 889 } 890 891 /** 892 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result 893 * @indio_dev: IIO device instance 894 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable 895 */ 896 static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev) 897 { 898 struct stm32_adc *adc = iio_priv(indio_dev); 899 int i, ret; 900 u32 lincalrdyw_mask, val; 901 902 /* Read linearity calibration */ 903 lincalrdyw_mask = STM32H7_LINCALRDYW6; 904 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 905 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */ 906 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 907 908 /* Poll: wait calib data to be ready in CALFACT2 register */ 909 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 910 !(val & lincalrdyw_mask), 911 100, STM32_ADC_TIMEOUT_US); 912 if (ret) { 913 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 914 return ret; 915 } 916 917 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 918 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); 919 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; 920 921 lincalrdyw_mask >>= 1; 922 } 923 924 /* Read offset calibration */ 925 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); 926 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); 927 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; 928 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); 929 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; 930 adc->cal.calibrated = true; 931 932 return 0; 933 } 934 935 /** 936 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result 937 * @indio_dev: IIO device instance 938 * Note: ADC must be enabled, with no on-going conversions. 939 */ 940 static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev) 941 { 942 struct stm32_adc *adc = iio_priv(indio_dev); 943 int i, ret; 944 u32 lincalrdyw_mask, val; 945 946 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | 947 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); 948 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); 949 950 lincalrdyw_mask = STM32H7_LINCALRDYW6; 951 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 952 /* 953 * Write saved calibration data to shadow registers: 954 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger 955 * data write. Then poll to wait for complete transfer. 956 */ 957 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; 958 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); 959 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 960 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 961 val & lincalrdyw_mask, 962 100, STM32_ADC_TIMEOUT_US); 963 if (ret) { 964 dev_err(&indio_dev->dev, "Failed to write calfact\n"); 965 return ret; 966 } 967 968 /* 969 * Read back calibration data, has two effects: 970 * - It ensures bits LINCALRDYW[6..1] are kept cleared 971 * for next time calibration needs to be restored. 972 * - BTW, bit clear triggers a read, then check data has been 973 * correctly written. 974 */ 975 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 976 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 977 !(val & lincalrdyw_mask), 978 100, STM32_ADC_TIMEOUT_US); 979 if (ret) { 980 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 981 return ret; 982 } 983 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 984 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { 985 dev_err(&indio_dev->dev, "calfact not consistent\n"); 986 return -EIO; 987 } 988 989 lincalrdyw_mask >>= 1; 990 } 991 992 return 0; 993 } 994 995 /* 996 * Fixed timeout value for ADC calibration. 997 * worst cases: 998 * - low clock frequency 999 * - maximum prescalers 1000 * Calibration requires: 1001 * - 131,072 ADC clock cycle for the linear calibration 1002 * - 20 ADC clock cycle for the offset calibration 1003 * 1004 * Set to 100ms for now 1005 */ 1006 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000 1007 1008 /** 1009 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC 1010 * @indio_dev: IIO device instance 1011 * Note: Must be called once ADC is out of power down. 1012 */ 1013 static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev) 1014 { 1015 struct stm32_adc *adc = iio_priv(indio_dev); 1016 int ret; 1017 u32 val; 1018 1019 if (adc->cal.calibrated) 1020 return true; 1021 1022 /* ADC must be disabled for calibration */ 1023 stm32h7_adc_disable(indio_dev); 1024 1025 /* 1026 * Select calibration mode: 1027 * - Offset calibration for single ended inputs 1028 * - No linearity calibration (do it later, before reading it) 1029 */ 1030 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); 1031 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); 1032 1033 /* Start calibration, then wait for completion */ 1034 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1035 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1036 !(val & STM32H7_ADCAL), 100, 1037 STM32H7_ADC_CALIB_TIMEOUT_US); 1038 if (ret) { 1039 dev_err(&indio_dev->dev, "calibration failed\n"); 1040 goto out; 1041 } 1042 1043 /* 1044 * Select calibration mode, then start calibration: 1045 * - Offset calibration for differential input 1046 * - Linearity calibration (needs to be done only once for single/diff) 1047 * will run simultaneously with offset calibration. 1048 */ 1049 stm32_adc_set_bits(adc, STM32H7_ADC_CR, 1050 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 1051 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1052 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1053 !(val & STM32H7_ADCAL), 100, 1054 STM32H7_ADC_CALIB_TIMEOUT_US); 1055 if (ret) { 1056 dev_err(&indio_dev->dev, "calibration failed\n"); 1057 goto out; 1058 } 1059 1060 out: 1061 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, 1062 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 1063 1064 return ret; 1065 } 1066 1067 /** 1068 * stm32h7_adc_prepare() - Leave power down mode to enable ADC. 1069 * @indio_dev: IIO device instance 1070 * Leave power down mode. 1071 * Configure channels as single ended or differential before enabling ADC. 1072 * Enable ADC. 1073 * Restore calibration data. 1074 * Pre-select channels that may be used in PCSEL (required by input MUX / IO): 1075 * - Only one input is selected for single ended (e.g. 'vinp') 1076 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn') 1077 */ 1078 static int stm32h7_adc_prepare(struct iio_dev *indio_dev) 1079 { 1080 struct stm32_adc *adc = iio_priv(indio_dev); 1081 int calib, ret; 1082 1083 ret = stm32h7_adc_exit_pwr_down(indio_dev); 1084 if (ret) 1085 return ret; 1086 1087 ret = stm32h7_adc_selfcalib(indio_dev); 1088 if (ret < 0) 1089 goto pwr_dwn; 1090 calib = ret; 1091 1092 stm32_adc_int_ch_enable(indio_dev); 1093 1094 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); 1095 1096 ret = stm32h7_adc_enable(indio_dev); 1097 if (ret) 1098 goto ch_disable; 1099 1100 /* Either restore or read calibration result for future reference */ 1101 if (calib) 1102 ret = stm32h7_adc_restore_selfcalib(indio_dev); 1103 else 1104 ret = stm32h7_adc_read_selfcalib(indio_dev); 1105 if (ret) 1106 goto disable; 1107 1108 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 1109 1110 return 0; 1111 1112 disable: 1113 stm32h7_adc_disable(indio_dev); 1114 ch_disable: 1115 stm32_adc_int_ch_disable(adc); 1116 pwr_dwn: 1117 stm32h7_adc_enter_pwr_down(adc); 1118 1119 return ret; 1120 } 1121 1122 static void stm32h7_adc_unprepare(struct iio_dev *indio_dev) 1123 { 1124 struct stm32_adc *adc = iio_priv(indio_dev); 1125 1126 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); 1127 stm32h7_adc_disable(indio_dev); 1128 stm32_adc_int_ch_disable(adc); 1129 stm32h7_adc_enter_pwr_down(adc); 1130 } 1131 1132 /** 1133 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence 1134 * @indio_dev: IIO device 1135 * @scan_mask: channels to be converted 1136 * 1137 * Conversion sequence : 1138 * Apply sampling time settings for all channels. 1139 * Configure ADC scan sequence based on selected channels in scan_mask. 1140 * Add channels to SQR registers, from scan_mask LSB to MSB, then 1141 * program sequence len. 1142 */ 1143 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, 1144 const unsigned long *scan_mask) 1145 { 1146 struct stm32_adc *adc = iio_priv(indio_dev); 1147 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; 1148 const struct iio_chan_spec *chan; 1149 u32 val, bit; 1150 int i = 0; 1151 1152 /* Apply sampling time settings */ 1153 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); 1154 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); 1155 1156 for_each_set_bit(bit, scan_mask, indio_dev->masklength) { 1157 chan = indio_dev->channels + bit; 1158 /* 1159 * Assign one channel per SQ entry in regular 1160 * sequence, starting with SQ1. 1161 */ 1162 i++; 1163 if (i > STM32_ADC_MAX_SQ) 1164 return -EINVAL; 1165 1166 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", 1167 __func__, chan->channel, i); 1168 1169 val = stm32_adc_readl(adc, sqr[i].reg); 1170 val &= ~sqr[i].mask; 1171 val |= chan->channel << sqr[i].shift; 1172 stm32_adc_writel(adc, sqr[i].reg, val); 1173 } 1174 1175 if (!i) 1176 return -EINVAL; 1177 1178 /* Sequence len */ 1179 val = stm32_adc_readl(adc, sqr[0].reg); 1180 val &= ~sqr[0].mask; 1181 val |= ((i - 1) << sqr[0].shift); 1182 stm32_adc_writel(adc, sqr[0].reg, val); 1183 1184 return 0; 1185 } 1186 1187 /** 1188 * stm32_adc_get_trig_extsel() - Get external trigger selection 1189 * @indio_dev: IIO device structure 1190 * @trig: trigger 1191 * 1192 * Returns trigger extsel value, if trig matches, -EINVAL otherwise. 1193 */ 1194 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, 1195 struct iio_trigger *trig) 1196 { 1197 struct stm32_adc *adc = iio_priv(indio_dev); 1198 int i; 1199 1200 /* lookup triggers registered by stm32 timer trigger driver */ 1201 for (i = 0; adc->cfg->trigs[i].name; i++) { 1202 /** 1203 * Checking both stm32 timer trigger type and trig name 1204 * should be safe against arbitrary trigger names. 1205 */ 1206 if ((is_stm32_timer_trigger(trig) || 1207 is_stm32_lptim_trigger(trig)) && 1208 !strcmp(adc->cfg->trigs[i].name, trig->name)) { 1209 return adc->cfg->trigs[i].extsel; 1210 } 1211 } 1212 1213 return -EINVAL; 1214 } 1215 1216 /** 1217 * stm32_adc_set_trig() - Set a regular trigger 1218 * @indio_dev: IIO device 1219 * @trig: IIO trigger 1220 * 1221 * Set trigger source/polarity (e.g. SW, or HW with polarity) : 1222 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) 1223 * - if HW trigger enabled, set source & polarity 1224 */ 1225 static int stm32_adc_set_trig(struct iio_dev *indio_dev, 1226 struct iio_trigger *trig) 1227 { 1228 struct stm32_adc *adc = iio_priv(indio_dev); 1229 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; 1230 unsigned long flags; 1231 int ret; 1232 1233 if (trig) { 1234 ret = stm32_adc_get_trig_extsel(indio_dev, trig); 1235 if (ret < 0) 1236 return ret; 1237 1238 /* set trigger source and polarity (default to rising edge) */ 1239 extsel = ret; 1240 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; 1241 } 1242 1243 spin_lock_irqsave(&adc->lock, flags); 1244 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); 1245 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); 1246 val |= exten << adc->cfg->regs->exten.shift; 1247 val |= extsel << adc->cfg->regs->extsel.shift; 1248 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); 1249 spin_unlock_irqrestore(&adc->lock, flags); 1250 1251 return 0; 1252 } 1253 1254 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, 1255 const struct iio_chan_spec *chan, 1256 unsigned int type) 1257 { 1258 struct stm32_adc *adc = iio_priv(indio_dev); 1259 1260 adc->trigger_polarity = type; 1261 1262 return 0; 1263 } 1264 1265 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, 1266 const struct iio_chan_spec *chan) 1267 { 1268 struct stm32_adc *adc = iio_priv(indio_dev); 1269 1270 return adc->trigger_polarity; 1271 } 1272 1273 static const char * const stm32_trig_pol_items[] = { 1274 "rising-edge", "falling-edge", "both-edges", 1275 }; 1276 1277 static const struct iio_enum stm32_adc_trig_pol = { 1278 .items = stm32_trig_pol_items, 1279 .num_items = ARRAY_SIZE(stm32_trig_pol_items), 1280 .get = stm32_adc_get_trig_pol, 1281 .set = stm32_adc_set_trig_pol, 1282 }; 1283 1284 /** 1285 * stm32_adc_single_conv() - Performs a single conversion 1286 * @indio_dev: IIO device 1287 * @chan: IIO channel 1288 * @res: conversion result 1289 * 1290 * The function performs a single conversion on a given channel: 1291 * - Apply sampling time settings 1292 * - Program sequencer with one channel (e.g. in SQ1 with len = 1) 1293 * - Use SW trigger 1294 * - Start conversion, then wait for interrupt completion. 1295 */ 1296 static int stm32_adc_single_conv(struct iio_dev *indio_dev, 1297 const struct iio_chan_spec *chan, 1298 int *res) 1299 { 1300 struct stm32_adc *adc = iio_priv(indio_dev); 1301 struct device *dev = indio_dev->dev.parent; 1302 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1303 long timeout; 1304 u32 val; 1305 int ret; 1306 1307 reinit_completion(&adc->completion); 1308 1309 adc->bufi = 0; 1310 1311 ret = pm_runtime_resume_and_get(dev); 1312 if (ret < 0) 1313 return ret; 1314 1315 /* Apply sampling time settings */ 1316 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); 1317 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); 1318 1319 /* Program chan number in regular sequence (SQ1) */ 1320 val = stm32_adc_readl(adc, regs->sqr[1].reg); 1321 val &= ~regs->sqr[1].mask; 1322 val |= chan->channel << regs->sqr[1].shift; 1323 stm32_adc_writel(adc, regs->sqr[1].reg, val); 1324 1325 /* Set regular sequence len (0 for 1 conversion) */ 1326 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); 1327 1328 /* Trigger detection disabled (conversion can be launched in SW) */ 1329 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); 1330 1331 stm32_adc_conv_irq_enable(adc); 1332 1333 adc->cfg->start_conv(indio_dev, false); 1334 1335 timeout = wait_for_completion_interruptible_timeout( 1336 &adc->completion, STM32_ADC_TIMEOUT); 1337 if (timeout == 0) { 1338 ret = -ETIMEDOUT; 1339 } else if (timeout < 0) { 1340 ret = timeout; 1341 } else { 1342 *res = adc->buffer[0]; 1343 ret = IIO_VAL_INT; 1344 } 1345 1346 adc->cfg->stop_conv(indio_dev); 1347 1348 stm32_adc_conv_irq_disable(adc); 1349 1350 pm_runtime_mark_last_busy(dev); 1351 pm_runtime_put_autosuspend(dev); 1352 1353 return ret; 1354 } 1355 1356 static int stm32_adc_read_raw(struct iio_dev *indio_dev, 1357 struct iio_chan_spec const *chan, 1358 int *val, int *val2, long mask) 1359 { 1360 struct stm32_adc *adc = iio_priv(indio_dev); 1361 int ret; 1362 1363 switch (mask) { 1364 case IIO_CHAN_INFO_RAW: 1365 case IIO_CHAN_INFO_PROCESSED: 1366 ret = iio_device_claim_direct_mode(indio_dev); 1367 if (ret) 1368 return ret; 1369 if (chan->type == IIO_VOLTAGE) 1370 ret = stm32_adc_single_conv(indio_dev, chan, val); 1371 else 1372 ret = -EINVAL; 1373 1374 if (mask == IIO_CHAN_INFO_PROCESSED) 1375 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; 1376 1377 iio_device_release_direct_mode(indio_dev); 1378 return ret; 1379 1380 case IIO_CHAN_INFO_SCALE: 1381 if (chan->differential) { 1382 *val = adc->common->vref_mv * 2; 1383 *val2 = chan->scan_type.realbits; 1384 } else { 1385 *val = adc->common->vref_mv; 1386 *val2 = chan->scan_type.realbits; 1387 } 1388 return IIO_VAL_FRACTIONAL_LOG2; 1389 1390 case IIO_CHAN_INFO_OFFSET: 1391 if (chan->differential) 1392 /* ADC_full_scale / 2 */ 1393 *val = -((1 << chan->scan_type.realbits) / 2); 1394 else 1395 *val = 0; 1396 return IIO_VAL_INT; 1397 1398 default: 1399 return -EINVAL; 1400 } 1401 } 1402 1403 static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 1404 { 1405 struct stm32_adc *adc = iio_priv(indio_dev); 1406 1407 adc->cfg->irq_clear(indio_dev, msk); 1408 } 1409 1410 static irqreturn_t stm32_adc_threaded_isr(int irq, void *data) 1411 { 1412 struct iio_dev *indio_dev = data; 1413 struct stm32_adc *adc = iio_priv(indio_dev); 1414 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1415 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1416 1417 /* Check ovr status right now, as ovr mask should be already disabled */ 1418 if (status & regs->isr_ovr.mask) { 1419 /* 1420 * Clear ovr bit to avoid subsequent calls to IRQ handler. 1421 * This requires to stop ADC first. OVR bit state in ISR, 1422 * is propaged to CSR register by hardware. 1423 */ 1424 adc->cfg->stop_conv(indio_dev); 1425 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask); 1426 dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n"); 1427 return IRQ_HANDLED; 1428 } 1429 1430 return IRQ_NONE; 1431 } 1432 1433 static irqreturn_t stm32_adc_isr(int irq, void *data) 1434 { 1435 struct iio_dev *indio_dev = data; 1436 struct stm32_adc *adc = iio_priv(indio_dev); 1437 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1438 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1439 1440 if (status & regs->isr_ovr.mask) { 1441 /* 1442 * Overrun occurred on regular conversions: data for wrong 1443 * channel may be read. Unconditionally disable interrupts 1444 * to stop processing data and print error message. 1445 * Restarting the capture can be done by disabling, then 1446 * re-enabling it (e.g. write 0, then 1 to buffer/enable). 1447 */ 1448 stm32_adc_ovr_irq_disable(adc); 1449 stm32_adc_conv_irq_disable(adc); 1450 return IRQ_WAKE_THREAD; 1451 } 1452 1453 if (status & regs->isr_eoc.mask) { 1454 /* Reading DR also clears EOC status flag */ 1455 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); 1456 if (iio_buffer_enabled(indio_dev)) { 1457 adc->bufi++; 1458 if (adc->bufi >= adc->num_conv) { 1459 stm32_adc_conv_irq_disable(adc); 1460 iio_trigger_poll(indio_dev->trig); 1461 } 1462 } else { 1463 complete(&adc->completion); 1464 } 1465 return IRQ_HANDLED; 1466 } 1467 1468 return IRQ_NONE; 1469 } 1470 1471 /** 1472 * stm32_adc_validate_trigger() - validate trigger for stm32 adc 1473 * @indio_dev: IIO device 1474 * @trig: new trigger 1475 * 1476 * Returns: 0 if trig matches one of the triggers registered by stm32 adc 1477 * driver, -EINVAL otherwise. 1478 */ 1479 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, 1480 struct iio_trigger *trig) 1481 { 1482 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; 1483 } 1484 1485 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1486 { 1487 struct stm32_adc *adc = iio_priv(indio_dev); 1488 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2; 1489 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE; 1490 1491 /* 1492 * dma cyclic transfers are used, buffer is split into two periods. 1493 * There should be : 1494 * - always one buffer (period) dma is working on 1495 * - one buffer (period) driver can push data. 1496 */ 1497 watermark = min(watermark, val * (unsigned)(sizeof(u16))); 1498 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); 1499 1500 return 0; 1501 } 1502 1503 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, 1504 const unsigned long *scan_mask) 1505 { 1506 struct stm32_adc *adc = iio_priv(indio_dev); 1507 struct device *dev = indio_dev->dev.parent; 1508 int ret; 1509 1510 ret = pm_runtime_resume_and_get(dev); 1511 if (ret < 0) 1512 return ret; 1513 1514 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); 1515 1516 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask); 1517 pm_runtime_mark_last_busy(dev); 1518 pm_runtime_put_autosuspend(dev); 1519 1520 return ret; 1521 } 1522 1523 static int stm32_adc_of_xlate(struct iio_dev *indio_dev, 1524 const struct of_phandle_args *iiospec) 1525 { 1526 int i; 1527 1528 for (i = 0; i < indio_dev->num_channels; i++) 1529 if (indio_dev->channels[i].channel == iiospec->args[0]) 1530 return i; 1531 1532 return -EINVAL; 1533 } 1534 1535 /** 1536 * stm32_adc_debugfs_reg_access - read or write register value 1537 * @indio_dev: IIO device structure 1538 * @reg: register offset 1539 * @writeval: value to write 1540 * @readval: value to read 1541 * 1542 * To read a value from an ADC register: 1543 * echo [ADC reg offset] > direct_reg_access 1544 * cat direct_reg_access 1545 * 1546 * To write a value in a ADC register: 1547 * echo [ADC_reg_offset] [value] > direct_reg_access 1548 */ 1549 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, 1550 unsigned reg, unsigned writeval, 1551 unsigned *readval) 1552 { 1553 struct stm32_adc *adc = iio_priv(indio_dev); 1554 struct device *dev = indio_dev->dev.parent; 1555 int ret; 1556 1557 ret = pm_runtime_resume_and_get(dev); 1558 if (ret < 0) 1559 return ret; 1560 1561 if (!readval) 1562 stm32_adc_writel(adc, reg, writeval); 1563 else 1564 *readval = stm32_adc_readl(adc, reg); 1565 1566 pm_runtime_mark_last_busy(dev); 1567 pm_runtime_put_autosuspend(dev); 1568 1569 return 0; 1570 } 1571 1572 static const struct iio_info stm32_adc_iio_info = { 1573 .read_raw = stm32_adc_read_raw, 1574 .validate_trigger = stm32_adc_validate_trigger, 1575 .hwfifo_set_watermark = stm32_adc_set_watermark, 1576 .update_scan_mode = stm32_adc_update_scan_mode, 1577 .debugfs_reg_access = stm32_adc_debugfs_reg_access, 1578 .of_xlate = stm32_adc_of_xlate, 1579 }; 1580 1581 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) 1582 { 1583 struct dma_tx_state state; 1584 enum dma_status status; 1585 1586 status = dmaengine_tx_status(adc->dma_chan, 1587 adc->dma_chan->cookie, 1588 &state); 1589 if (status == DMA_IN_PROGRESS) { 1590 /* Residue is size in bytes from end of buffer */ 1591 unsigned int i = adc->rx_buf_sz - state.residue; 1592 unsigned int size; 1593 1594 /* Return available bytes */ 1595 if (i >= adc->bufi) 1596 size = i - adc->bufi; 1597 else 1598 size = adc->rx_buf_sz + i - adc->bufi; 1599 1600 return size; 1601 } 1602 1603 return 0; 1604 } 1605 1606 static void stm32_adc_dma_buffer_done(void *data) 1607 { 1608 struct iio_dev *indio_dev = data; 1609 struct stm32_adc *adc = iio_priv(indio_dev); 1610 int residue = stm32_adc_dma_residue(adc); 1611 1612 /* 1613 * In DMA mode the trigger services of IIO are not used 1614 * (e.g. no call to iio_trigger_poll). 1615 * Calling irq handler associated to the hardware trigger is not 1616 * relevant as the conversions have already been done. Data 1617 * transfers are performed directly in DMA callback instead. 1618 * This implementation avoids to call trigger irq handler that 1619 * may sleep, in an atomic context (DMA irq handler context). 1620 */ 1621 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1622 1623 while (residue >= indio_dev->scan_bytes) { 1624 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1625 1626 iio_push_to_buffers(indio_dev, buffer); 1627 1628 residue -= indio_dev->scan_bytes; 1629 adc->bufi += indio_dev->scan_bytes; 1630 if (adc->bufi >= adc->rx_buf_sz) 1631 adc->bufi = 0; 1632 } 1633 } 1634 1635 static int stm32_adc_dma_start(struct iio_dev *indio_dev) 1636 { 1637 struct stm32_adc *adc = iio_priv(indio_dev); 1638 struct dma_async_tx_descriptor *desc; 1639 dma_cookie_t cookie; 1640 int ret; 1641 1642 if (!adc->dma_chan) 1643 return 0; 1644 1645 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 1646 adc->rx_buf_sz, adc->rx_buf_sz / 2); 1647 1648 /* Prepare a DMA cyclic transaction */ 1649 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 1650 adc->rx_dma_buf, 1651 adc->rx_buf_sz, adc->rx_buf_sz / 2, 1652 DMA_DEV_TO_MEM, 1653 DMA_PREP_INTERRUPT); 1654 if (!desc) 1655 return -EBUSY; 1656 1657 desc->callback = stm32_adc_dma_buffer_done; 1658 desc->callback_param = indio_dev; 1659 1660 cookie = dmaengine_submit(desc); 1661 ret = dma_submit_error(cookie); 1662 if (ret) { 1663 dmaengine_terminate_sync(adc->dma_chan); 1664 return ret; 1665 } 1666 1667 /* Issue pending DMA requests */ 1668 dma_async_issue_pending(adc->dma_chan); 1669 1670 return 0; 1671 } 1672 1673 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) 1674 { 1675 struct stm32_adc *adc = iio_priv(indio_dev); 1676 struct device *dev = indio_dev->dev.parent; 1677 int ret; 1678 1679 ret = pm_runtime_resume_and_get(dev); 1680 if (ret < 0) 1681 return ret; 1682 1683 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); 1684 if (ret) { 1685 dev_err(&indio_dev->dev, "Can't set trigger\n"); 1686 goto err_pm_put; 1687 } 1688 1689 ret = stm32_adc_dma_start(indio_dev); 1690 if (ret) { 1691 dev_err(&indio_dev->dev, "Can't start dma\n"); 1692 goto err_clr_trig; 1693 } 1694 1695 /* Reset adc buffer index */ 1696 adc->bufi = 0; 1697 1698 stm32_adc_ovr_irq_enable(adc); 1699 1700 if (!adc->dma_chan) 1701 stm32_adc_conv_irq_enable(adc); 1702 1703 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); 1704 1705 return 0; 1706 1707 err_clr_trig: 1708 stm32_adc_set_trig(indio_dev, NULL); 1709 err_pm_put: 1710 pm_runtime_mark_last_busy(dev); 1711 pm_runtime_put_autosuspend(dev); 1712 1713 return ret; 1714 } 1715 1716 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) 1717 { 1718 struct stm32_adc *adc = iio_priv(indio_dev); 1719 struct device *dev = indio_dev->dev.parent; 1720 1721 adc->cfg->stop_conv(indio_dev); 1722 if (!adc->dma_chan) 1723 stm32_adc_conv_irq_disable(adc); 1724 1725 stm32_adc_ovr_irq_disable(adc); 1726 1727 if (adc->dma_chan) 1728 dmaengine_terminate_sync(adc->dma_chan); 1729 1730 if (stm32_adc_set_trig(indio_dev, NULL)) 1731 dev_err(&indio_dev->dev, "Can't clear trigger\n"); 1732 1733 pm_runtime_mark_last_busy(dev); 1734 pm_runtime_put_autosuspend(dev); 1735 1736 return 0; 1737 } 1738 1739 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = { 1740 .postenable = &stm32_adc_buffer_postenable, 1741 .predisable = &stm32_adc_buffer_predisable, 1742 }; 1743 1744 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) 1745 { 1746 struct iio_poll_func *pf = p; 1747 struct iio_dev *indio_dev = pf->indio_dev; 1748 struct stm32_adc *adc = iio_priv(indio_dev); 1749 1750 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1751 1752 /* reset buffer index */ 1753 adc->bufi = 0; 1754 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, 1755 pf->timestamp); 1756 iio_trigger_notify_done(indio_dev->trig); 1757 1758 /* re-enable eoc irq */ 1759 stm32_adc_conv_irq_enable(adc); 1760 1761 return IRQ_HANDLED; 1762 } 1763 1764 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = { 1765 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), 1766 { 1767 .name = "trigger_polarity_available", 1768 .shared = IIO_SHARED_BY_ALL, 1769 .read = iio_enum_available_read, 1770 .private = (uintptr_t)&stm32_adc_trig_pol, 1771 }, 1772 {}, 1773 }; 1774 1775 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev) 1776 { 1777 struct device_node *node = indio_dev->dev.of_node; 1778 struct stm32_adc *adc = iio_priv(indio_dev); 1779 unsigned int i; 1780 u32 res; 1781 1782 if (of_property_read_u32(node, "assigned-resolution-bits", &res)) 1783 res = adc->cfg->adc_info->resolutions[0]; 1784 1785 for (i = 0; i < adc->cfg->adc_info->num_res; i++) 1786 if (res == adc->cfg->adc_info->resolutions[i]) 1787 break; 1788 if (i >= adc->cfg->adc_info->num_res) { 1789 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); 1790 return -EINVAL; 1791 } 1792 1793 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); 1794 adc->res = i; 1795 1796 return 0; 1797 } 1798 1799 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) 1800 { 1801 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; 1802 u32 period_ns, shift = smpr->shift, mask = smpr->mask; 1803 unsigned int smp, r = smpr->reg; 1804 1805 /* 1806 * For vrefint channel, ensure that the sampling time cannot 1807 * be lower than the one specified in the datasheet 1808 */ 1809 if (channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) 1810 smp_ns = max(smp_ns, adc->cfg->ts_vrefint_ns); 1811 1812 /* Determine sampling time (ADC clock cycles) */ 1813 period_ns = NSEC_PER_SEC / adc->common->rate; 1814 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++) 1815 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) 1816 break; 1817 if (smp > STM32_ADC_MAX_SMP) 1818 smp = STM32_ADC_MAX_SMP; 1819 1820 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ 1821 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); 1822 } 1823 1824 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, 1825 struct iio_chan_spec *chan, u32 vinp, 1826 u32 vinn, int scan_index, bool differential) 1827 { 1828 struct stm32_adc *adc = iio_priv(indio_dev); 1829 char *name = adc->chan_name[vinp]; 1830 1831 chan->type = IIO_VOLTAGE; 1832 chan->channel = vinp; 1833 if (differential) { 1834 chan->differential = 1; 1835 chan->channel2 = vinn; 1836 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); 1837 } else { 1838 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp); 1839 } 1840 chan->datasheet_name = name; 1841 chan->scan_index = scan_index; 1842 chan->indexed = 1; 1843 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) 1844 chan->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); 1845 else 1846 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 1847 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 1848 BIT(IIO_CHAN_INFO_OFFSET); 1849 chan->scan_type.sign = 'u'; 1850 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; 1851 chan->scan_type.storagebits = 16; 1852 chan->ext_info = stm32_adc_ext_info; 1853 1854 /* pre-build selected channels mask */ 1855 adc->pcsel |= BIT(chan->channel); 1856 if (differential) { 1857 /* pre-build diff channels mask */ 1858 adc->difsel |= BIT(chan->channel); 1859 /* Also add negative input to pre-selected channels */ 1860 adc->pcsel |= BIT(chan->channel2); 1861 } 1862 } 1863 1864 static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) 1865 { 1866 struct device_node *node = indio_dev->dev.of_node; 1867 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 1868 int num_channels = 0, ret; 1869 1870 ret = of_property_count_u32_elems(node, "st,adc-channels"); 1871 if (ret > adc_info->max_channels) { 1872 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); 1873 return -EINVAL; 1874 } else if (ret > 0) { 1875 num_channels += ret; 1876 } 1877 1878 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels", 1879 sizeof(struct stm32_adc_diff_channel)); 1880 if (ret > adc_info->max_channels) { 1881 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); 1882 return -EINVAL; 1883 } else if (ret > 0) { 1884 adc->num_diff = ret; 1885 num_channels += ret; 1886 } 1887 1888 /* Optional sample time is provided either for each, or all channels */ 1889 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs"); 1890 if (ret > 1 && ret != num_channels) { 1891 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); 1892 return -EINVAL; 1893 } 1894 1895 return num_channels; 1896 } 1897 1898 static int stm32_adc_legacy_chan_init(struct iio_dev *indio_dev, 1899 struct stm32_adc *adc, 1900 struct iio_chan_spec *channels) 1901 { 1902 struct device_node *node = indio_dev->dev.of_node; 1903 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 1904 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; 1905 u32 num_diff = adc->num_diff; 1906 int size = num_diff * sizeof(*diff) / sizeof(u32); 1907 int scan_index = 0, val, ret, i; 1908 struct property *prop; 1909 const __be32 *cur; 1910 u32 smp = 0; 1911 1912 if (num_diff) { 1913 ret = of_property_read_u32_array(node, "st,adc-diff-channels", 1914 (u32 *)diff, size); 1915 if (ret) { 1916 dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret); 1917 return ret; 1918 } 1919 1920 for (i = 0; i < num_diff; i++) { 1921 if (diff[i].vinp >= adc_info->max_channels || 1922 diff[i].vinn >= adc_info->max_channels) { 1923 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 1924 diff[i].vinp, diff[i].vinn); 1925 return -EINVAL; 1926 } 1927 1928 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 1929 diff[i].vinp, diff[i].vinn, 1930 scan_index, true); 1931 scan_index++; 1932 } 1933 } 1934 1935 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { 1936 if (val >= adc_info->max_channels) { 1937 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); 1938 return -EINVAL; 1939 } 1940 1941 /* Channel can't be configured both as single-ended & diff */ 1942 for (i = 0; i < num_diff; i++) { 1943 if (val == diff[i].vinp) { 1944 dev_err(&indio_dev->dev, "channel %d misconfigured\n", val); 1945 return -EINVAL; 1946 } 1947 } 1948 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 1949 0, scan_index, false); 1950 scan_index++; 1951 } 1952 1953 for (i = 0; i < scan_index; i++) { 1954 /* 1955 * Using of_property_read_u32_index(), smp value will only be 1956 * modified if valid u32 value can be decoded. This allows to 1957 * get either no value, 1 shared value for all indexes, or one 1958 * value per channel. 1959 */ 1960 of_property_read_u32_index(node, "st,min-sample-time-nsecs", i, &smp); 1961 1962 /* Prepare sampling time settings */ 1963 stm32_adc_smpr_init(adc, channels[i].channel, smp); 1964 } 1965 1966 return scan_index; 1967 } 1968 1969 static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_name, 1970 int chan) 1971 { 1972 struct stm32_adc *adc = iio_priv(indio_dev); 1973 u16 vrefint; 1974 int i, ret; 1975 1976 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 1977 if (!strncmp(stm32_adc_ic[i].name, ch_name, STM32_ADC_CH_SZ)) { 1978 if (stm32_adc_ic[i].idx != STM32_ADC_INT_CH_VREFINT) { 1979 adc->int_ch[i] = chan; 1980 break; 1981 } 1982 1983 /* Get calibration data for vrefint channel */ 1984 ret = nvmem_cell_read_u16(&indio_dev->dev, "vrefint", &vrefint); 1985 if (ret && ret != -ENOENT) { 1986 return dev_err_probe(indio_dev->dev.parent, ret, 1987 "nvmem access error\n"); 1988 } 1989 if (ret == -ENOENT) { 1990 dev_dbg(&indio_dev->dev, "vrefint calibration not found. Skip vrefint channel\n"); 1991 return ret; 1992 } else if (!vrefint) { 1993 dev_dbg(&indio_dev->dev, "Null vrefint calibration value. Skip vrefint channel\n"); 1994 return -ENOENT; 1995 } 1996 adc->int_ch[i] = chan; 1997 adc->vrefint.vrefint_cal = vrefint; 1998 } 1999 } 2000 2001 return 0; 2002 } 2003 2004 static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev, 2005 struct stm32_adc *adc, 2006 struct iio_chan_spec *channels) 2007 { 2008 struct device_node *node = indio_dev->dev.of_node; 2009 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2010 struct device_node *child; 2011 const char *name; 2012 int val, scan_index = 0, ret; 2013 bool differential; 2014 u32 vin[2]; 2015 2016 for_each_available_child_of_node(node, child) { 2017 ret = of_property_read_u32(child, "reg", &val); 2018 if (ret) { 2019 dev_err(&indio_dev->dev, "Missing channel index %d\n", ret); 2020 goto err; 2021 } 2022 2023 ret = of_property_read_string(child, "label", &name); 2024 /* label is optional */ 2025 if (!ret) { 2026 if (strlen(name) >= STM32_ADC_CH_SZ) { 2027 dev_err(&indio_dev->dev, "Label %s exceeds %d characters\n", 2028 name, STM32_ADC_CH_SZ); 2029 ret = -EINVAL; 2030 goto err; 2031 } 2032 strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); 2033 ret = stm32_adc_populate_int_ch(indio_dev, name, val); 2034 if (ret == -ENOENT) 2035 continue; 2036 else if (ret) 2037 goto err; 2038 } else if (ret != -EINVAL) { 2039 dev_err(&indio_dev->dev, "Invalid label %d\n", ret); 2040 goto err; 2041 } 2042 2043 if (val >= adc_info->max_channels) { 2044 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); 2045 ret = -EINVAL; 2046 goto err; 2047 } 2048 2049 differential = false; 2050 ret = of_property_read_u32_array(child, "diff-channels", vin, 2); 2051 /* diff-channels is optional */ 2052 if (!ret) { 2053 differential = true; 2054 if (vin[0] != val || vin[1] >= adc_info->max_channels) { 2055 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 2056 vin[0], vin[1]); 2057 goto err; 2058 } 2059 } else if (ret != -EINVAL) { 2060 dev_err(&indio_dev->dev, "Invalid diff-channels property %d\n", ret); 2061 goto err; 2062 } 2063 2064 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 2065 vin[1], scan_index, differential); 2066 2067 ret = of_property_read_u32(child, "st,min-sample-time-ns", &val); 2068 /* st,min-sample-time-ns is optional */ 2069 if (!ret) { 2070 stm32_adc_smpr_init(adc, channels[scan_index].channel, val); 2071 if (differential) 2072 stm32_adc_smpr_init(adc, vin[1], val); 2073 } else if (ret != -EINVAL) { 2074 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-ns property %d\n", 2075 ret); 2076 goto err; 2077 } 2078 2079 scan_index++; 2080 } 2081 2082 return scan_index; 2083 2084 err: 2085 of_node_put(child); 2086 2087 return ret; 2088 } 2089 2090 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping) 2091 { 2092 struct device_node *node = indio_dev->dev.of_node; 2093 struct stm32_adc *adc = iio_priv(indio_dev); 2094 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2095 struct iio_chan_spec *channels; 2096 int scan_index = 0, num_channels = 0, ret, i; 2097 bool legacy = false; 2098 2099 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) 2100 adc->int_ch[i] = STM32_ADC_INT_CH_NONE; 2101 2102 num_channels = of_get_available_child_count(node); 2103 /* If no channels have been found, fallback to channels legacy properties. */ 2104 if (!num_channels) { 2105 legacy = true; 2106 2107 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); 2108 if (!ret) { 2109 dev_err(indio_dev->dev.parent, "No channel found\n"); 2110 return -ENODATA; 2111 } else if (ret < 0) { 2112 return ret; 2113 } 2114 2115 num_channels = ret; 2116 } 2117 2118 if (num_channels > adc_info->max_channels) { 2119 dev_err(&indio_dev->dev, "Channel number [%d] exceeds %d\n", 2120 num_channels, adc_info->max_channels); 2121 return -EINVAL; 2122 } 2123 2124 if (timestamping) 2125 num_channels++; 2126 2127 channels = devm_kcalloc(&indio_dev->dev, num_channels, 2128 sizeof(struct iio_chan_spec), GFP_KERNEL); 2129 if (!channels) 2130 return -ENOMEM; 2131 2132 if (legacy) 2133 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels); 2134 else 2135 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); 2136 if (ret < 0) 2137 return ret; 2138 scan_index = ret; 2139 2140 if (timestamping) { 2141 struct iio_chan_spec *timestamp = &channels[scan_index]; 2142 2143 timestamp->type = IIO_TIMESTAMP; 2144 timestamp->channel = -1; 2145 timestamp->scan_index = scan_index; 2146 timestamp->scan_type.sign = 's'; 2147 timestamp->scan_type.realbits = 64; 2148 timestamp->scan_type.storagebits = 64; 2149 2150 scan_index++; 2151 } 2152 2153 indio_dev->num_channels = scan_index; 2154 indio_dev->channels = channels; 2155 2156 return 0; 2157 } 2158 2159 static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev) 2160 { 2161 struct stm32_adc *adc = iio_priv(indio_dev); 2162 struct dma_slave_config config; 2163 int ret; 2164 2165 adc->dma_chan = dma_request_chan(dev, "rx"); 2166 if (IS_ERR(adc->dma_chan)) { 2167 ret = PTR_ERR(adc->dma_chan); 2168 if (ret != -ENODEV) 2169 return dev_err_probe(dev, ret, 2170 "DMA channel request failed with\n"); 2171 2172 /* DMA is optional: fall back to IRQ mode */ 2173 adc->dma_chan = NULL; 2174 return 0; 2175 } 2176 2177 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 2178 STM32_DMA_BUFFER_SIZE, 2179 &adc->rx_dma_buf, GFP_KERNEL); 2180 if (!adc->rx_buf) { 2181 ret = -ENOMEM; 2182 goto err_release; 2183 } 2184 2185 /* Configure DMA channel to read data register */ 2186 memset(&config, 0, sizeof(config)); 2187 config.src_addr = (dma_addr_t)adc->common->phys_base; 2188 config.src_addr += adc->offset + adc->cfg->regs->dr; 2189 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 2190 2191 ret = dmaengine_slave_config(adc->dma_chan, &config); 2192 if (ret) 2193 goto err_free; 2194 2195 return 0; 2196 2197 err_free: 2198 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, 2199 adc->rx_buf, adc->rx_dma_buf); 2200 err_release: 2201 dma_release_channel(adc->dma_chan); 2202 2203 return ret; 2204 } 2205 2206 static int stm32_adc_probe(struct platform_device *pdev) 2207 { 2208 struct iio_dev *indio_dev; 2209 struct device *dev = &pdev->dev; 2210 irqreturn_t (*handler)(int irq, void *p) = NULL; 2211 struct stm32_adc *adc; 2212 bool timestamping = false; 2213 int ret; 2214 2215 if (!pdev->dev.of_node) 2216 return -ENODEV; 2217 2218 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 2219 if (!indio_dev) 2220 return -ENOMEM; 2221 2222 adc = iio_priv(indio_dev); 2223 adc->common = dev_get_drvdata(pdev->dev.parent); 2224 spin_lock_init(&adc->lock); 2225 init_completion(&adc->completion); 2226 adc->cfg = (const struct stm32_adc_cfg *) 2227 of_match_device(dev->driver->of_match_table, dev)->data; 2228 2229 indio_dev->name = dev_name(&pdev->dev); 2230 indio_dev->dev.of_node = pdev->dev.of_node; 2231 indio_dev->info = &stm32_adc_iio_info; 2232 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; 2233 2234 platform_set_drvdata(pdev, indio_dev); 2235 2236 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset); 2237 if (ret != 0) { 2238 dev_err(&pdev->dev, "missing reg property\n"); 2239 return -EINVAL; 2240 } 2241 2242 adc->irq = platform_get_irq(pdev, 0); 2243 if (adc->irq < 0) 2244 return adc->irq; 2245 2246 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, 2247 stm32_adc_threaded_isr, 2248 0, pdev->name, indio_dev); 2249 if (ret) { 2250 dev_err(&pdev->dev, "failed to request IRQ\n"); 2251 return ret; 2252 } 2253 2254 adc->clk = devm_clk_get(&pdev->dev, NULL); 2255 if (IS_ERR(adc->clk)) { 2256 ret = PTR_ERR(adc->clk); 2257 if (ret == -ENOENT && !adc->cfg->clk_required) { 2258 adc->clk = NULL; 2259 } else { 2260 dev_err(&pdev->dev, "Can't get clock\n"); 2261 return ret; 2262 } 2263 } 2264 2265 ret = stm32_adc_of_get_resolution(indio_dev); 2266 if (ret < 0) 2267 return ret; 2268 2269 ret = stm32_adc_dma_request(dev, indio_dev); 2270 if (ret < 0) 2271 return ret; 2272 2273 if (!adc->dma_chan) { 2274 /* For PIO mode only, iio_pollfunc_store_time stores a timestamp 2275 * in the primary trigger IRQ handler and stm32_adc_trigger_handler 2276 * runs in the IRQ thread to push out buffer along with timestamp. 2277 */ 2278 handler = &stm32_adc_trigger_handler; 2279 timestamping = true; 2280 } 2281 2282 ret = stm32_adc_chan_of_init(indio_dev, timestamping); 2283 if (ret < 0) 2284 goto err_dma_disable; 2285 2286 ret = iio_triggered_buffer_setup(indio_dev, 2287 &iio_pollfunc_store_time, handler, 2288 &stm32_adc_buffer_setup_ops); 2289 if (ret) { 2290 dev_err(&pdev->dev, "buffer setup failed\n"); 2291 goto err_dma_disable; 2292 } 2293 2294 /* Get stm32-adc-core PM online */ 2295 pm_runtime_get_noresume(dev); 2296 pm_runtime_set_active(dev); 2297 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS); 2298 pm_runtime_use_autosuspend(dev); 2299 pm_runtime_enable(dev); 2300 2301 ret = stm32_adc_hw_start(dev); 2302 if (ret) 2303 goto err_buffer_cleanup; 2304 2305 ret = iio_device_register(indio_dev); 2306 if (ret) { 2307 dev_err(&pdev->dev, "iio dev register failed\n"); 2308 goto err_hw_stop; 2309 } 2310 2311 pm_runtime_mark_last_busy(dev); 2312 pm_runtime_put_autosuspend(dev); 2313 2314 return 0; 2315 2316 err_hw_stop: 2317 stm32_adc_hw_stop(dev); 2318 2319 err_buffer_cleanup: 2320 pm_runtime_disable(dev); 2321 pm_runtime_set_suspended(dev); 2322 pm_runtime_put_noidle(dev); 2323 iio_triggered_buffer_cleanup(indio_dev); 2324 2325 err_dma_disable: 2326 if (adc->dma_chan) { 2327 dma_free_coherent(adc->dma_chan->device->dev, 2328 STM32_DMA_BUFFER_SIZE, 2329 adc->rx_buf, adc->rx_dma_buf); 2330 dma_release_channel(adc->dma_chan); 2331 } 2332 2333 return ret; 2334 } 2335 2336 static int stm32_adc_remove(struct platform_device *pdev) 2337 { 2338 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2339 struct stm32_adc *adc = iio_priv(indio_dev); 2340 2341 pm_runtime_get_sync(&pdev->dev); 2342 iio_device_unregister(indio_dev); 2343 stm32_adc_hw_stop(&pdev->dev); 2344 pm_runtime_disable(&pdev->dev); 2345 pm_runtime_set_suspended(&pdev->dev); 2346 pm_runtime_put_noidle(&pdev->dev); 2347 iio_triggered_buffer_cleanup(indio_dev); 2348 if (adc->dma_chan) { 2349 dma_free_coherent(adc->dma_chan->device->dev, 2350 STM32_DMA_BUFFER_SIZE, 2351 adc->rx_buf, adc->rx_dma_buf); 2352 dma_release_channel(adc->dma_chan); 2353 } 2354 2355 return 0; 2356 } 2357 2358 static int stm32_adc_suspend(struct device *dev) 2359 { 2360 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2361 2362 if (iio_buffer_enabled(indio_dev)) 2363 stm32_adc_buffer_predisable(indio_dev); 2364 2365 return pm_runtime_force_suspend(dev); 2366 } 2367 2368 static int stm32_adc_resume(struct device *dev) 2369 { 2370 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2371 int ret; 2372 2373 ret = pm_runtime_force_resume(dev); 2374 if (ret < 0) 2375 return ret; 2376 2377 if (!iio_buffer_enabled(indio_dev)) 2378 return 0; 2379 2380 ret = stm32_adc_update_scan_mode(indio_dev, 2381 indio_dev->active_scan_mask); 2382 if (ret < 0) 2383 return ret; 2384 2385 return stm32_adc_buffer_postenable(indio_dev); 2386 } 2387 2388 static int stm32_adc_runtime_suspend(struct device *dev) 2389 { 2390 return stm32_adc_hw_stop(dev); 2391 } 2392 2393 static int stm32_adc_runtime_resume(struct device *dev) 2394 { 2395 return stm32_adc_hw_start(dev); 2396 } 2397 2398 static const struct dev_pm_ops stm32_adc_pm_ops = { 2399 SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume) 2400 RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume, 2401 NULL) 2402 }; 2403 2404 static const struct stm32_adc_cfg stm32f4_adc_cfg = { 2405 .regs = &stm32f4_adc_regspec, 2406 .adc_info = &stm32f4_adc_info, 2407 .trigs = stm32f4_adc_trigs, 2408 .clk_required = true, 2409 .start_conv = stm32f4_adc_start_conv, 2410 .stop_conv = stm32f4_adc_stop_conv, 2411 .smp_cycles = stm32f4_adc_smp_cycles, 2412 .irq_clear = stm32f4_adc_irq_clear, 2413 }; 2414 2415 static const struct stm32_adc_cfg stm32h7_adc_cfg = { 2416 .regs = &stm32h7_adc_regspec, 2417 .adc_info = &stm32h7_adc_info, 2418 .trigs = stm32h7_adc_trigs, 2419 .start_conv = stm32h7_adc_start_conv, 2420 .stop_conv = stm32h7_adc_stop_conv, 2421 .prepare = stm32h7_adc_prepare, 2422 .unprepare = stm32h7_adc_unprepare, 2423 .smp_cycles = stm32h7_adc_smp_cycles, 2424 .irq_clear = stm32h7_adc_irq_clear, 2425 }; 2426 2427 static const struct stm32_adc_cfg stm32mp1_adc_cfg = { 2428 .regs = &stm32mp1_adc_regspec, 2429 .adc_info = &stm32h7_adc_info, 2430 .trigs = stm32h7_adc_trigs, 2431 .has_vregready = true, 2432 .start_conv = stm32h7_adc_start_conv, 2433 .stop_conv = stm32h7_adc_stop_conv, 2434 .prepare = stm32h7_adc_prepare, 2435 .unprepare = stm32h7_adc_unprepare, 2436 .smp_cycles = stm32h7_adc_smp_cycles, 2437 .irq_clear = stm32h7_adc_irq_clear, 2438 .ts_vrefint_ns = 4300, 2439 }; 2440 2441 static const struct of_device_id stm32_adc_of_match[] = { 2442 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, 2443 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, 2444 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg }, 2445 {}, 2446 }; 2447 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 2448 2449 static struct platform_driver stm32_adc_driver = { 2450 .probe = stm32_adc_probe, 2451 .remove = stm32_adc_remove, 2452 .driver = { 2453 .name = "stm32-adc", 2454 .of_match_table = stm32_adc_of_match, 2455 .pm = pm_ptr(&stm32_adc_pm_ops), 2456 }, 2457 }; 2458 module_platform_driver(stm32_adc_driver); 2459 2460 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 2461 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver"); 2462 MODULE_LICENSE("GPL v2"); 2463 MODULE_ALIAS("platform:stm32-adc"); 2464