1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/iio/iio.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/timer/stm32-lptim-trigger.h> 16 #include <linux/iio/timer/stm32-timer-trigger.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/trigger_consumer.h> 19 #include <linux/iio/triggered_buffer.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/module.h> 24 #include <linux/mod_devicetable.h> 25 #include <linux/nvmem-consumer.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/property.h> 29 30 #include "stm32-adc-core.h" 31 32 /* Number of linear calibration shadow registers / LINCALRDYW control bits */ 33 #define STM32H7_LINCALFACT_NUM 6 34 35 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ 36 #define STM32H7_BOOST_CLKRATE 20000000UL 37 38 #define STM32_ADC_CH_MAX 20 /* max number of channels */ 39 #define STM32_ADC_CH_SZ 16 /* max channel name size */ 40 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ 41 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */ 42 #define STM32_ADC_TIMEOUT_US 100000 43 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) 44 #define STM32_ADC_HW_STOP_DELAY_MS 100 45 #define STM32_ADC_VREFINT_VOLTAGE 3300 46 47 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE 48 49 /* External trigger enable */ 50 enum stm32_adc_exten { 51 STM32_EXTEN_SWTRIG, 52 STM32_EXTEN_HWTRIG_RISING_EDGE, 53 STM32_EXTEN_HWTRIG_FALLING_EDGE, 54 STM32_EXTEN_HWTRIG_BOTH_EDGES, 55 }; 56 57 /* extsel - trigger mux selection value */ 58 enum stm32_adc_extsel { 59 STM32_EXT0, 60 STM32_EXT1, 61 STM32_EXT2, 62 STM32_EXT3, 63 STM32_EXT4, 64 STM32_EXT5, 65 STM32_EXT6, 66 STM32_EXT7, 67 STM32_EXT8, 68 STM32_EXT9, 69 STM32_EXT10, 70 STM32_EXT11, 71 STM32_EXT12, 72 STM32_EXT13, 73 STM32_EXT14, 74 STM32_EXT15, 75 STM32_EXT16, 76 STM32_EXT17, 77 STM32_EXT18, 78 STM32_EXT19, 79 STM32_EXT20, 80 }; 81 82 enum stm32_adc_int_ch { 83 STM32_ADC_INT_CH_NONE = -1, 84 STM32_ADC_INT_CH_VDDCORE, 85 STM32_ADC_INT_CH_VREFINT, 86 STM32_ADC_INT_CH_VBAT, 87 STM32_ADC_INT_CH_NB, 88 }; 89 90 /** 91 * struct stm32_adc_ic - ADC internal channels 92 * @name: name of the internal channel 93 * @idx: internal channel enum index 94 */ 95 struct stm32_adc_ic { 96 const char *name; 97 u32 idx; 98 }; 99 100 static const struct stm32_adc_ic stm32_adc_ic[STM32_ADC_INT_CH_NB] = { 101 { "vddcore", STM32_ADC_INT_CH_VDDCORE }, 102 { "vrefint", STM32_ADC_INT_CH_VREFINT }, 103 { "vbat", STM32_ADC_INT_CH_VBAT }, 104 }; 105 106 /** 107 * struct stm32_adc_trig_info - ADC trigger info 108 * @name: name of the trigger, corresponding to its source 109 * @extsel: trigger selection 110 */ 111 struct stm32_adc_trig_info { 112 const char *name; 113 enum stm32_adc_extsel extsel; 114 }; 115 116 /** 117 * struct stm32_adc_calib - optional adc calibration data 118 * @calfact_s: Calibration offset for single ended channels 119 * @calfact_d: Calibration offset in differential 120 * @lincalfact: Linearity calibration factor 121 * @calibrated: Indicates calibration status 122 */ 123 struct stm32_adc_calib { 124 u32 calfact_s; 125 u32 calfact_d; 126 u32 lincalfact[STM32H7_LINCALFACT_NUM]; 127 bool calibrated; 128 }; 129 130 /** 131 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc 132 * @reg: register offset 133 * @mask: bitfield mask 134 * @shift: left shift 135 */ 136 struct stm32_adc_regs { 137 int reg; 138 int mask; 139 int shift; 140 }; 141 142 /** 143 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data 144 * @vrefint_cal: vrefint calibration value from nvmem 145 * @vrefint_data: vrefint actual value 146 */ 147 struct stm32_adc_vrefint { 148 u32 vrefint_cal; 149 u32 vrefint_data; 150 }; 151 152 /** 153 * struct stm32_adc_regspec - stm32 registers definition 154 * @dr: data register offset 155 * @ier_eoc: interrupt enable register & eocie bitfield 156 * @ier_ovr: interrupt enable register & overrun bitfield 157 * @isr_eoc: interrupt status register & eoc bitfield 158 * @isr_ovr: interrupt status register & overrun bitfield 159 * @sqr: reference to sequence registers array 160 * @exten: trigger control register & bitfield 161 * @extsel: trigger selection register & bitfield 162 * @res: resolution selection register & bitfield 163 * @smpr: smpr1 & smpr2 registers offset array 164 * @smp_bits: smpr1 & smpr2 index and bitfields 165 * @or_vdd: option register & vddcore bitfield 166 * @ccr_vbat: common register & vbat bitfield 167 * @ccr_vref: common register & vrefint bitfield 168 */ 169 struct stm32_adc_regspec { 170 const u32 dr; 171 const struct stm32_adc_regs ier_eoc; 172 const struct stm32_adc_regs ier_ovr; 173 const struct stm32_adc_regs isr_eoc; 174 const struct stm32_adc_regs isr_ovr; 175 const struct stm32_adc_regs *sqr; 176 const struct stm32_adc_regs exten; 177 const struct stm32_adc_regs extsel; 178 const struct stm32_adc_regs res; 179 const u32 smpr[2]; 180 const struct stm32_adc_regs *smp_bits; 181 const struct stm32_adc_regs or_vdd; 182 const struct stm32_adc_regs ccr_vbat; 183 const struct stm32_adc_regs ccr_vref; 184 }; 185 186 struct stm32_adc; 187 188 /** 189 * struct stm32_adc_cfg - stm32 compatible configuration data 190 * @regs: registers descriptions 191 * @adc_info: per instance input channels definitions 192 * @trigs: external trigger sources 193 * @clk_required: clock is required 194 * @has_vregready: vregready status flag presence 195 * @prepare: optional prepare routine (power-up, enable) 196 * @start_conv: routine to start conversions 197 * @stop_conv: routine to stop conversions 198 * @unprepare: optional unprepare routine (disable, power-down) 199 * @irq_clear: routine to clear irqs 200 * @smp_cycles: programmable sampling time (ADC clock cycles) 201 * @ts_vrefint_ns: vrefint minimum sampling time in ns 202 */ 203 struct stm32_adc_cfg { 204 const struct stm32_adc_regspec *regs; 205 const struct stm32_adc_info *adc_info; 206 struct stm32_adc_trig_info *trigs; 207 bool clk_required; 208 bool has_vregready; 209 int (*prepare)(struct iio_dev *); 210 void (*start_conv)(struct iio_dev *, bool dma); 211 void (*stop_conv)(struct iio_dev *); 212 void (*unprepare)(struct iio_dev *); 213 void (*irq_clear)(struct iio_dev *indio_dev, u32 msk); 214 const unsigned int *smp_cycles; 215 const unsigned int ts_vrefint_ns; 216 }; 217 218 /** 219 * struct stm32_adc - private data of each ADC IIO instance 220 * @common: reference to ADC block common data 221 * @offset: ADC instance register offset in ADC block 222 * @cfg: compatible configuration data 223 * @completion: end of single conversion completion 224 * @buffer: data buffer + 8 bytes for timestamp if enabled 225 * @clk: clock for this adc instance 226 * @irq: interrupt for this adc instance 227 * @lock: spinlock 228 * @bufi: data buffer index 229 * @num_conv: expected number of scan conversions 230 * @res: data resolution (e.g. RES bitfield value) 231 * @trigger_polarity: external trigger polarity (e.g. exten) 232 * @dma_chan: dma channel 233 * @rx_buf: dma rx buffer cpu address 234 * @rx_dma_buf: dma rx buffer bus address 235 * @rx_buf_sz: dma rx buffer size 236 * @difsel: bitmask to set single-ended/differential channel 237 * @pcsel: bitmask to preselect channels on some devices 238 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) 239 * @cal: optional calibration data on some devices 240 * @vrefint: internal reference voltage data 241 * @chan_name: channel name array 242 * @num_diff: number of differential channels 243 * @int_ch: internal channel indexes array 244 * @nsmps: number of channels with optional sample time 245 */ 246 struct stm32_adc { 247 struct stm32_adc_common *common; 248 u32 offset; 249 const struct stm32_adc_cfg *cfg; 250 struct completion completion; 251 u16 buffer[STM32_ADC_MAX_SQ + 4] __aligned(8); 252 struct clk *clk; 253 int irq; 254 spinlock_t lock; /* interrupt lock */ 255 unsigned int bufi; 256 unsigned int num_conv; 257 u32 res; 258 u32 trigger_polarity; 259 struct dma_chan *dma_chan; 260 u8 *rx_buf; 261 dma_addr_t rx_dma_buf; 262 unsigned int rx_buf_sz; 263 u32 difsel; 264 u32 pcsel; 265 u32 smpr_val[2]; 266 struct stm32_adc_calib cal; 267 struct stm32_adc_vrefint vrefint; 268 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ]; 269 u32 num_diff; 270 int int_ch[STM32_ADC_INT_CH_NB]; 271 int nsmps; 272 }; 273 274 struct stm32_adc_diff_channel { 275 u32 vinp; 276 u32 vinn; 277 }; 278 279 /** 280 * struct stm32_adc_info - stm32 ADC, per instance config data 281 * @max_channels: Number of channels 282 * @resolutions: available resolutions 283 * @num_res: number of available resolutions 284 */ 285 struct stm32_adc_info { 286 int max_channels; 287 const unsigned int *resolutions; 288 const unsigned int num_res; 289 }; 290 291 static const unsigned int stm32f4_adc_resolutions[] = { 292 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */ 293 12, 10, 8, 6, 294 }; 295 296 /* stm32f4 can have up to 16 channels */ 297 static const struct stm32_adc_info stm32f4_adc_info = { 298 .max_channels = 16, 299 .resolutions = stm32f4_adc_resolutions, 300 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 301 }; 302 303 static const unsigned int stm32h7_adc_resolutions[] = { 304 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */ 305 16, 14, 12, 10, 8, 306 }; 307 308 /* stm32h7 can have up to 20 channels */ 309 static const struct stm32_adc_info stm32h7_adc_info = { 310 .max_channels = STM32_ADC_CH_MAX, 311 .resolutions = stm32h7_adc_resolutions, 312 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), 313 }; 314 315 /* 316 * stm32f4_sq - describe regular sequence registers 317 * - L: sequence len (register & bit field) 318 * - SQ1..SQ16: sequence entries (register & bit field) 319 */ 320 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = { 321 /* L: len bit field description to be kept as first element */ 322 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 }, 323 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 324 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 }, 325 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 }, 326 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 }, 327 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 }, 328 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 }, 329 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 }, 330 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 }, 331 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 }, 332 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 }, 333 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 }, 334 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 }, 335 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 }, 336 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 }, 337 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 }, 338 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 }, 339 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 }, 340 }; 341 342 /* STM32F4 external trigger sources for all instances */ 343 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 344 { TIM1_CH1, STM32_EXT0 }, 345 { TIM1_CH2, STM32_EXT1 }, 346 { TIM1_CH3, STM32_EXT2 }, 347 { TIM2_CH2, STM32_EXT3 }, 348 { TIM2_CH3, STM32_EXT4 }, 349 { TIM2_CH4, STM32_EXT5 }, 350 { TIM2_TRGO, STM32_EXT6 }, 351 { TIM3_CH1, STM32_EXT7 }, 352 { TIM3_TRGO, STM32_EXT8 }, 353 { TIM4_CH4, STM32_EXT9 }, 354 { TIM5_CH1, STM32_EXT10 }, 355 { TIM5_CH2, STM32_EXT11 }, 356 { TIM5_CH3, STM32_EXT12 }, 357 { TIM8_CH1, STM32_EXT13 }, 358 { TIM8_TRGO, STM32_EXT14 }, 359 {}, /* sentinel */ 360 }; 361 362 /* 363 * stm32f4_smp_bits[] - describe sampling time register index & bit fields 364 * Sorted so it can be indexed by channel number. 365 */ 366 static const struct stm32_adc_regs stm32f4_smp_bits[] = { 367 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */ 368 { 1, GENMASK(2, 0), 0 }, 369 { 1, GENMASK(5, 3), 3 }, 370 { 1, GENMASK(8, 6), 6 }, 371 { 1, GENMASK(11, 9), 9 }, 372 { 1, GENMASK(14, 12), 12 }, 373 { 1, GENMASK(17, 15), 15 }, 374 { 1, GENMASK(20, 18), 18 }, 375 { 1, GENMASK(23, 21), 21 }, 376 { 1, GENMASK(26, 24), 24 }, 377 { 1, GENMASK(29, 27), 27 }, 378 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */ 379 { 0, GENMASK(2, 0), 0 }, 380 { 0, GENMASK(5, 3), 3 }, 381 { 0, GENMASK(8, 6), 6 }, 382 { 0, GENMASK(11, 9), 9 }, 383 { 0, GENMASK(14, 12), 12 }, 384 { 0, GENMASK(17, 15), 15 }, 385 { 0, GENMASK(20, 18), 18 }, 386 { 0, GENMASK(23, 21), 21 }, 387 { 0, GENMASK(26, 24), 24 }, 388 }; 389 390 /* STM32F4 programmable sampling time (ADC clock cycles) */ 391 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 392 3, 15, 28, 56, 84, 112, 144, 480, 393 }; 394 395 static const struct stm32_adc_regspec stm32f4_adc_regspec = { 396 .dr = STM32F4_ADC_DR, 397 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE }, 398 .ier_ovr = { STM32F4_ADC_CR1, STM32F4_OVRIE }, 399 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC }, 400 .isr_ovr = { STM32F4_ADC_SR, STM32F4_OVR }, 401 .sqr = stm32f4_sq, 402 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT }, 403 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK, 404 STM32F4_EXTSEL_SHIFT }, 405 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT }, 406 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 }, 407 .smp_bits = stm32f4_smp_bits, 408 }; 409 410 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = { 411 /* L: len bit field description to be kept as first element */ 412 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 }, 413 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 414 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 }, 415 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 }, 416 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 }, 417 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 }, 418 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 }, 419 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 }, 420 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 }, 421 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 }, 422 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 }, 423 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 }, 424 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 }, 425 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 }, 426 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 }, 427 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 }, 428 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 }, 429 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 }, 430 }; 431 432 /* STM32H7 external trigger sources for all instances */ 433 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 434 { TIM1_CH1, STM32_EXT0 }, 435 { TIM1_CH2, STM32_EXT1 }, 436 { TIM1_CH3, STM32_EXT2 }, 437 { TIM2_CH2, STM32_EXT3 }, 438 { TIM3_TRGO, STM32_EXT4 }, 439 { TIM4_CH4, STM32_EXT5 }, 440 { TIM8_TRGO, STM32_EXT7 }, 441 { TIM8_TRGO2, STM32_EXT8 }, 442 { TIM1_TRGO, STM32_EXT9 }, 443 { TIM1_TRGO2, STM32_EXT10 }, 444 { TIM2_TRGO, STM32_EXT11 }, 445 { TIM4_TRGO, STM32_EXT12 }, 446 { TIM6_TRGO, STM32_EXT13 }, 447 { TIM15_TRGO, STM32_EXT14 }, 448 { TIM3_CH4, STM32_EXT15 }, 449 { LPTIM1_OUT, STM32_EXT18 }, 450 { LPTIM2_OUT, STM32_EXT19 }, 451 { LPTIM3_OUT, STM32_EXT20 }, 452 {}, 453 }; 454 455 /* 456 * stm32h7_smp_bits - describe sampling time register index & bit fields 457 * Sorted so it can be indexed by channel number. 458 */ 459 static const struct stm32_adc_regs stm32h7_smp_bits[] = { 460 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */ 461 { 0, GENMASK(2, 0), 0 }, 462 { 0, GENMASK(5, 3), 3 }, 463 { 0, GENMASK(8, 6), 6 }, 464 { 0, GENMASK(11, 9), 9 }, 465 { 0, GENMASK(14, 12), 12 }, 466 { 0, GENMASK(17, 15), 15 }, 467 { 0, GENMASK(20, 18), 18 }, 468 { 0, GENMASK(23, 21), 21 }, 469 { 0, GENMASK(26, 24), 24 }, 470 { 0, GENMASK(29, 27), 27 }, 471 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */ 472 { 1, GENMASK(2, 0), 0 }, 473 { 1, GENMASK(5, 3), 3 }, 474 { 1, GENMASK(8, 6), 6 }, 475 { 1, GENMASK(11, 9), 9 }, 476 { 1, GENMASK(14, 12), 12 }, 477 { 1, GENMASK(17, 15), 15 }, 478 { 1, GENMASK(20, 18), 18 }, 479 { 1, GENMASK(23, 21), 21 }, 480 { 1, GENMASK(26, 24), 24 }, 481 { 1, GENMASK(29, 27), 27 }, 482 }; 483 484 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */ 485 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 486 1, 2, 8, 16, 32, 64, 387, 810, 487 }; 488 489 static const struct stm32_adc_regspec stm32h7_adc_regspec = { 490 .dr = STM32H7_ADC_DR, 491 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 492 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 493 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 494 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 495 .sqr = stm32h7_sq, 496 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 497 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 498 STM32H7_EXTSEL_SHIFT }, 499 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 500 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 501 .smp_bits = stm32h7_smp_bits, 502 }; 503 504 static const struct stm32_adc_regspec stm32mp1_adc_regspec = { 505 .dr = STM32H7_ADC_DR, 506 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 507 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 508 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 509 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 510 .sqr = stm32h7_sq, 511 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 512 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 513 STM32H7_EXTSEL_SHIFT }, 514 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 515 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 516 .smp_bits = stm32h7_smp_bits, 517 .or_vdd = { STM32MP1_ADC2_OR, STM32MP1_VDDCOREEN }, 518 .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, 519 .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, 520 }; 521 522 /* 523 * STM32 ADC registers access routines 524 * @adc: stm32 adc instance 525 * @reg: reg offset in adc instance 526 * 527 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. 528 * for adc1, adc2 and adc3. 529 */ 530 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) 531 { 532 return readl_relaxed(adc->common->base + adc->offset + reg); 533 } 534 535 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr) 536 537 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ 538 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ 539 cond, sleep_us, timeout_us) 540 541 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) 542 { 543 return readw_relaxed(adc->common->base + adc->offset + reg); 544 } 545 546 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) 547 { 548 writel_relaxed(val, adc->common->base + adc->offset + reg); 549 } 550 551 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) 552 { 553 unsigned long flags; 554 555 spin_lock_irqsave(&adc->lock, flags); 556 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); 557 spin_unlock_irqrestore(&adc->lock, flags); 558 } 559 560 static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) 561 { 562 spin_lock(&adc->common->lock); 563 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, 564 adc->common->base + reg); 565 spin_unlock(&adc->common->lock); 566 } 567 568 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) 569 { 570 unsigned long flags; 571 572 spin_lock_irqsave(&adc->lock, flags); 573 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); 574 spin_unlock_irqrestore(&adc->lock, flags); 575 } 576 577 static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) 578 { 579 spin_lock(&adc->common->lock); 580 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, 581 adc->common->base + reg); 582 spin_unlock(&adc->common->lock); 583 } 584 585 /** 586 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt 587 * @adc: stm32 adc instance 588 */ 589 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) 590 { 591 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, 592 adc->cfg->regs->ier_eoc.mask); 593 }; 594 595 /** 596 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt 597 * @adc: stm32 adc instance 598 */ 599 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) 600 { 601 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, 602 adc->cfg->regs->ier_eoc.mask); 603 } 604 605 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) 606 { 607 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, 608 adc->cfg->regs->ier_ovr.mask); 609 } 610 611 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) 612 { 613 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, 614 adc->cfg->regs->ier_ovr.mask); 615 } 616 617 static void stm32_adc_set_res(struct stm32_adc *adc) 618 { 619 const struct stm32_adc_regs *res = &adc->cfg->regs->res; 620 u32 val; 621 622 val = stm32_adc_readl(adc, res->reg); 623 val = (val & ~res->mask) | (adc->res << res->shift); 624 stm32_adc_writel(adc, res->reg, val); 625 } 626 627 static int stm32_adc_hw_stop(struct device *dev) 628 { 629 struct iio_dev *indio_dev = dev_get_drvdata(dev); 630 struct stm32_adc *adc = iio_priv(indio_dev); 631 632 if (adc->cfg->unprepare) 633 adc->cfg->unprepare(indio_dev); 634 635 clk_disable_unprepare(adc->clk); 636 637 return 0; 638 } 639 640 static int stm32_adc_hw_start(struct device *dev) 641 { 642 struct iio_dev *indio_dev = dev_get_drvdata(dev); 643 struct stm32_adc *adc = iio_priv(indio_dev); 644 int ret; 645 646 ret = clk_prepare_enable(adc->clk); 647 if (ret) 648 return ret; 649 650 stm32_adc_set_res(adc); 651 652 if (adc->cfg->prepare) { 653 ret = adc->cfg->prepare(indio_dev); 654 if (ret) 655 goto err_clk_dis; 656 } 657 658 return 0; 659 660 err_clk_dis: 661 clk_disable_unprepare(adc->clk); 662 663 return ret; 664 } 665 666 static void stm32_adc_int_ch_enable(struct iio_dev *indio_dev) 667 { 668 struct stm32_adc *adc = iio_priv(indio_dev); 669 u32 i; 670 671 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 672 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) 673 continue; 674 675 switch (i) { 676 case STM32_ADC_INT_CH_VDDCORE: 677 dev_dbg(&indio_dev->dev, "Enable VDDCore\n"); 678 stm32_adc_set_bits(adc, adc->cfg->regs->or_vdd.reg, 679 adc->cfg->regs->or_vdd.mask); 680 break; 681 case STM32_ADC_INT_CH_VREFINT: 682 dev_dbg(&indio_dev->dev, "Enable VREFInt\n"); 683 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, 684 adc->cfg->regs->ccr_vref.mask); 685 break; 686 case STM32_ADC_INT_CH_VBAT: 687 dev_dbg(&indio_dev->dev, "Enable VBAT\n"); 688 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, 689 adc->cfg->regs->ccr_vbat.mask); 690 break; 691 } 692 } 693 } 694 695 static void stm32_adc_int_ch_disable(struct stm32_adc *adc) 696 { 697 u32 i; 698 699 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 700 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) 701 continue; 702 703 switch (i) { 704 case STM32_ADC_INT_CH_VDDCORE: 705 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vdd.reg, 706 adc->cfg->regs->or_vdd.mask); 707 break; 708 case STM32_ADC_INT_CH_VREFINT: 709 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, 710 adc->cfg->regs->ccr_vref.mask); 711 break; 712 case STM32_ADC_INT_CH_VBAT: 713 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, 714 adc->cfg->regs->ccr_vbat.mask); 715 break; 716 } 717 } 718 } 719 720 /** 721 * stm32f4_adc_start_conv() - Start conversions for regular channels. 722 * @indio_dev: IIO device instance 723 * @dma: use dma to transfer conversion result 724 * 725 * Start conversions for regular channels. 726 * Also take care of normal or DMA mode. Circular DMA may be used for regular 727 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct 728 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). 729 */ 730 static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma) 731 { 732 struct stm32_adc *adc = iio_priv(indio_dev); 733 734 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 735 736 if (dma) 737 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, 738 STM32F4_DMA | STM32F4_DDS); 739 740 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); 741 742 /* Wait for Power-up time (tSTAB from datasheet) */ 743 usleep_range(2, 3); 744 745 /* Software start ? (e.g. trigger detection disabled ?) */ 746 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) 747 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); 748 } 749 750 static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev) 751 { 752 struct stm32_adc *adc = iio_priv(indio_dev); 753 754 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 755 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); 756 757 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 758 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, 759 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); 760 } 761 762 static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 763 { 764 struct stm32_adc *adc = iio_priv(indio_dev); 765 766 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 767 } 768 769 static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma) 770 { 771 struct stm32_adc *adc = iio_priv(indio_dev); 772 enum stm32h7_adc_dmngt dmngt; 773 unsigned long flags; 774 u32 val; 775 776 if (dma) 777 dmngt = STM32H7_DMNGT_DMA_CIRC; 778 else 779 dmngt = STM32H7_DMNGT_DR_ONLY; 780 781 spin_lock_irqsave(&adc->lock, flags); 782 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); 783 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); 784 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); 785 spin_unlock_irqrestore(&adc->lock, flags); 786 787 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 788 } 789 790 static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev) 791 { 792 struct stm32_adc *adc = iio_priv(indio_dev); 793 int ret; 794 u32 val; 795 796 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); 797 798 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 799 !(val & (STM32H7_ADSTART)), 800 100, STM32_ADC_TIMEOUT_US); 801 if (ret) 802 dev_warn(&indio_dev->dev, "stop failed\n"); 803 804 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); 805 } 806 807 static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 808 { 809 struct stm32_adc *adc = iio_priv(indio_dev); 810 /* On STM32H7 IRQs are cleared by writing 1 into ISR register */ 811 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 812 } 813 814 static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev) 815 { 816 struct stm32_adc *adc = iio_priv(indio_dev); 817 int ret; 818 u32 val; 819 820 /* Exit deep power down, then enable ADC voltage regulator */ 821 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 822 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); 823 824 if (adc->common->rate > STM32H7_BOOST_CLKRATE) 825 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 826 827 /* Wait for startup time */ 828 if (!adc->cfg->has_vregready) { 829 usleep_range(10, 20); 830 return 0; 831 } 832 833 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 834 val & STM32MP1_VREGREADY, 100, 835 STM32_ADC_TIMEOUT_US); 836 if (ret) { 837 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 838 dev_err(&indio_dev->dev, "Failed to exit power down\n"); 839 } 840 841 return ret; 842 } 843 844 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) 845 { 846 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 847 848 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ 849 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 850 } 851 852 static int stm32h7_adc_enable(struct iio_dev *indio_dev) 853 { 854 struct stm32_adc *adc = iio_priv(indio_dev); 855 int ret; 856 u32 val; 857 858 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); 859 860 /* Poll for ADRDY to be set (after adc startup time) */ 861 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 862 val & STM32H7_ADRDY, 863 100, STM32_ADC_TIMEOUT_US); 864 if (ret) { 865 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 866 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); 867 } else { 868 /* Clear ADRDY by writing one */ 869 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); 870 } 871 872 return ret; 873 } 874 875 static void stm32h7_adc_disable(struct iio_dev *indio_dev) 876 { 877 struct stm32_adc *adc = iio_priv(indio_dev); 878 int ret; 879 u32 val; 880 881 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) 882 return; 883 884 /* Disable ADC and wait until it's effectively disabled */ 885 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 886 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 887 !(val & STM32H7_ADEN), 100, 888 STM32_ADC_TIMEOUT_US); 889 if (ret) 890 dev_warn(&indio_dev->dev, "Failed to disable\n"); 891 } 892 893 /** 894 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result 895 * @indio_dev: IIO device instance 896 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable 897 */ 898 static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev) 899 { 900 struct stm32_adc *adc = iio_priv(indio_dev); 901 int i, ret; 902 u32 lincalrdyw_mask, val; 903 904 /* Read linearity calibration */ 905 lincalrdyw_mask = STM32H7_LINCALRDYW6; 906 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 907 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */ 908 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 909 910 /* Poll: wait calib data to be ready in CALFACT2 register */ 911 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 912 !(val & lincalrdyw_mask), 913 100, STM32_ADC_TIMEOUT_US); 914 if (ret) { 915 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 916 return ret; 917 } 918 919 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 920 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); 921 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; 922 923 lincalrdyw_mask >>= 1; 924 } 925 926 /* Read offset calibration */ 927 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); 928 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); 929 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; 930 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); 931 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; 932 adc->cal.calibrated = true; 933 934 return 0; 935 } 936 937 /** 938 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result 939 * @indio_dev: IIO device instance 940 * Note: ADC must be enabled, with no on-going conversions. 941 */ 942 static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev) 943 { 944 struct stm32_adc *adc = iio_priv(indio_dev); 945 int i, ret; 946 u32 lincalrdyw_mask, val; 947 948 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | 949 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); 950 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); 951 952 lincalrdyw_mask = STM32H7_LINCALRDYW6; 953 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 954 /* 955 * Write saved calibration data to shadow registers: 956 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger 957 * data write. Then poll to wait for complete transfer. 958 */ 959 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; 960 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); 961 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 962 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 963 val & lincalrdyw_mask, 964 100, STM32_ADC_TIMEOUT_US); 965 if (ret) { 966 dev_err(&indio_dev->dev, "Failed to write calfact\n"); 967 return ret; 968 } 969 970 /* 971 * Read back calibration data, has two effects: 972 * - It ensures bits LINCALRDYW[6..1] are kept cleared 973 * for next time calibration needs to be restored. 974 * - BTW, bit clear triggers a read, then check data has been 975 * correctly written. 976 */ 977 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 978 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 979 !(val & lincalrdyw_mask), 980 100, STM32_ADC_TIMEOUT_US); 981 if (ret) { 982 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 983 return ret; 984 } 985 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 986 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { 987 dev_err(&indio_dev->dev, "calfact not consistent\n"); 988 return -EIO; 989 } 990 991 lincalrdyw_mask >>= 1; 992 } 993 994 return 0; 995 } 996 997 /* 998 * Fixed timeout value for ADC calibration. 999 * worst cases: 1000 * - low clock frequency 1001 * - maximum prescalers 1002 * Calibration requires: 1003 * - 131,072 ADC clock cycle for the linear calibration 1004 * - 20 ADC clock cycle for the offset calibration 1005 * 1006 * Set to 100ms for now 1007 */ 1008 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000 1009 1010 /** 1011 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC 1012 * @indio_dev: IIO device instance 1013 * Note: Must be called once ADC is out of power down. 1014 */ 1015 static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev) 1016 { 1017 struct stm32_adc *adc = iio_priv(indio_dev); 1018 int ret; 1019 u32 val; 1020 1021 if (adc->cal.calibrated) 1022 return true; 1023 1024 /* ADC must be disabled for calibration */ 1025 stm32h7_adc_disable(indio_dev); 1026 1027 /* 1028 * Select calibration mode: 1029 * - Offset calibration for single ended inputs 1030 * - No linearity calibration (do it later, before reading it) 1031 */ 1032 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); 1033 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); 1034 1035 /* Start calibration, then wait for completion */ 1036 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1037 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1038 !(val & STM32H7_ADCAL), 100, 1039 STM32H7_ADC_CALIB_TIMEOUT_US); 1040 if (ret) { 1041 dev_err(&indio_dev->dev, "calibration failed\n"); 1042 goto out; 1043 } 1044 1045 /* 1046 * Select calibration mode, then start calibration: 1047 * - Offset calibration for differential input 1048 * - Linearity calibration (needs to be done only once for single/diff) 1049 * will run simultaneously with offset calibration. 1050 */ 1051 stm32_adc_set_bits(adc, STM32H7_ADC_CR, 1052 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 1053 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1054 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1055 !(val & STM32H7_ADCAL), 100, 1056 STM32H7_ADC_CALIB_TIMEOUT_US); 1057 if (ret) { 1058 dev_err(&indio_dev->dev, "calibration failed\n"); 1059 goto out; 1060 } 1061 1062 out: 1063 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, 1064 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 1065 1066 return ret; 1067 } 1068 1069 /** 1070 * stm32h7_adc_prepare() - Leave power down mode to enable ADC. 1071 * @indio_dev: IIO device instance 1072 * Leave power down mode. 1073 * Configure channels as single ended or differential before enabling ADC. 1074 * Enable ADC. 1075 * Restore calibration data. 1076 * Pre-select channels that may be used in PCSEL (required by input MUX / IO): 1077 * - Only one input is selected for single ended (e.g. 'vinp') 1078 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn') 1079 */ 1080 static int stm32h7_adc_prepare(struct iio_dev *indio_dev) 1081 { 1082 struct stm32_adc *adc = iio_priv(indio_dev); 1083 int calib, ret; 1084 1085 ret = stm32h7_adc_exit_pwr_down(indio_dev); 1086 if (ret) 1087 return ret; 1088 1089 ret = stm32h7_adc_selfcalib(indio_dev); 1090 if (ret < 0) 1091 goto pwr_dwn; 1092 calib = ret; 1093 1094 stm32_adc_int_ch_enable(indio_dev); 1095 1096 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); 1097 1098 ret = stm32h7_adc_enable(indio_dev); 1099 if (ret) 1100 goto ch_disable; 1101 1102 /* Either restore or read calibration result for future reference */ 1103 if (calib) 1104 ret = stm32h7_adc_restore_selfcalib(indio_dev); 1105 else 1106 ret = stm32h7_adc_read_selfcalib(indio_dev); 1107 if (ret) 1108 goto disable; 1109 1110 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 1111 1112 return 0; 1113 1114 disable: 1115 stm32h7_adc_disable(indio_dev); 1116 ch_disable: 1117 stm32_adc_int_ch_disable(adc); 1118 pwr_dwn: 1119 stm32h7_adc_enter_pwr_down(adc); 1120 1121 return ret; 1122 } 1123 1124 static void stm32h7_adc_unprepare(struct iio_dev *indio_dev) 1125 { 1126 struct stm32_adc *adc = iio_priv(indio_dev); 1127 1128 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); 1129 stm32h7_adc_disable(indio_dev); 1130 stm32_adc_int_ch_disable(adc); 1131 stm32h7_adc_enter_pwr_down(adc); 1132 } 1133 1134 /** 1135 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence 1136 * @indio_dev: IIO device 1137 * @scan_mask: channels to be converted 1138 * 1139 * Conversion sequence : 1140 * Apply sampling time settings for all channels. 1141 * Configure ADC scan sequence based on selected channels in scan_mask. 1142 * Add channels to SQR registers, from scan_mask LSB to MSB, then 1143 * program sequence len. 1144 */ 1145 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, 1146 const unsigned long *scan_mask) 1147 { 1148 struct stm32_adc *adc = iio_priv(indio_dev); 1149 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; 1150 const struct iio_chan_spec *chan; 1151 u32 val, bit; 1152 int i = 0; 1153 1154 /* Apply sampling time settings */ 1155 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); 1156 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); 1157 1158 for_each_set_bit(bit, scan_mask, indio_dev->masklength) { 1159 chan = indio_dev->channels + bit; 1160 /* 1161 * Assign one channel per SQ entry in regular 1162 * sequence, starting with SQ1. 1163 */ 1164 i++; 1165 if (i > STM32_ADC_MAX_SQ) 1166 return -EINVAL; 1167 1168 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", 1169 __func__, chan->channel, i); 1170 1171 val = stm32_adc_readl(adc, sqr[i].reg); 1172 val &= ~sqr[i].mask; 1173 val |= chan->channel << sqr[i].shift; 1174 stm32_adc_writel(adc, sqr[i].reg, val); 1175 } 1176 1177 if (!i) 1178 return -EINVAL; 1179 1180 /* Sequence len */ 1181 val = stm32_adc_readl(adc, sqr[0].reg); 1182 val &= ~sqr[0].mask; 1183 val |= ((i - 1) << sqr[0].shift); 1184 stm32_adc_writel(adc, sqr[0].reg, val); 1185 1186 return 0; 1187 } 1188 1189 /** 1190 * stm32_adc_get_trig_extsel() - Get external trigger selection 1191 * @indio_dev: IIO device structure 1192 * @trig: trigger 1193 * 1194 * Returns trigger extsel value, if trig matches, -EINVAL otherwise. 1195 */ 1196 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, 1197 struct iio_trigger *trig) 1198 { 1199 struct stm32_adc *adc = iio_priv(indio_dev); 1200 int i; 1201 1202 /* lookup triggers registered by stm32 timer trigger driver */ 1203 for (i = 0; adc->cfg->trigs[i].name; i++) { 1204 /** 1205 * Checking both stm32 timer trigger type and trig name 1206 * should be safe against arbitrary trigger names. 1207 */ 1208 if ((is_stm32_timer_trigger(trig) || 1209 is_stm32_lptim_trigger(trig)) && 1210 !strcmp(adc->cfg->trigs[i].name, trig->name)) { 1211 return adc->cfg->trigs[i].extsel; 1212 } 1213 } 1214 1215 return -EINVAL; 1216 } 1217 1218 /** 1219 * stm32_adc_set_trig() - Set a regular trigger 1220 * @indio_dev: IIO device 1221 * @trig: IIO trigger 1222 * 1223 * Set trigger source/polarity (e.g. SW, or HW with polarity) : 1224 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) 1225 * - if HW trigger enabled, set source & polarity 1226 */ 1227 static int stm32_adc_set_trig(struct iio_dev *indio_dev, 1228 struct iio_trigger *trig) 1229 { 1230 struct stm32_adc *adc = iio_priv(indio_dev); 1231 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; 1232 unsigned long flags; 1233 int ret; 1234 1235 if (trig) { 1236 ret = stm32_adc_get_trig_extsel(indio_dev, trig); 1237 if (ret < 0) 1238 return ret; 1239 1240 /* set trigger source and polarity (default to rising edge) */ 1241 extsel = ret; 1242 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; 1243 } 1244 1245 spin_lock_irqsave(&adc->lock, flags); 1246 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); 1247 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); 1248 val |= exten << adc->cfg->regs->exten.shift; 1249 val |= extsel << adc->cfg->regs->extsel.shift; 1250 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); 1251 spin_unlock_irqrestore(&adc->lock, flags); 1252 1253 return 0; 1254 } 1255 1256 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, 1257 const struct iio_chan_spec *chan, 1258 unsigned int type) 1259 { 1260 struct stm32_adc *adc = iio_priv(indio_dev); 1261 1262 adc->trigger_polarity = type; 1263 1264 return 0; 1265 } 1266 1267 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, 1268 const struct iio_chan_spec *chan) 1269 { 1270 struct stm32_adc *adc = iio_priv(indio_dev); 1271 1272 return adc->trigger_polarity; 1273 } 1274 1275 static const char * const stm32_trig_pol_items[] = { 1276 "rising-edge", "falling-edge", "both-edges", 1277 }; 1278 1279 static const struct iio_enum stm32_adc_trig_pol = { 1280 .items = stm32_trig_pol_items, 1281 .num_items = ARRAY_SIZE(stm32_trig_pol_items), 1282 .get = stm32_adc_get_trig_pol, 1283 .set = stm32_adc_set_trig_pol, 1284 }; 1285 1286 /** 1287 * stm32_adc_single_conv() - Performs a single conversion 1288 * @indio_dev: IIO device 1289 * @chan: IIO channel 1290 * @res: conversion result 1291 * 1292 * The function performs a single conversion on a given channel: 1293 * - Apply sampling time settings 1294 * - Program sequencer with one channel (e.g. in SQ1 with len = 1) 1295 * - Use SW trigger 1296 * - Start conversion, then wait for interrupt completion. 1297 */ 1298 static int stm32_adc_single_conv(struct iio_dev *indio_dev, 1299 const struct iio_chan_spec *chan, 1300 int *res) 1301 { 1302 struct stm32_adc *adc = iio_priv(indio_dev); 1303 struct device *dev = indio_dev->dev.parent; 1304 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1305 long timeout; 1306 u32 val; 1307 int ret; 1308 1309 reinit_completion(&adc->completion); 1310 1311 adc->bufi = 0; 1312 1313 ret = pm_runtime_resume_and_get(dev); 1314 if (ret < 0) 1315 return ret; 1316 1317 /* Apply sampling time settings */ 1318 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); 1319 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); 1320 1321 /* Program chan number in regular sequence (SQ1) */ 1322 val = stm32_adc_readl(adc, regs->sqr[1].reg); 1323 val &= ~regs->sqr[1].mask; 1324 val |= chan->channel << regs->sqr[1].shift; 1325 stm32_adc_writel(adc, regs->sqr[1].reg, val); 1326 1327 /* Set regular sequence len (0 for 1 conversion) */ 1328 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); 1329 1330 /* Trigger detection disabled (conversion can be launched in SW) */ 1331 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); 1332 1333 stm32_adc_conv_irq_enable(adc); 1334 1335 adc->cfg->start_conv(indio_dev, false); 1336 1337 timeout = wait_for_completion_interruptible_timeout( 1338 &adc->completion, STM32_ADC_TIMEOUT); 1339 if (timeout == 0) { 1340 ret = -ETIMEDOUT; 1341 } else if (timeout < 0) { 1342 ret = timeout; 1343 } else { 1344 *res = adc->buffer[0]; 1345 ret = IIO_VAL_INT; 1346 } 1347 1348 adc->cfg->stop_conv(indio_dev); 1349 1350 stm32_adc_conv_irq_disable(adc); 1351 1352 pm_runtime_mark_last_busy(dev); 1353 pm_runtime_put_autosuspend(dev); 1354 1355 return ret; 1356 } 1357 1358 static int stm32_adc_read_raw(struct iio_dev *indio_dev, 1359 struct iio_chan_spec const *chan, 1360 int *val, int *val2, long mask) 1361 { 1362 struct stm32_adc *adc = iio_priv(indio_dev); 1363 int ret; 1364 1365 switch (mask) { 1366 case IIO_CHAN_INFO_RAW: 1367 case IIO_CHAN_INFO_PROCESSED: 1368 ret = iio_device_claim_direct_mode(indio_dev); 1369 if (ret) 1370 return ret; 1371 if (chan->type == IIO_VOLTAGE) 1372 ret = stm32_adc_single_conv(indio_dev, chan, val); 1373 else 1374 ret = -EINVAL; 1375 1376 if (mask == IIO_CHAN_INFO_PROCESSED) 1377 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; 1378 1379 iio_device_release_direct_mode(indio_dev); 1380 return ret; 1381 1382 case IIO_CHAN_INFO_SCALE: 1383 if (chan->differential) { 1384 *val = adc->common->vref_mv * 2; 1385 *val2 = chan->scan_type.realbits; 1386 } else { 1387 *val = adc->common->vref_mv; 1388 *val2 = chan->scan_type.realbits; 1389 } 1390 return IIO_VAL_FRACTIONAL_LOG2; 1391 1392 case IIO_CHAN_INFO_OFFSET: 1393 if (chan->differential) 1394 /* ADC_full_scale / 2 */ 1395 *val = -((1 << chan->scan_type.realbits) / 2); 1396 else 1397 *val = 0; 1398 return IIO_VAL_INT; 1399 1400 default: 1401 return -EINVAL; 1402 } 1403 } 1404 1405 static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 1406 { 1407 struct stm32_adc *adc = iio_priv(indio_dev); 1408 1409 adc->cfg->irq_clear(indio_dev, msk); 1410 } 1411 1412 static irqreturn_t stm32_adc_threaded_isr(int irq, void *data) 1413 { 1414 struct iio_dev *indio_dev = data; 1415 struct stm32_adc *adc = iio_priv(indio_dev); 1416 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1417 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1418 1419 /* Check ovr status right now, as ovr mask should be already disabled */ 1420 if (status & regs->isr_ovr.mask) { 1421 /* 1422 * Clear ovr bit to avoid subsequent calls to IRQ handler. 1423 * This requires to stop ADC first. OVR bit state in ISR, 1424 * is propaged to CSR register by hardware. 1425 */ 1426 adc->cfg->stop_conv(indio_dev); 1427 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask); 1428 dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n"); 1429 return IRQ_HANDLED; 1430 } 1431 1432 return IRQ_NONE; 1433 } 1434 1435 static irqreturn_t stm32_adc_isr(int irq, void *data) 1436 { 1437 struct iio_dev *indio_dev = data; 1438 struct stm32_adc *adc = iio_priv(indio_dev); 1439 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1440 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1441 1442 if (status & regs->isr_ovr.mask) { 1443 /* 1444 * Overrun occurred on regular conversions: data for wrong 1445 * channel may be read. Unconditionally disable interrupts 1446 * to stop processing data and print error message. 1447 * Restarting the capture can be done by disabling, then 1448 * re-enabling it (e.g. write 0, then 1 to buffer/enable). 1449 */ 1450 stm32_adc_ovr_irq_disable(adc); 1451 stm32_adc_conv_irq_disable(adc); 1452 return IRQ_WAKE_THREAD; 1453 } 1454 1455 if (status & regs->isr_eoc.mask) { 1456 /* Reading DR also clears EOC status flag */ 1457 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); 1458 if (iio_buffer_enabled(indio_dev)) { 1459 adc->bufi++; 1460 if (adc->bufi >= adc->num_conv) { 1461 stm32_adc_conv_irq_disable(adc); 1462 iio_trigger_poll(indio_dev->trig); 1463 } 1464 } else { 1465 complete(&adc->completion); 1466 } 1467 return IRQ_HANDLED; 1468 } 1469 1470 return IRQ_NONE; 1471 } 1472 1473 /** 1474 * stm32_adc_validate_trigger() - validate trigger for stm32 adc 1475 * @indio_dev: IIO device 1476 * @trig: new trigger 1477 * 1478 * Returns: 0 if trig matches one of the triggers registered by stm32 adc 1479 * driver, -EINVAL otherwise. 1480 */ 1481 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, 1482 struct iio_trigger *trig) 1483 { 1484 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; 1485 } 1486 1487 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1488 { 1489 struct stm32_adc *adc = iio_priv(indio_dev); 1490 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2; 1491 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE; 1492 1493 /* 1494 * dma cyclic transfers are used, buffer is split into two periods. 1495 * There should be : 1496 * - always one buffer (period) dma is working on 1497 * - one buffer (period) driver can push data. 1498 */ 1499 watermark = min(watermark, val * (unsigned)(sizeof(u16))); 1500 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); 1501 1502 return 0; 1503 } 1504 1505 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, 1506 const unsigned long *scan_mask) 1507 { 1508 struct stm32_adc *adc = iio_priv(indio_dev); 1509 struct device *dev = indio_dev->dev.parent; 1510 int ret; 1511 1512 ret = pm_runtime_resume_and_get(dev); 1513 if (ret < 0) 1514 return ret; 1515 1516 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); 1517 1518 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask); 1519 pm_runtime_mark_last_busy(dev); 1520 pm_runtime_put_autosuspend(dev); 1521 1522 return ret; 1523 } 1524 1525 static int stm32_adc_fwnode_xlate(struct iio_dev *indio_dev, 1526 const struct fwnode_reference_args *iiospec) 1527 { 1528 int i; 1529 1530 for (i = 0; i < indio_dev->num_channels; i++) 1531 if (indio_dev->channels[i].channel == iiospec->args[0]) 1532 return i; 1533 1534 return -EINVAL; 1535 } 1536 1537 /** 1538 * stm32_adc_debugfs_reg_access - read or write register value 1539 * @indio_dev: IIO device structure 1540 * @reg: register offset 1541 * @writeval: value to write 1542 * @readval: value to read 1543 * 1544 * To read a value from an ADC register: 1545 * echo [ADC reg offset] > direct_reg_access 1546 * cat direct_reg_access 1547 * 1548 * To write a value in a ADC register: 1549 * echo [ADC_reg_offset] [value] > direct_reg_access 1550 */ 1551 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, 1552 unsigned reg, unsigned writeval, 1553 unsigned *readval) 1554 { 1555 struct stm32_adc *adc = iio_priv(indio_dev); 1556 struct device *dev = indio_dev->dev.parent; 1557 int ret; 1558 1559 ret = pm_runtime_resume_and_get(dev); 1560 if (ret < 0) 1561 return ret; 1562 1563 if (!readval) 1564 stm32_adc_writel(adc, reg, writeval); 1565 else 1566 *readval = stm32_adc_readl(adc, reg); 1567 1568 pm_runtime_mark_last_busy(dev); 1569 pm_runtime_put_autosuspend(dev); 1570 1571 return 0; 1572 } 1573 1574 static const struct iio_info stm32_adc_iio_info = { 1575 .read_raw = stm32_adc_read_raw, 1576 .validate_trigger = stm32_adc_validate_trigger, 1577 .hwfifo_set_watermark = stm32_adc_set_watermark, 1578 .update_scan_mode = stm32_adc_update_scan_mode, 1579 .debugfs_reg_access = stm32_adc_debugfs_reg_access, 1580 .fwnode_xlate = stm32_adc_fwnode_xlate, 1581 }; 1582 1583 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) 1584 { 1585 struct dma_tx_state state; 1586 enum dma_status status; 1587 1588 status = dmaengine_tx_status(adc->dma_chan, 1589 adc->dma_chan->cookie, 1590 &state); 1591 if (status == DMA_IN_PROGRESS) { 1592 /* Residue is size in bytes from end of buffer */ 1593 unsigned int i = adc->rx_buf_sz - state.residue; 1594 unsigned int size; 1595 1596 /* Return available bytes */ 1597 if (i >= adc->bufi) 1598 size = i - adc->bufi; 1599 else 1600 size = adc->rx_buf_sz + i - adc->bufi; 1601 1602 return size; 1603 } 1604 1605 return 0; 1606 } 1607 1608 static void stm32_adc_dma_buffer_done(void *data) 1609 { 1610 struct iio_dev *indio_dev = data; 1611 struct stm32_adc *adc = iio_priv(indio_dev); 1612 int residue = stm32_adc_dma_residue(adc); 1613 1614 /* 1615 * In DMA mode the trigger services of IIO are not used 1616 * (e.g. no call to iio_trigger_poll). 1617 * Calling irq handler associated to the hardware trigger is not 1618 * relevant as the conversions have already been done. Data 1619 * transfers are performed directly in DMA callback instead. 1620 * This implementation avoids to call trigger irq handler that 1621 * may sleep, in an atomic context (DMA irq handler context). 1622 */ 1623 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1624 1625 while (residue >= indio_dev->scan_bytes) { 1626 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1627 1628 iio_push_to_buffers(indio_dev, buffer); 1629 1630 residue -= indio_dev->scan_bytes; 1631 adc->bufi += indio_dev->scan_bytes; 1632 if (adc->bufi >= adc->rx_buf_sz) 1633 adc->bufi = 0; 1634 } 1635 } 1636 1637 static int stm32_adc_dma_start(struct iio_dev *indio_dev) 1638 { 1639 struct stm32_adc *adc = iio_priv(indio_dev); 1640 struct dma_async_tx_descriptor *desc; 1641 dma_cookie_t cookie; 1642 int ret; 1643 1644 if (!adc->dma_chan) 1645 return 0; 1646 1647 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 1648 adc->rx_buf_sz, adc->rx_buf_sz / 2); 1649 1650 /* Prepare a DMA cyclic transaction */ 1651 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 1652 adc->rx_dma_buf, 1653 adc->rx_buf_sz, adc->rx_buf_sz / 2, 1654 DMA_DEV_TO_MEM, 1655 DMA_PREP_INTERRUPT); 1656 if (!desc) 1657 return -EBUSY; 1658 1659 desc->callback = stm32_adc_dma_buffer_done; 1660 desc->callback_param = indio_dev; 1661 1662 cookie = dmaengine_submit(desc); 1663 ret = dma_submit_error(cookie); 1664 if (ret) { 1665 dmaengine_terminate_sync(adc->dma_chan); 1666 return ret; 1667 } 1668 1669 /* Issue pending DMA requests */ 1670 dma_async_issue_pending(adc->dma_chan); 1671 1672 return 0; 1673 } 1674 1675 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) 1676 { 1677 struct stm32_adc *adc = iio_priv(indio_dev); 1678 struct device *dev = indio_dev->dev.parent; 1679 int ret; 1680 1681 ret = pm_runtime_resume_and_get(dev); 1682 if (ret < 0) 1683 return ret; 1684 1685 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); 1686 if (ret) { 1687 dev_err(&indio_dev->dev, "Can't set trigger\n"); 1688 goto err_pm_put; 1689 } 1690 1691 ret = stm32_adc_dma_start(indio_dev); 1692 if (ret) { 1693 dev_err(&indio_dev->dev, "Can't start dma\n"); 1694 goto err_clr_trig; 1695 } 1696 1697 /* Reset adc buffer index */ 1698 adc->bufi = 0; 1699 1700 stm32_adc_ovr_irq_enable(adc); 1701 1702 if (!adc->dma_chan) 1703 stm32_adc_conv_irq_enable(adc); 1704 1705 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); 1706 1707 return 0; 1708 1709 err_clr_trig: 1710 stm32_adc_set_trig(indio_dev, NULL); 1711 err_pm_put: 1712 pm_runtime_mark_last_busy(dev); 1713 pm_runtime_put_autosuspend(dev); 1714 1715 return ret; 1716 } 1717 1718 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) 1719 { 1720 struct stm32_adc *adc = iio_priv(indio_dev); 1721 struct device *dev = indio_dev->dev.parent; 1722 1723 adc->cfg->stop_conv(indio_dev); 1724 if (!adc->dma_chan) 1725 stm32_adc_conv_irq_disable(adc); 1726 1727 stm32_adc_ovr_irq_disable(adc); 1728 1729 if (adc->dma_chan) 1730 dmaengine_terminate_sync(adc->dma_chan); 1731 1732 if (stm32_adc_set_trig(indio_dev, NULL)) 1733 dev_err(&indio_dev->dev, "Can't clear trigger\n"); 1734 1735 pm_runtime_mark_last_busy(dev); 1736 pm_runtime_put_autosuspend(dev); 1737 1738 return 0; 1739 } 1740 1741 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = { 1742 .postenable = &stm32_adc_buffer_postenable, 1743 .predisable = &stm32_adc_buffer_predisable, 1744 }; 1745 1746 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) 1747 { 1748 struct iio_poll_func *pf = p; 1749 struct iio_dev *indio_dev = pf->indio_dev; 1750 struct stm32_adc *adc = iio_priv(indio_dev); 1751 1752 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1753 1754 /* reset buffer index */ 1755 adc->bufi = 0; 1756 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, 1757 pf->timestamp); 1758 iio_trigger_notify_done(indio_dev->trig); 1759 1760 /* re-enable eoc irq */ 1761 stm32_adc_conv_irq_enable(adc); 1762 1763 return IRQ_HANDLED; 1764 } 1765 1766 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = { 1767 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), 1768 { 1769 .name = "trigger_polarity_available", 1770 .shared = IIO_SHARED_BY_ALL, 1771 .read = iio_enum_available_read, 1772 .private = (uintptr_t)&stm32_adc_trig_pol, 1773 }, 1774 {}, 1775 }; 1776 1777 static int stm32_adc_fw_get_resolution(struct iio_dev *indio_dev) 1778 { 1779 struct device *dev = &indio_dev->dev; 1780 struct stm32_adc *adc = iio_priv(indio_dev); 1781 unsigned int i; 1782 u32 res; 1783 1784 if (device_property_read_u32(dev, "assigned-resolution-bits", &res)) 1785 res = adc->cfg->adc_info->resolutions[0]; 1786 1787 for (i = 0; i < adc->cfg->adc_info->num_res; i++) 1788 if (res == adc->cfg->adc_info->resolutions[i]) 1789 break; 1790 if (i >= adc->cfg->adc_info->num_res) { 1791 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); 1792 return -EINVAL; 1793 } 1794 1795 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); 1796 adc->res = i; 1797 1798 return 0; 1799 } 1800 1801 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) 1802 { 1803 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; 1804 u32 period_ns, shift = smpr->shift, mask = smpr->mask; 1805 unsigned int smp, r = smpr->reg; 1806 1807 /* 1808 * For vrefint channel, ensure that the sampling time cannot 1809 * be lower than the one specified in the datasheet 1810 */ 1811 if (channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) 1812 smp_ns = max(smp_ns, adc->cfg->ts_vrefint_ns); 1813 1814 /* Determine sampling time (ADC clock cycles) */ 1815 period_ns = NSEC_PER_SEC / adc->common->rate; 1816 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++) 1817 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) 1818 break; 1819 if (smp > STM32_ADC_MAX_SMP) 1820 smp = STM32_ADC_MAX_SMP; 1821 1822 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ 1823 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); 1824 } 1825 1826 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, 1827 struct iio_chan_spec *chan, u32 vinp, 1828 u32 vinn, int scan_index, bool differential) 1829 { 1830 struct stm32_adc *adc = iio_priv(indio_dev); 1831 char *name = adc->chan_name[vinp]; 1832 1833 chan->type = IIO_VOLTAGE; 1834 chan->channel = vinp; 1835 if (differential) { 1836 chan->differential = 1; 1837 chan->channel2 = vinn; 1838 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); 1839 } else { 1840 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp); 1841 } 1842 chan->datasheet_name = name; 1843 chan->scan_index = scan_index; 1844 chan->indexed = 1; 1845 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) 1846 chan->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); 1847 else 1848 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 1849 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 1850 BIT(IIO_CHAN_INFO_OFFSET); 1851 chan->scan_type.sign = 'u'; 1852 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; 1853 chan->scan_type.storagebits = 16; 1854 chan->ext_info = stm32_adc_ext_info; 1855 1856 /* pre-build selected channels mask */ 1857 adc->pcsel |= BIT(chan->channel); 1858 if (differential) { 1859 /* pre-build diff channels mask */ 1860 adc->difsel |= BIT(chan->channel); 1861 /* Also add negative input to pre-selected channels */ 1862 adc->pcsel |= BIT(chan->channel2); 1863 } 1864 } 1865 1866 static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) 1867 { 1868 struct device *dev = &indio_dev->dev; 1869 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 1870 int num_channels = 0, ret; 1871 1872 ret = device_property_count_u32(dev, "st,adc-channels"); 1873 if (ret > adc_info->max_channels) { 1874 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); 1875 return -EINVAL; 1876 } else if (ret > 0) { 1877 num_channels += ret; 1878 } 1879 1880 /* 1881 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret 1882 * to get the *real* number of channels. 1883 */ 1884 ret = device_property_count_u32(dev, "st,adc-diff-channels"); 1885 if (ret < 0) 1886 return ret; 1887 1888 ret /= (int)(sizeof(struct stm32_adc_diff_channel) / sizeof(u32)); 1889 if (ret > adc_info->max_channels) { 1890 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); 1891 return -EINVAL; 1892 } else if (ret > 0) { 1893 adc->num_diff = ret; 1894 num_channels += ret; 1895 } 1896 1897 /* Optional sample time is provided either for each, or all channels */ 1898 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs"); 1899 if (adc->nsmps > 1 && adc->nsmps != num_channels) { 1900 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); 1901 return -EINVAL; 1902 } 1903 1904 return num_channels; 1905 } 1906 1907 static int stm32_adc_legacy_chan_init(struct iio_dev *indio_dev, 1908 struct stm32_adc *adc, 1909 struct iio_chan_spec *channels, 1910 int nchans) 1911 { 1912 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 1913 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; 1914 struct device *dev = &indio_dev->dev; 1915 u32 num_diff = adc->num_diff; 1916 int size = num_diff * sizeof(*diff) / sizeof(u32); 1917 int scan_index = 0, ret, i, c; 1918 u32 smp = 0, smps[STM32_ADC_CH_MAX], chans[STM32_ADC_CH_MAX]; 1919 1920 if (num_diff) { 1921 ret = device_property_read_u32_array(dev, "st,adc-diff-channels", 1922 (u32 *)diff, size); 1923 if (ret) { 1924 dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret); 1925 return ret; 1926 } 1927 1928 for (i = 0; i < num_diff; i++) { 1929 if (diff[i].vinp >= adc_info->max_channels || 1930 diff[i].vinn >= adc_info->max_channels) { 1931 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 1932 diff[i].vinp, diff[i].vinn); 1933 return -EINVAL; 1934 } 1935 1936 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 1937 diff[i].vinp, diff[i].vinn, 1938 scan_index, true); 1939 scan_index++; 1940 } 1941 } 1942 1943 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, 1944 nchans); 1945 if (ret) 1946 return ret; 1947 1948 for (c = 0; c < nchans; c++) { 1949 if (chans[c] >= adc_info->max_channels) { 1950 dev_err(&indio_dev->dev, "Invalid channel %d\n", 1951 chans[c]); 1952 return -EINVAL; 1953 } 1954 1955 /* Channel can't be configured both as single-ended & diff */ 1956 for (i = 0; i < num_diff; i++) { 1957 if (chans[c] == diff[i].vinp) { 1958 dev_err(&indio_dev->dev, "channel %d misconfigured\n", chans[c]); 1959 return -EINVAL; 1960 } 1961 } 1962 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 1963 chans[c], 0, scan_index, false); 1964 scan_index++; 1965 } 1966 1967 if (adc->nsmps > 0) { 1968 ret = device_property_read_u32_array(dev, "st,min-sample-time-nsecs", 1969 smps, adc->nsmps); 1970 if (ret) 1971 return ret; 1972 } 1973 1974 for (i = 0; i < scan_index; i++) { 1975 /* 1976 * This check is used with the above logic so that smp value 1977 * will only be modified if valid u32 value can be decoded. This 1978 * allows to get either no value, 1 shared value for all indexes, 1979 * or one value per channel. The point is to have the same 1980 * behavior as 'of_property_read_u32_index()'. 1981 */ 1982 if (i < adc->nsmps) 1983 smp = smps[i]; 1984 1985 /* Prepare sampling time settings */ 1986 stm32_adc_smpr_init(adc, channels[i].channel, smp); 1987 } 1988 1989 return scan_index; 1990 } 1991 1992 static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_name, 1993 int chan) 1994 { 1995 struct stm32_adc *adc = iio_priv(indio_dev); 1996 u16 vrefint; 1997 int i, ret; 1998 1999 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 2000 if (!strncmp(stm32_adc_ic[i].name, ch_name, STM32_ADC_CH_SZ)) { 2001 if (stm32_adc_ic[i].idx != STM32_ADC_INT_CH_VREFINT) { 2002 adc->int_ch[i] = chan; 2003 break; 2004 } 2005 2006 /* Get calibration data for vrefint channel */ 2007 ret = nvmem_cell_read_u16(&indio_dev->dev, "vrefint", &vrefint); 2008 if (ret && ret != -ENOENT) { 2009 return dev_err_probe(indio_dev->dev.parent, ret, 2010 "nvmem access error\n"); 2011 } 2012 if (ret == -ENOENT) { 2013 dev_dbg(&indio_dev->dev, "vrefint calibration not found. Skip vrefint channel\n"); 2014 return ret; 2015 } else if (!vrefint) { 2016 dev_dbg(&indio_dev->dev, "Null vrefint calibration value. Skip vrefint channel\n"); 2017 return -ENOENT; 2018 } 2019 adc->int_ch[i] = chan; 2020 adc->vrefint.vrefint_cal = vrefint; 2021 } 2022 } 2023 2024 return 0; 2025 } 2026 2027 static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev, 2028 struct stm32_adc *adc, 2029 struct iio_chan_spec *channels) 2030 { 2031 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2032 struct fwnode_handle *child; 2033 const char *name; 2034 int val, scan_index = 0, ret; 2035 bool differential; 2036 u32 vin[2]; 2037 2038 device_for_each_child_node(&indio_dev->dev, child) { 2039 ret = fwnode_property_read_u32(child, "reg", &val); 2040 if (ret) { 2041 dev_err(&indio_dev->dev, "Missing channel index %d\n", ret); 2042 goto err; 2043 } 2044 2045 ret = fwnode_property_read_string(child, "label", &name); 2046 /* label is optional */ 2047 if (!ret) { 2048 if (strlen(name) >= STM32_ADC_CH_SZ) { 2049 dev_err(&indio_dev->dev, "Label %s exceeds %d characters\n", 2050 name, STM32_ADC_CH_SZ); 2051 ret = -EINVAL; 2052 goto err; 2053 } 2054 strncpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); 2055 ret = stm32_adc_populate_int_ch(indio_dev, name, val); 2056 if (ret == -ENOENT) 2057 continue; 2058 else if (ret) 2059 goto err; 2060 } else if (ret != -EINVAL) { 2061 dev_err(&indio_dev->dev, "Invalid label %d\n", ret); 2062 goto err; 2063 } 2064 2065 if (val >= adc_info->max_channels) { 2066 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); 2067 ret = -EINVAL; 2068 goto err; 2069 } 2070 2071 differential = false; 2072 ret = fwnode_property_read_u32_array(child, "diff-channels", vin, 2); 2073 /* diff-channels is optional */ 2074 if (!ret) { 2075 differential = true; 2076 if (vin[0] != val || vin[1] >= adc_info->max_channels) { 2077 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 2078 vin[0], vin[1]); 2079 goto err; 2080 } 2081 } else if (ret != -EINVAL) { 2082 dev_err(&indio_dev->dev, "Invalid diff-channels property %d\n", ret); 2083 goto err; 2084 } 2085 2086 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 2087 vin[1], scan_index, differential); 2088 2089 ret = fwnode_property_read_u32(child, "st,min-sample-time-ns", &val); 2090 /* st,min-sample-time-ns is optional */ 2091 if (!ret) { 2092 stm32_adc_smpr_init(adc, channels[scan_index].channel, val); 2093 if (differential) 2094 stm32_adc_smpr_init(adc, vin[1], val); 2095 } else if (ret != -EINVAL) { 2096 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-ns property %d\n", 2097 ret); 2098 goto err; 2099 } 2100 2101 scan_index++; 2102 } 2103 2104 return scan_index; 2105 2106 err: 2107 fwnode_handle_put(child); 2108 2109 return ret; 2110 } 2111 2112 static int stm32_adc_chan_fw_init(struct iio_dev *indio_dev, bool timestamping) 2113 { 2114 struct stm32_adc *adc = iio_priv(indio_dev); 2115 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2116 struct iio_chan_spec *channels; 2117 int scan_index = 0, num_channels = 0, ret, i; 2118 bool legacy = false; 2119 2120 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) 2121 adc->int_ch[i] = STM32_ADC_INT_CH_NONE; 2122 2123 num_channels = device_get_child_node_count(&indio_dev->dev); 2124 /* If no channels have been found, fallback to channels legacy properties. */ 2125 if (!num_channels) { 2126 legacy = true; 2127 2128 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); 2129 if (!ret) { 2130 dev_err(indio_dev->dev.parent, "No channel found\n"); 2131 return -ENODATA; 2132 } else if (ret < 0) { 2133 return ret; 2134 } 2135 2136 num_channels = ret; 2137 } 2138 2139 if (num_channels > adc_info->max_channels) { 2140 dev_err(&indio_dev->dev, "Channel number [%d] exceeds %d\n", 2141 num_channels, adc_info->max_channels); 2142 return -EINVAL; 2143 } 2144 2145 if (timestamping) 2146 num_channels++; 2147 2148 channels = devm_kcalloc(&indio_dev->dev, num_channels, 2149 sizeof(struct iio_chan_spec), GFP_KERNEL); 2150 if (!channels) 2151 return -ENOMEM; 2152 2153 if (legacy) 2154 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels, 2155 num_channels); 2156 else 2157 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); 2158 if (ret < 0) 2159 return ret; 2160 scan_index = ret; 2161 2162 if (timestamping) { 2163 struct iio_chan_spec *timestamp = &channels[scan_index]; 2164 2165 timestamp->type = IIO_TIMESTAMP; 2166 timestamp->channel = -1; 2167 timestamp->scan_index = scan_index; 2168 timestamp->scan_type.sign = 's'; 2169 timestamp->scan_type.realbits = 64; 2170 timestamp->scan_type.storagebits = 64; 2171 2172 scan_index++; 2173 } 2174 2175 indio_dev->num_channels = scan_index; 2176 indio_dev->channels = channels; 2177 2178 return 0; 2179 } 2180 2181 static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev) 2182 { 2183 struct stm32_adc *adc = iio_priv(indio_dev); 2184 struct dma_slave_config config; 2185 int ret; 2186 2187 adc->dma_chan = dma_request_chan(dev, "rx"); 2188 if (IS_ERR(adc->dma_chan)) { 2189 ret = PTR_ERR(adc->dma_chan); 2190 if (ret != -ENODEV) 2191 return dev_err_probe(dev, ret, 2192 "DMA channel request failed with\n"); 2193 2194 /* DMA is optional: fall back to IRQ mode */ 2195 adc->dma_chan = NULL; 2196 return 0; 2197 } 2198 2199 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 2200 STM32_DMA_BUFFER_SIZE, 2201 &adc->rx_dma_buf, GFP_KERNEL); 2202 if (!adc->rx_buf) { 2203 ret = -ENOMEM; 2204 goto err_release; 2205 } 2206 2207 /* Configure DMA channel to read data register */ 2208 memset(&config, 0, sizeof(config)); 2209 config.src_addr = (dma_addr_t)adc->common->phys_base; 2210 config.src_addr += adc->offset + adc->cfg->regs->dr; 2211 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 2212 2213 ret = dmaengine_slave_config(adc->dma_chan, &config); 2214 if (ret) 2215 goto err_free; 2216 2217 return 0; 2218 2219 err_free: 2220 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, 2221 adc->rx_buf, adc->rx_dma_buf); 2222 err_release: 2223 dma_release_channel(adc->dma_chan); 2224 2225 return ret; 2226 } 2227 2228 static int stm32_adc_probe(struct platform_device *pdev) 2229 { 2230 struct iio_dev *indio_dev; 2231 struct device *dev = &pdev->dev; 2232 irqreturn_t (*handler)(int irq, void *p) = NULL; 2233 struct stm32_adc *adc; 2234 bool timestamping = false; 2235 int ret; 2236 2237 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 2238 if (!indio_dev) 2239 return -ENOMEM; 2240 2241 adc = iio_priv(indio_dev); 2242 adc->common = dev_get_drvdata(pdev->dev.parent); 2243 spin_lock_init(&adc->lock); 2244 init_completion(&adc->completion); 2245 adc->cfg = device_get_match_data(dev); 2246 2247 indio_dev->name = dev_name(&pdev->dev); 2248 device_set_node(&indio_dev->dev, dev_fwnode(&pdev->dev)); 2249 indio_dev->info = &stm32_adc_iio_info; 2250 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; 2251 2252 platform_set_drvdata(pdev, indio_dev); 2253 2254 ret = device_property_read_u32(dev, "reg", &adc->offset); 2255 if (ret != 0) { 2256 dev_err(&pdev->dev, "missing reg property\n"); 2257 return -EINVAL; 2258 } 2259 2260 adc->irq = platform_get_irq(pdev, 0); 2261 if (adc->irq < 0) 2262 return adc->irq; 2263 2264 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, 2265 stm32_adc_threaded_isr, 2266 0, pdev->name, indio_dev); 2267 if (ret) { 2268 dev_err(&pdev->dev, "failed to request IRQ\n"); 2269 return ret; 2270 } 2271 2272 adc->clk = devm_clk_get(&pdev->dev, NULL); 2273 if (IS_ERR(adc->clk)) { 2274 ret = PTR_ERR(adc->clk); 2275 if (ret == -ENOENT && !adc->cfg->clk_required) { 2276 adc->clk = NULL; 2277 } else { 2278 dev_err(&pdev->dev, "Can't get clock\n"); 2279 return ret; 2280 } 2281 } 2282 2283 ret = stm32_adc_fw_get_resolution(indio_dev); 2284 if (ret < 0) 2285 return ret; 2286 2287 ret = stm32_adc_dma_request(dev, indio_dev); 2288 if (ret < 0) 2289 return ret; 2290 2291 if (!adc->dma_chan) { 2292 /* For PIO mode only, iio_pollfunc_store_time stores a timestamp 2293 * in the primary trigger IRQ handler and stm32_adc_trigger_handler 2294 * runs in the IRQ thread to push out buffer along with timestamp. 2295 */ 2296 handler = &stm32_adc_trigger_handler; 2297 timestamping = true; 2298 } 2299 2300 ret = stm32_adc_chan_fw_init(indio_dev, timestamping); 2301 if (ret < 0) 2302 goto err_dma_disable; 2303 2304 ret = iio_triggered_buffer_setup(indio_dev, 2305 &iio_pollfunc_store_time, handler, 2306 &stm32_adc_buffer_setup_ops); 2307 if (ret) { 2308 dev_err(&pdev->dev, "buffer setup failed\n"); 2309 goto err_dma_disable; 2310 } 2311 2312 /* Get stm32-adc-core PM online */ 2313 pm_runtime_get_noresume(dev); 2314 pm_runtime_set_active(dev); 2315 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS); 2316 pm_runtime_use_autosuspend(dev); 2317 pm_runtime_enable(dev); 2318 2319 ret = stm32_adc_hw_start(dev); 2320 if (ret) 2321 goto err_buffer_cleanup; 2322 2323 ret = iio_device_register(indio_dev); 2324 if (ret) { 2325 dev_err(&pdev->dev, "iio dev register failed\n"); 2326 goto err_hw_stop; 2327 } 2328 2329 pm_runtime_mark_last_busy(dev); 2330 pm_runtime_put_autosuspend(dev); 2331 2332 return 0; 2333 2334 err_hw_stop: 2335 stm32_adc_hw_stop(dev); 2336 2337 err_buffer_cleanup: 2338 pm_runtime_disable(dev); 2339 pm_runtime_set_suspended(dev); 2340 pm_runtime_put_noidle(dev); 2341 iio_triggered_buffer_cleanup(indio_dev); 2342 2343 err_dma_disable: 2344 if (adc->dma_chan) { 2345 dma_free_coherent(adc->dma_chan->device->dev, 2346 STM32_DMA_BUFFER_SIZE, 2347 adc->rx_buf, adc->rx_dma_buf); 2348 dma_release_channel(adc->dma_chan); 2349 } 2350 2351 return ret; 2352 } 2353 2354 static int stm32_adc_remove(struct platform_device *pdev) 2355 { 2356 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2357 struct stm32_adc *adc = iio_priv(indio_dev); 2358 2359 pm_runtime_get_sync(&pdev->dev); 2360 iio_device_unregister(indio_dev); 2361 stm32_adc_hw_stop(&pdev->dev); 2362 pm_runtime_disable(&pdev->dev); 2363 pm_runtime_set_suspended(&pdev->dev); 2364 pm_runtime_put_noidle(&pdev->dev); 2365 iio_triggered_buffer_cleanup(indio_dev); 2366 if (adc->dma_chan) { 2367 dma_free_coherent(adc->dma_chan->device->dev, 2368 STM32_DMA_BUFFER_SIZE, 2369 adc->rx_buf, adc->rx_dma_buf); 2370 dma_release_channel(adc->dma_chan); 2371 } 2372 2373 return 0; 2374 } 2375 2376 static int stm32_adc_suspend(struct device *dev) 2377 { 2378 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2379 2380 if (iio_buffer_enabled(indio_dev)) 2381 stm32_adc_buffer_predisable(indio_dev); 2382 2383 return pm_runtime_force_suspend(dev); 2384 } 2385 2386 static int stm32_adc_resume(struct device *dev) 2387 { 2388 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2389 int ret; 2390 2391 ret = pm_runtime_force_resume(dev); 2392 if (ret < 0) 2393 return ret; 2394 2395 if (!iio_buffer_enabled(indio_dev)) 2396 return 0; 2397 2398 ret = stm32_adc_update_scan_mode(indio_dev, 2399 indio_dev->active_scan_mask); 2400 if (ret < 0) 2401 return ret; 2402 2403 return stm32_adc_buffer_postenable(indio_dev); 2404 } 2405 2406 static int stm32_adc_runtime_suspend(struct device *dev) 2407 { 2408 return stm32_adc_hw_stop(dev); 2409 } 2410 2411 static int stm32_adc_runtime_resume(struct device *dev) 2412 { 2413 return stm32_adc_hw_start(dev); 2414 } 2415 2416 static const struct dev_pm_ops stm32_adc_pm_ops = { 2417 SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume) 2418 RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume, 2419 NULL) 2420 }; 2421 2422 static const struct stm32_adc_cfg stm32f4_adc_cfg = { 2423 .regs = &stm32f4_adc_regspec, 2424 .adc_info = &stm32f4_adc_info, 2425 .trigs = stm32f4_adc_trigs, 2426 .clk_required = true, 2427 .start_conv = stm32f4_adc_start_conv, 2428 .stop_conv = stm32f4_adc_stop_conv, 2429 .smp_cycles = stm32f4_adc_smp_cycles, 2430 .irq_clear = stm32f4_adc_irq_clear, 2431 }; 2432 2433 static const struct stm32_adc_cfg stm32h7_adc_cfg = { 2434 .regs = &stm32h7_adc_regspec, 2435 .adc_info = &stm32h7_adc_info, 2436 .trigs = stm32h7_adc_trigs, 2437 .start_conv = stm32h7_adc_start_conv, 2438 .stop_conv = stm32h7_adc_stop_conv, 2439 .prepare = stm32h7_adc_prepare, 2440 .unprepare = stm32h7_adc_unprepare, 2441 .smp_cycles = stm32h7_adc_smp_cycles, 2442 .irq_clear = stm32h7_adc_irq_clear, 2443 }; 2444 2445 static const struct stm32_adc_cfg stm32mp1_adc_cfg = { 2446 .regs = &stm32mp1_adc_regspec, 2447 .adc_info = &stm32h7_adc_info, 2448 .trigs = stm32h7_adc_trigs, 2449 .has_vregready = true, 2450 .start_conv = stm32h7_adc_start_conv, 2451 .stop_conv = stm32h7_adc_stop_conv, 2452 .prepare = stm32h7_adc_prepare, 2453 .unprepare = stm32h7_adc_unprepare, 2454 .smp_cycles = stm32h7_adc_smp_cycles, 2455 .irq_clear = stm32h7_adc_irq_clear, 2456 .ts_vrefint_ns = 4300, 2457 }; 2458 2459 static const struct of_device_id stm32_adc_of_match[] = { 2460 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, 2461 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, 2462 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg }, 2463 {}, 2464 }; 2465 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 2466 2467 static struct platform_driver stm32_adc_driver = { 2468 .probe = stm32_adc_probe, 2469 .remove = stm32_adc_remove, 2470 .driver = { 2471 .name = "stm32-adc", 2472 .of_match_table = stm32_adc_of_match, 2473 .pm = pm_ptr(&stm32_adc_pm_ops), 2474 }, 2475 }; 2476 module_platform_driver(stm32_adc_driver); 2477 2478 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 2479 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver"); 2480 MODULE_LICENSE("GPL v2"); 2481 MODULE_ALIAS("platform:stm32-adc"); 2482