1 /* 2 * This file is part of STM32 ADC driver 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 6 * 7 * License type: GPLv2 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. 16 * See the GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmaengine.h> 26 #include <linux/iio/iio.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/timer/stm32-timer-trigger.h> 29 #include <linux/iio/trigger.h> 30 #include <linux/iio/trigger_consumer.h> 31 #include <linux/iio/triggered_buffer.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/module.h> 35 #include <linux/platform_device.h> 36 #include <linux/of.h> 37 38 #include "stm32-adc-core.h" 39 40 /* STM32F4 - Registers for each ADC instance */ 41 #define STM32F4_ADC_SR 0x00 42 #define STM32F4_ADC_CR1 0x04 43 #define STM32F4_ADC_CR2 0x08 44 #define STM32F4_ADC_SMPR1 0x0C 45 #define STM32F4_ADC_SMPR2 0x10 46 #define STM32F4_ADC_HTR 0x24 47 #define STM32F4_ADC_LTR 0x28 48 #define STM32F4_ADC_SQR1 0x2C 49 #define STM32F4_ADC_SQR2 0x30 50 #define STM32F4_ADC_SQR3 0x34 51 #define STM32F4_ADC_JSQR 0x38 52 #define STM32F4_ADC_JDR1 0x3C 53 #define STM32F4_ADC_JDR2 0x40 54 #define STM32F4_ADC_JDR3 0x44 55 #define STM32F4_ADC_JDR4 0x48 56 #define STM32F4_ADC_DR 0x4C 57 58 /* STM32F4_ADC_SR - bit fields */ 59 #define STM32F4_STRT BIT(4) 60 #define STM32F4_EOC BIT(1) 61 62 /* STM32F4_ADC_CR1 - bit fields */ 63 #define STM32F4_SCAN BIT(8) 64 #define STM32F4_EOCIE BIT(5) 65 66 /* STM32F4_ADC_CR2 - bit fields */ 67 #define STM32F4_SWSTART BIT(30) 68 #define STM32F4_EXTEN_SHIFT 28 69 #define STM32F4_EXTEN_MASK GENMASK(29, 28) 70 #define STM32F4_EXTSEL_SHIFT 24 71 #define STM32F4_EXTSEL_MASK GENMASK(27, 24) 72 #define STM32F4_EOCS BIT(10) 73 #define STM32F4_DDS BIT(9) 74 #define STM32F4_DMA BIT(8) 75 #define STM32F4_ADON BIT(0) 76 77 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ 78 #define STM32_ADC_TIMEOUT_US 100000 79 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) 80 81 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE 82 83 /* External trigger enable */ 84 enum stm32_adc_exten { 85 STM32_EXTEN_SWTRIG, 86 STM32_EXTEN_HWTRIG_RISING_EDGE, 87 STM32_EXTEN_HWTRIG_FALLING_EDGE, 88 STM32_EXTEN_HWTRIG_BOTH_EDGES, 89 }; 90 91 /* extsel - trigger mux selection value */ 92 enum stm32_adc_extsel { 93 STM32_EXT0, 94 STM32_EXT1, 95 STM32_EXT2, 96 STM32_EXT3, 97 STM32_EXT4, 98 STM32_EXT5, 99 STM32_EXT6, 100 STM32_EXT7, 101 STM32_EXT8, 102 STM32_EXT9, 103 STM32_EXT10, 104 STM32_EXT11, 105 STM32_EXT12, 106 STM32_EXT13, 107 STM32_EXT14, 108 STM32_EXT15, 109 }; 110 111 /** 112 * struct stm32_adc_trig_info - ADC trigger info 113 * @name: name of the trigger, corresponding to its source 114 * @extsel: trigger selection 115 */ 116 struct stm32_adc_trig_info { 117 const char *name; 118 enum stm32_adc_extsel extsel; 119 }; 120 121 /** 122 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc 123 * @reg: register offset 124 * @mask: bitfield mask 125 * @shift: left shift 126 */ 127 struct stm32_adc_regs { 128 int reg; 129 int mask; 130 int shift; 131 }; 132 133 /** 134 * struct stm32_adc - private data of each ADC IIO instance 135 * @common: reference to ADC block common data 136 * @offset: ADC instance register offset in ADC block 137 * @completion: end of single conversion completion 138 * @buffer: data buffer 139 * @clk: clock for this adc instance 140 * @irq: interrupt for this adc instance 141 * @lock: spinlock 142 * @bufi: data buffer index 143 * @num_conv: expected number of scan conversions 144 * @trigger_polarity: external trigger polarity (e.g. exten) 145 * @dma_chan: dma channel 146 * @rx_buf: dma rx buffer cpu address 147 * @rx_dma_buf: dma rx buffer bus address 148 * @rx_buf_sz: dma rx buffer size 149 */ 150 struct stm32_adc { 151 struct stm32_adc_common *common; 152 u32 offset; 153 struct completion completion; 154 u16 buffer[STM32_ADC_MAX_SQ]; 155 struct clk *clk; 156 int irq; 157 spinlock_t lock; /* interrupt lock */ 158 unsigned int bufi; 159 unsigned int num_conv; 160 u32 trigger_polarity; 161 struct dma_chan *dma_chan; 162 u8 *rx_buf; 163 dma_addr_t rx_dma_buf; 164 unsigned int rx_buf_sz; 165 }; 166 167 /** 168 * struct stm32_adc_chan_spec - specification of stm32 adc channel 169 * @type: IIO channel type 170 * @channel: channel number (single ended) 171 * @name: channel name (single ended) 172 */ 173 struct stm32_adc_chan_spec { 174 enum iio_chan_type type; 175 int channel; 176 const char *name; 177 }; 178 179 /* Input definitions common for all STM32F4 instances */ 180 static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = { 181 { IIO_VOLTAGE, 0, "in0" }, 182 { IIO_VOLTAGE, 1, "in1" }, 183 { IIO_VOLTAGE, 2, "in2" }, 184 { IIO_VOLTAGE, 3, "in3" }, 185 { IIO_VOLTAGE, 4, "in4" }, 186 { IIO_VOLTAGE, 5, "in5" }, 187 { IIO_VOLTAGE, 6, "in6" }, 188 { IIO_VOLTAGE, 7, "in7" }, 189 { IIO_VOLTAGE, 8, "in8" }, 190 { IIO_VOLTAGE, 9, "in9" }, 191 { IIO_VOLTAGE, 10, "in10" }, 192 { IIO_VOLTAGE, 11, "in11" }, 193 { IIO_VOLTAGE, 12, "in12" }, 194 { IIO_VOLTAGE, 13, "in13" }, 195 { IIO_VOLTAGE, 14, "in14" }, 196 { IIO_VOLTAGE, 15, "in15" }, 197 }; 198 199 /** 200 * stm32f4_sq - describe regular sequence registers 201 * - L: sequence len (register & bit field) 202 * - SQ1..SQ16: sequence entries (register & bit field) 203 */ 204 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = { 205 /* L: len bit field description to be kept as first element */ 206 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 }, 207 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 208 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 }, 209 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 }, 210 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 }, 211 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 }, 212 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 }, 213 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 }, 214 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 }, 215 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 }, 216 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 }, 217 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 }, 218 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 }, 219 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 }, 220 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 }, 221 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 }, 222 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 }, 223 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 }, 224 }; 225 226 /* STM32F4 external trigger sources for all instances */ 227 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 228 { TIM1_CH1, STM32_EXT0 }, 229 { TIM1_CH2, STM32_EXT1 }, 230 { TIM1_CH3, STM32_EXT2 }, 231 { TIM2_CH2, STM32_EXT3 }, 232 { TIM2_CH3, STM32_EXT4 }, 233 { TIM2_CH4, STM32_EXT5 }, 234 { TIM2_TRGO, STM32_EXT6 }, 235 { TIM3_CH1, STM32_EXT7 }, 236 { TIM3_TRGO, STM32_EXT8 }, 237 { TIM4_CH4, STM32_EXT9 }, 238 { TIM5_CH1, STM32_EXT10 }, 239 { TIM5_CH2, STM32_EXT11 }, 240 { TIM5_CH3, STM32_EXT12 }, 241 { TIM8_CH1, STM32_EXT13 }, 242 { TIM8_TRGO, STM32_EXT14 }, 243 {}, /* sentinel */ 244 }; 245 246 /** 247 * STM32 ADC registers access routines 248 * @adc: stm32 adc instance 249 * @reg: reg offset in adc instance 250 * 251 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. 252 * for adc1, adc2 and adc3. 253 */ 254 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) 255 { 256 return readl_relaxed(adc->common->base + adc->offset + reg); 257 } 258 259 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) 260 { 261 return readw_relaxed(adc->common->base + adc->offset + reg); 262 } 263 264 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) 265 { 266 writel_relaxed(val, adc->common->base + adc->offset + reg); 267 } 268 269 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) 270 { 271 unsigned long flags; 272 273 spin_lock_irqsave(&adc->lock, flags); 274 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); 275 spin_unlock_irqrestore(&adc->lock, flags); 276 } 277 278 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) 279 { 280 unsigned long flags; 281 282 spin_lock_irqsave(&adc->lock, flags); 283 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); 284 spin_unlock_irqrestore(&adc->lock, flags); 285 } 286 287 /** 288 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt 289 * @adc: stm32 adc instance 290 */ 291 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) 292 { 293 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE); 294 }; 295 296 /** 297 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt 298 * @adc: stm32 adc instance 299 */ 300 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) 301 { 302 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE); 303 } 304 305 /** 306 * stm32_adc_start_conv() - Start conversions for regular channels. 307 * @adc: stm32 adc instance 308 * @dma: use dma to transfer conversion result 309 * 310 * Start conversions for regular channels. 311 * Also take care of normal or DMA mode. Circular DMA may be used for regular 312 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct 313 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). 314 */ 315 static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma) 316 { 317 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 318 319 if (dma) 320 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, 321 STM32F4_DMA | STM32F4_DDS); 322 323 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); 324 325 /* Wait for Power-up time (tSTAB from datasheet) */ 326 usleep_range(2, 3); 327 328 /* Software start ? (e.g. trigger detection disabled ?) */ 329 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) 330 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); 331 } 332 333 static void stm32_adc_stop_conv(struct stm32_adc *adc) 334 { 335 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 336 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); 337 338 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 339 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, 340 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); 341 } 342 343 /** 344 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence 345 * @indio_dev: IIO device 346 * @scan_mask: channels to be converted 347 * 348 * Conversion sequence : 349 * Configure ADC scan sequence based on selected channels in scan_mask. 350 * Add channels to SQR registers, from scan_mask LSB to MSB, then 351 * program sequence len. 352 */ 353 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, 354 const unsigned long *scan_mask) 355 { 356 struct stm32_adc *adc = iio_priv(indio_dev); 357 const struct iio_chan_spec *chan; 358 u32 val, bit; 359 int i = 0; 360 361 for_each_set_bit(bit, scan_mask, indio_dev->masklength) { 362 chan = indio_dev->channels + bit; 363 /* 364 * Assign one channel per SQ entry in regular 365 * sequence, starting with SQ1. 366 */ 367 i++; 368 if (i > STM32_ADC_MAX_SQ) 369 return -EINVAL; 370 371 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", 372 __func__, chan->channel, i); 373 374 val = stm32_adc_readl(adc, stm32f4_sq[i].reg); 375 val &= ~stm32f4_sq[i].mask; 376 val |= chan->channel << stm32f4_sq[i].shift; 377 stm32_adc_writel(adc, stm32f4_sq[i].reg, val); 378 } 379 380 if (!i) 381 return -EINVAL; 382 383 /* Sequence len */ 384 val = stm32_adc_readl(adc, stm32f4_sq[0].reg); 385 val &= ~stm32f4_sq[0].mask; 386 val |= ((i - 1) << stm32f4_sq[0].shift); 387 stm32_adc_writel(adc, stm32f4_sq[0].reg, val); 388 389 return 0; 390 } 391 392 /** 393 * stm32_adc_get_trig_extsel() - Get external trigger selection 394 * @trig: trigger 395 * 396 * Returns trigger extsel value, if trig matches, -EINVAL otherwise. 397 */ 398 static int stm32_adc_get_trig_extsel(struct iio_trigger *trig) 399 { 400 int i; 401 402 /* lookup triggers registered by stm32 timer trigger driver */ 403 for (i = 0; stm32f4_adc_trigs[i].name; i++) { 404 /** 405 * Checking both stm32 timer trigger type and trig name 406 * should be safe against arbitrary trigger names. 407 */ 408 if (is_stm32_timer_trigger(trig) && 409 !strcmp(stm32f4_adc_trigs[i].name, trig->name)) { 410 return stm32f4_adc_trigs[i].extsel; 411 } 412 } 413 414 return -EINVAL; 415 } 416 417 /** 418 * stm32_adc_set_trig() - Set a regular trigger 419 * @indio_dev: IIO device 420 * @trig: IIO trigger 421 * 422 * Set trigger source/polarity (e.g. SW, or HW with polarity) : 423 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) 424 * - if HW trigger enabled, set source & polarity 425 */ 426 static int stm32_adc_set_trig(struct iio_dev *indio_dev, 427 struct iio_trigger *trig) 428 { 429 struct stm32_adc *adc = iio_priv(indio_dev); 430 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; 431 unsigned long flags; 432 int ret; 433 434 if (trig) { 435 ret = stm32_adc_get_trig_extsel(trig); 436 if (ret < 0) 437 return ret; 438 439 /* set trigger source and polarity (default to rising edge) */ 440 extsel = ret; 441 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; 442 } 443 444 spin_lock_irqsave(&adc->lock, flags); 445 val = stm32_adc_readl(adc, STM32F4_ADC_CR2); 446 val &= ~(STM32F4_EXTEN_MASK | STM32F4_EXTSEL_MASK); 447 val |= exten << STM32F4_EXTEN_SHIFT; 448 val |= extsel << STM32F4_EXTSEL_SHIFT; 449 stm32_adc_writel(adc, STM32F4_ADC_CR2, val); 450 spin_unlock_irqrestore(&adc->lock, flags); 451 452 return 0; 453 } 454 455 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, 456 const struct iio_chan_spec *chan, 457 unsigned int type) 458 { 459 struct stm32_adc *adc = iio_priv(indio_dev); 460 461 adc->trigger_polarity = type; 462 463 return 0; 464 } 465 466 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, 467 const struct iio_chan_spec *chan) 468 { 469 struct stm32_adc *adc = iio_priv(indio_dev); 470 471 return adc->trigger_polarity; 472 } 473 474 static const char * const stm32_trig_pol_items[] = { 475 "rising-edge", "falling-edge", "both-edges", 476 }; 477 478 static const struct iio_enum stm32_adc_trig_pol = { 479 .items = stm32_trig_pol_items, 480 .num_items = ARRAY_SIZE(stm32_trig_pol_items), 481 .get = stm32_adc_get_trig_pol, 482 .set = stm32_adc_set_trig_pol, 483 }; 484 485 /** 486 * stm32_adc_single_conv() - Performs a single conversion 487 * @indio_dev: IIO device 488 * @chan: IIO channel 489 * @res: conversion result 490 * 491 * The function performs a single conversion on a given channel: 492 * - Program sequencer with one channel (e.g. in SQ1 with len = 1) 493 * - Use SW trigger 494 * - Start conversion, then wait for interrupt completion. 495 */ 496 static int stm32_adc_single_conv(struct iio_dev *indio_dev, 497 const struct iio_chan_spec *chan, 498 int *res) 499 { 500 struct stm32_adc *adc = iio_priv(indio_dev); 501 long timeout; 502 u32 val; 503 int ret; 504 505 reinit_completion(&adc->completion); 506 507 adc->bufi = 0; 508 509 /* Program chan number in regular sequence (SQ1) */ 510 val = stm32_adc_readl(adc, stm32f4_sq[1].reg); 511 val &= ~stm32f4_sq[1].mask; 512 val |= chan->channel << stm32f4_sq[1].shift; 513 stm32_adc_writel(adc, stm32f4_sq[1].reg, val); 514 515 /* Set regular sequence len (0 for 1 conversion) */ 516 stm32_adc_clr_bits(adc, stm32f4_sq[0].reg, stm32f4_sq[0].mask); 517 518 /* Trigger detection disabled (conversion can be launched in SW) */ 519 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 520 521 stm32_adc_conv_irq_enable(adc); 522 523 stm32_adc_start_conv(adc, false); 524 525 timeout = wait_for_completion_interruptible_timeout( 526 &adc->completion, STM32_ADC_TIMEOUT); 527 if (timeout == 0) { 528 ret = -ETIMEDOUT; 529 } else if (timeout < 0) { 530 ret = timeout; 531 } else { 532 *res = adc->buffer[0]; 533 ret = IIO_VAL_INT; 534 } 535 536 stm32_adc_stop_conv(adc); 537 538 stm32_adc_conv_irq_disable(adc); 539 540 return ret; 541 } 542 543 static int stm32_adc_read_raw(struct iio_dev *indio_dev, 544 struct iio_chan_spec const *chan, 545 int *val, int *val2, long mask) 546 { 547 struct stm32_adc *adc = iio_priv(indio_dev); 548 int ret; 549 550 switch (mask) { 551 case IIO_CHAN_INFO_RAW: 552 ret = iio_device_claim_direct_mode(indio_dev); 553 if (ret) 554 return ret; 555 if (chan->type == IIO_VOLTAGE) 556 ret = stm32_adc_single_conv(indio_dev, chan, val); 557 else 558 ret = -EINVAL; 559 iio_device_release_direct_mode(indio_dev); 560 return ret; 561 562 case IIO_CHAN_INFO_SCALE: 563 *val = adc->common->vref_mv; 564 *val2 = chan->scan_type.realbits; 565 return IIO_VAL_FRACTIONAL_LOG2; 566 567 default: 568 return -EINVAL; 569 } 570 } 571 572 static irqreturn_t stm32_adc_isr(int irq, void *data) 573 { 574 struct stm32_adc *adc = data; 575 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 576 u32 status = stm32_adc_readl(adc, STM32F4_ADC_SR); 577 578 if (status & STM32F4_EOC) { 579 /* Reading DR also clears EOC status flag */ 580 adc->buffer[adc->bufi] = stm32_adc_readw(adc, STM32F4_ADC_DR); 581 if (iio_buffer_enabled(indio_dev)) { 582 adc->bufi++; 583 if (adc->bufi >= adc->num_conv) { 584 stm32_adc_conv_irq_disable(adc); 585 iio_trigger_poll(indio_dev->trig); 586 } 587 } else { 588 complete(&adc->completion); 589 } 590 return IRQ_HANDLED; 591 } 592 593 return IRQ_NONE; 594 } 595 596 /** 597 * stm32_adc_validate_trigger() - validate trigger for stm32 adc 598 * @indio_dev: IIO device 599 * @trig: new trigger 600 * 601 * Returns: 0 if trig matches one of the triggers registered by stm32 adc 602 * driver, -EINVAL otherwise. 603 */ 604 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, 605 struct iio_trigger *trig) 606 { 607 return stm32_adc_get_trig_extsel(trig) < 0 ? -EINVAL : 0; 608 } 609 610 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 611 { 612 struct stm32_adc *adc = iio_priv(indio_dev); 613 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2; 614 615 /* 616 * dma cyclic transfers are used, buffer is split into two periods. 617 * There should be : 618 * - always one buffer (period) dma is working on 619 * - one buffer (period) driver can push with iio_trigger_poll(). 620 */ 621 watermark = min(watermark, val * (unsigned)(sizeof(u16))); 622 adc->rx_buf_sz = watermark * 2; 623 624 return 0; 625 } 626 627 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, 628 const unsigned long *scan_mask) 629 { 630 struct stm32_adc *adc = iio_priv(indio_dev); 631 int ret; 632 633 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); 634 635 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask); 636 if (ret) 637 return ret; 638 639 return 0; 640 } 641 642 static int stm32_adc_of_xlate(struct iio_dev *indio_dev, 643 const struct of_phandle_args *iiospec) 644 { 645 int i; 646 647 for (i = 0; i < indio_dev->num_channels; i++) 648 if (indio_dev->channels[i].channel == iiospec->args[0]) 649 return i; 650 651 return -EINVAL; 652 } 653 654 /** 655 * stm32_adc_debugfs_reg_access - read or write register value 656 * 657 * To read a value from an ADC register: 658 * echo [ADC reg offset] > direct_reg_access 659 * cat direct_reg_access 660 * 661 * To write a value in a ADC register: 662 * echo [ADC_reg_offset] [value] > direct_reg_access 663 */ 664 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, 665 unsigned reg, unsigned writeval, 666 unsigned *readval) 667 { 668 struct stm32_adc *adc = iio_priv(indio_dev); 669 670 if (!readval) 671 stm32_adc_writel(adc, reg, writeval); 672 else 673 *readval = stm32_adc_readl(adc, reg); 674 675 return 0; 676 } 677 678 static const struct iio_info stm32_adc_iio_info = { 679 .read_raw = stm32_adc_read_raw, 680 .validate_trigger = stm32_adc_validate_trigger, 681 .hwfifo_set_watermark = stm32_adc_set_watermark, 682 .update_scan_mode = stm32_adc_update_scan_mode, 683 .debugfs_reg_access = stm32_adc_debugfs_reg_access, 684 .of_xlate = stm32_adc_of_xlate, 685 .driver_module = THIS_MODULE, 686 }; 687 688 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) 689 { 690 struct dma_tx_state state; 691 enum dma_status status; 692 693 status = dmaengine_tx_status(adc->dma_chan, 694 adc->dma_chan->cookie, 695 &state); 696 if (status == DMA_IN_PROGRESS) { 697 /* Residue is size in bytes from end of buffer */ 698 unsigned int i = adc->rx_buf_sz - state.residue; 699 unsigned int size; 700 701 /* Return available bytes */ 702 if (i >= adc->bufi) 703 size = i - adc->bufi; 704 else 705 size = adc->rx_buf_sz + i - adc->bufi; 706 707 return size; 708 } 709 710 return 0; 711 } 712 713 static void stm32_adc_dma_buffer_done(void *data) 714 { 715 struct iio_dev *indio_dev = data; 716 717 iio_trigger_poll_chained(indio_dev->trig); 718 } 719 720 static int stm32_adc_dma_start(struct iio_dev *indio_dev) 721 { 722 struct stm32_adc *adc = iio_priv(indio_dev); 723 struct dma_async_tx_descriptor *desc; 724 dma_cookie_t cookie; 725 int ret; 726 727 if (!adc->dma_chan) 728 return 0; 729 730 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 731 adc->rx_buf_sz, adc->rx_buf_sz / 2); 732 733 /* Prepare a DMA cyclic transaction */ 734 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 735 adc->rx_dma_buf, 736 adc->rx_buf_sz, adc->rx_buf_sz / 2, 737 DMA_DEV_TO_MEM, 738 DMA_PREP_INTERRUPT); 739 if (!desc) 740 return -EBUSY; 741 742 desc->callback = stm32_adc_dma_buffer_done; 743 desc->callback_param = indio_dev; 744 745 cookie = dmaengine_submit(desc); 746 ret = dma_submit_error(cookie); 747 if (ret) { 748 dmaengine_terminate_all(adc->dma_chan); 749 return ret; 750 } 751 752 /* Issue pending DMA requests */ 753 dma_async_issue_pending(adc->dma_chan); 754 755 return 0; 756 } 757 758 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) 759 { 760 struct stm32_adc *adc = iio_priv(indio_dev); 761 int ret; 762 763 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); 764 if (ret) { 765 dev_err(&indio_dev->dev, "Can't set trigger\n"); 766 return ret; 767 } 768 769 ret = stm32_adc_dma_start(indio_dev); 770 if (ret) { 771 dev_err(&indio_dev->dev, "Can't start dma\n"); 772 goto err_clr_trig; 773 } 774 775 ret = iio_triggered_buffer_postenable(indio_dev); 776 if (ret < 0) 777 goto err_stop_dma; 778 779 /* Reset adc buffer index */ 780 adc->bufi = 0; 781 782 if (!adc->dma_chan) 783 stm32_adc_conv_irq_enable(adc); 784 785 stm32_adc_start_conv(adc, !!adc->dma_chan); 786 787 return 0; 788 789 err_stop_dma: 790 if (adc->dma_chan) 791 dmaengine_terminate_all(adc->dma_chan); 792 err_clr_trig: 793 stm32_adc_set_trig(indio_dev, NULL); 794 795 return ret; 796 } 797 798 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) 799 { 800 struct stm32_adc *adc = iio_priv(indio_dev); 801 int ret; 802 803 stm32_adc_stop_conv(adc); 804 if (!adc->dma_chan) 805 stm32_adc_conv_irq_disable(adc); 806 807 ret = iio_triggered_buffer_predisable(indio_dev); 808 if (ret < 0) 809 dev_err(&indio_dev->dev, "predisable failed\n"); 810 811 if (adc->dma_chan) 812 dmaengine_terminate_all(adc->dma_chan); 813 814 if (stm32_adc_set_trig(indio_dev, NULL)) 815 dev_err(&indio_dev->dev, "Can't clear trigger\n"); 816 817 return ret; 818 } 819 820 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = { 821 .postenable = &stm32_adc_buffer_postenable, 822 .predisable = &stm32_adc_buffer_predisable, 823 }; 824 825 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) 826 { 827 struct iio_poll_func *pf = p; 828 struct iio_dev *indio_dev = pf->indio_dev; 829 struct stm32_adc *adc = iio_priv(indio_dev); 830 831 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 832 833 if (!adc->dma_chan) { 834 /* reset buffer index */ 835 adc->bufi = 0; 836 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, 837 pf->timestamp); 838 } else { 839 int residue = stm32_adc_dma_residue(adc); 840 841 while (residue >= indio_dev->scan_bytes) { 842 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 843 844 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 845 pf->timestamp); 846 residue -= indio_dev->scan_bytes; 847 adc->bufi += indio_dev->scan_bytes; 848 if (adc->bufi >= adc->rx_buf_sz) 849 adc->bufi = 0; 850 } 851 } 852 853 iio_trigger_notify_done(indio_dev->trig); 854 855 /* re-enable eoc irq */ 856 if (!adc->dma_chan) 857 stm32_adc_conv_irq_enable(adc); 858 859 return IRQ_HANDLED; 860 } 861 862 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = { 863 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), 864 { 865 .name = "trigger_polarity_available", 866 .shared = IIO_SHARED_BY_ALL, 867 .read = iio_enum_available_read, 868 .private = (uintptr_t)&stm32_adc_trig_pol, 869 }, 870 {}, 871 }; 872 873 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, 874 struct iio_chan_spec *chan, 875 const struct stm32_adc_chan_spec *channel, 876 int scan_index) 877 { 878 chan->type = channel->type; 879 chan->channel = channel->channel; 880 chan->datasheet_name = channel->name; 881 chan->scan_index = scan_index; 882 chan->indexed = 1; 883 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 884 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 885 chan->scan_type.sign = 'u'; 886 chan->scan_type.realbits = 12; 887 chan->scan_type.storagebits = 16; 888 chan->ext_info = stm32_adc_ext_info; 889 } 890 891 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev) 892 { 893 struct device_node *node = indio_dev->dev.of_node; 894 struct property *prop; 895 const __be32 *cur; 896 struct iio_chan_spec *channels; 897 int scan_index = 0, num_channels; 898 u32 val; 899 900 num_channels = of_property_count_u32_elems(node, "st,adc-channels"); 901 if (num_channels < 0 || 902 num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) { 903 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); 904 return num_channels < 0 ? num_channels : -EINVAL; 905 } 906 907 channels = devm_kcalloc(&indio_dev->dev, num_channels, 908 sizeof(struct iio_chan_spec), GFP_KERNEL); 909 if (!channels) 910 return -ENOMEM; 911 912 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { 913 if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) { 914 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); 915 return -EINVAL; 916 } 917 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 918 &stm32f4_adc123_channels[val], 919 scan_index); 920 scan_index++; 921 } 922 923 indio_dev->num_channels = scan_index; 924 indio_dev->channels = channels; 925 926 return 0; 927 } 928 929 static int stm32_adc_dma_request(struct iio_dev *indio_dev) 930 { 931 struct stm32_adc *adc = iio_priv(indio_dev); 932 struct dma_slave_config config; 933 int ret; 934 935 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx"); 936 if (!adc->dma_chan) 937 return 0; 938 939 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 940 STM32_DMA_BUFFER_SIZE, 941 &adc->rx_dma_buf, GFP_KERNEL); 942 if (!adc->rx_buf) { 943 ret = -ENOMEM; 944 goto err_release; 945 } 946 947 /* Configure DMA channel to read data register */ 948 memset(&config, 0, sizeof(config)); 949 config.src_addr = (dma_addr_t)adc->common->phys_base; 950 config.src_addr += adc->offset + STM32F4_ADC_DR; 951 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 952 953 ret = dmaengine_slave_config(adc->dma_chan, &config); 954 if (ret) 955 goto err_free; 956 957 return 0; 958 959 err_free: 960 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, 961 adc->rx_buf, adc->rx_dma_buf); 962 err_release: 963 dma_release_channel(adc->dma_chan); 964 965 return ret; 966 } 967 968 static int stm32_adc_probe(struct platform_device *pdev) 969 { 970 struct iio_dev *indio_dev; 971 struct stm32_adc *adc; 972 int ret; 973 974 if (!pdev->dev.of_node) 975 return -ENODEV; 976 977 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 978 if (!indio_dev) 979 return -ENOMEM; 980 981 adc = iio_priv(indio_dev); 982 adc->common = dev_get_drvdata(pdev->dev.parent); 983 spin_lock_init(&adc->lock); 984 init_completion(&adc->completion); 985 986 indio_dev->name = dev_name(&pdev->dev); 987 indio_dev->dev.parent = &pdev->dev; 988 indio_dev->dev.of_node = pdev->dev.of_node; 989 indio_dev->info = &stm32_adc_iio_info; 990 indio_dev->modes = INDIO_DIRECT_MODE; 991 992 platform_set_drvdata(pdev, adc); 993 994 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset); 995 if (ret != 0) { 996 dev_err(&pdev->dev, "missing reg property\n"); 997 return -EINVAL; 998 } 999 1000 adc->irq = platform_get_irq(pdev, 0); 1001 if (adc->irq < 0) { 1002 dev_err(&pdev->dev, "failed to get irq\n"); 1003 return adc->irq; 1004 } 1005 1006 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr, 1007 0, pdev->name, adc); 1008 if (ret) { 1009 dev_err(&pdev->dev, "failed to request IRQ\n"); 1010 return ret; 1011 } 1012 1013 adc->clk = devm_clk_get(&pdev->dev, NULL); 1014 if (IS_ERR(adc->clk)) { 1015 dev_err(&pdev->dev, "Can't get clock\n"); 1016 return PTR_ERR(adc->clk); 1017 } 1018 1019 ret = clk_prepare_enable(adc->clk); 1020 if (ret < 0) { 1021 dev_err(&pdev->dev, "clk enable failed\n"); 1022 return ret; 1023 } 1024 1025 ret = stm32_adc_chan_of_init(indio_dev); 1026 if (ret < 0) 1027 goto err_clk_disable; 1028 1029 ret = stm32_adc_dma_request(indio_dev); 1030 if (ret < 0) 1031 goto err_clk_disable; 1032 1033 ret = iio_triggered_buffer_setup(indio_dev, 1034 &iio_pollfunc_store_time, 1035 &stm32_adc_trigger_handler, 1036 &stm32_adc_buffer_setup_ops); 1037 if (ret) { 1038 dev_err(&pdev->dev, "buffer setup failed\n"); 1039 goto err_dma_disable; 1040 } 1041 1042 ret = iio_device_register(indio_dev); 1043 if (ret) { 1044 dev_err(&pdev->dev, "iio dev register failed\n"); 1045 goto err_buffer_cleanup; 1046 } 1047 1048 return 0; 1049 1050 err_buffer_cleanup: 1051 iio_triggered_buffer_cleanup(indio_dev); 1052 1053 err_dma_disable: 1054 if (adc->dma_chan) { 1055 dma_free_coherent(adc->dma_chan->device->dev, 1056 STM32_DMA_BUFFER_SIZE, 1057 adc->rx_buf, adc->rx_dma_buf); 1058 dma_release_channel(adc->dma_chan); 1059 } 1060 err_clk_disable: 1061 clk_disable_unprepare(adc->clk); 1062 1063 return ret; 1064 } 1065 1066 static int stm32_adc_remove(struct platform_device *pdev) 1067 { 1068 struct stm32_adc *adc = platform_get_drvdata(pdev); 1069 struct iio_dev *indio_dev = iio_priv_to_dev(adc); 1070 1071 iio_device_unregister(indio_dev); 1072 iio_triggered_buffer_cleanup(indio_dev); 1073 if (adc->dma_chan) { 1074 dma_free_coherent(adc->dma_chan->device->dev, 1075 STM32_DMA_BUFFER_SIZE, 1076 adc->rx_buf, adc->rx_dma_buf); 1077 dma_release_channel(adc->dma_chan); 1078 } 1079 clk_disable_unprepare(adc->clk); 1080 1081 return 0; 1082 } 1083 1084 static const struct of_device_id stm32_adc_of_match[] = { 1085 { .compatible = "st,stm32f4-adc" }, 1086 {}, 1087 }; 1088 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 1089 1090 static struct platform_driver stm32_adc_driver = { 1091 .probe = stm32_adc_probe, 1092 .remove = stm32_adc_remove, 1093 .driver = { 1094 .name = "stm32-adc", 1095 .of_match_table = stm32_adc_of_match, 1096 }, 1097 }; 1098 module_platform_driver(stm32_adc_driver); 1099 1100 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 1101 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver"); 1102 MODULE_LICENSE("GPL v2"); 1103 MODULE_ALIAS("platform:stm32-adc"); 1104