1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdesc.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include "stm32-adc-core.h" 26 27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 28 29 /* SYSCFG registers */ 30 #define STM32MP1_SYSCFG_PMCSETR 0x04 31 #define STM32MP1_SYSCFG_PMCCLRR 0x44 32 33 /* SYSCFG bit fields */ 34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 35 36 /* SYSCFG capability flags */ 37 #define HAS_VBOOSTER BIT(0) 38 #define HAS_ANASWVDD BIT(1) 39 40 /** 41 * struct stm32_adc_common_regs - stm32 common registers 42 * @csr: common status register offset 43 * @ccr: common control register offset 44 * @eoc1_msk: adc1 end of conversion flag in @csr 45 * @eoc2_msk: adc2 end of conversion flag in @csr 46 * @eoc3_msk: adc3 end of conversion flag in @csr 47 * @ier: interrupt enable register offset for each adc 48 * @eocie_msk: end of conversion interrupt enable mask in @ier 49 */ 50 struct stm32_adc_common_regs { 51 u32 csr; 52 u32 ccr; 53 u32 eoc1_msk; 54 u32 eoc2_msk; 55 u32 eoc3_msk; 56 u32 ier; 57 u32 eocie_msk; 58 }; 59 60 struct stm32_adc_priv; 61 62 /** 63 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 64 * @regs: common registers for all instances 65 * @clk_sel: clock selection routine 66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 67 * @has_syscfg: SYSCFG capability flags 68 * @num_irqs: number of interrupt lines 69 */ 70 struct stm32_adc_priv_cfg { 71 const struct stm32_adc_common_regs *regs; 72 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 73 u32 max_clk_rate_hz; 74 unsigned int has_syscfg; 75 unsigned int num_irqs; 76 }; 77 78 /** 79 * struct stm32_adc_priv - stm32 ADC core private data 80 * @irq: irq(s) for ADC block 81 * @domain: irq domain reference 82 * @aclk: clock reference for the analog circuitry 83 * @bclk: bus clock common for all ADCs, depends on part used 84 * @max_clk_rate: desired maximum clock rate 85 * @booster: booster supply reference 86 * @vdd: vdd supply reference 87 * @vdda: vdda analog supply reference 88 * @vref: regulator reference 89 * @vdd_uv: vdd supply voltage (microvolts) 90 * @vdda_uv: vdda supply voltage (microvolts) 91 * @cfg: compatible configuration data 92 * @common: common data for all ADC instances 93 * @ccr_bak: backup CCR in low power mode 94 * @syscfg: reference to syscon, system control registers 95 */ 96 struct stm32_adc_priv { 97 int irq[STM32_ADC_MAX_ADCS]; 98 struct irq_domain *domain; 99 struct clk *aclk; 100 struct clk *bclk; 101 u32 max_clk_rate; 102 struct regulator *booster; 103 struct regulator *vdd; 104 struct regulator *vdda; 105 struct regulator *vref; 106 int vdd_uv; 107 int vdda_uv; 108 const struct stm32_adc_priv_cfg *cfg; 109 struct stm32_adc_common common; 110 u32 ccr_bak; 111 struct regmap *syscfg; 112 }; 113 114 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 115 { 116 return container_of(com, struct stm32_adc_priv, common); 117 } 118 119 /* STM32F4 ADC internal common clock prescaler division ratios */ 120 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 121 122 /** 123 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 124 * @pdev: platform device 125 * @priv: stm32 ADC core private data 126 * Select clock prescaler used for analog conversions, before using ADC. 127 */ 128 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 129 struct stm32_adc_priv *priv) 130 { 131 unsigned long rate; 132 u32 val; 133 int i; 134 135 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 136 if (!priv->aclk) { 137 dev_err(&pdev->dev, "No 'adc' clock found\n"); 138 return -ENOENT; 139 } 140 141 rate = clk_get_rate(priv->aclk); 142 if (!rate) { 143 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 144 return -EINVAL; 145 } 146 147 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 148 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 149 break; 150 } 151 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 152 dev_err(&pdev->dev, "adc clk selection failed\n"); 153 return -EINVAL; 154 } 155 156 priv->common.rate = rate / stm32f4_pclk_div[i]; 157 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 158 val &= ~STM32F4_ADC_ADCPRE_MASK; 159 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 160 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 161 162 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 163 priv->common.rate / 1000); 164 165 return 0; 166 } 167 168 /** 169 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 170 * @ckmode: ADC clock mode, Async or sync with prescaler. 171 * @presc: prescaler bitfield for async clock mode 172 * @div: prescaler division ratio 173 */ 174 struct stm32h7_adc_ck_spec { 175 u32 ckmode; 176 u32 presc; 177 int div; 178 }; 179 180 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 181 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 182 { 0, 0, 1 }, 183 { 0, 1, 2 }, 184 { 0, 2, 4 }, 185 { 0, 3, 6 }, 186 { 0, 4, 8 }, 187 { 0, 5, 10 }, 188 { 0, 6, 12 }, 189 { 0, 7, 16 }, 190 { 0, 8, 32 }, 191 { 0, 9, 64 }, 192 { 0, 10, 128 }, 193 { 0, 11, 256 }, 194 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 195 { 1, 0, 1 }, 196 { 2, 0, 2 }, 197 { 3, 0, 4 }, 198 }; 199 200 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 201 struct stm32_adc_priv *priv) 202 { 203 u32 ckmode, presc, val; 204 unsigned long rate; 205 int i, div, duty; 206 207 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 208 if (!priv->bclk) { 209 dev_err(&pdev->dev, "No 'bus' clock found\n"); 210 return -ENOENT; 211 } 212 213 /* 214 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 215 * So, choice is to have bus clock mandatory and adc clock optional. 216 * If optional 'adc' clock has been found, then try to use it first. 217 */ 218 if (priv->aclk) { 219 /* 220 * Asynchronous clock modes (e.g. ckmode == 0) 221 * From spec: PLL output musn't exceed max rate 222 */ 223 rate = clk_get_rate(priv->aclk); 224 if (!rate) { 225 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 226 return -EINVAL; 227 } 228 229 /* If duty is an error, kindly use at least /2 divider */ 230 duty = clk_get_scaled_duty_cycle(priv->aclk, 100); 231 if (duty < 0) 232 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty); 233 234 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 235 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 236 presc = stm32h7_adc_ckmodes_spec[i].presc; 237 div = stm32h7_adc_ckmodes_spec[i].div; 238 239 if (ckmode) 240 continue; 241 242 /* 243 * For proper operation, clock duty cycle range is 49% 244 * to 51%. Apply at least /2 prescaler otherwise. 245 */ 246 if (div == 1 && (duty < 49 || duty > 51)) 247 continue; 248 249 if ((rate / div) <= priv->max_clk_rate) 250 goto out; 251 } 252 } 253 254 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 255 rate = clk_get_rate(priv->bclk); 256 if (!rate) { 257 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 258 return -EINVAL; 259 } 260 261 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); 262 if (duty < 0) 263 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty); 264 265 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 266 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 267 presc = stm32h7_adc_ckmodes_spec[i].presc; 268 div = stm32h7_adc_ckmodes_spec[i].div; 269 270 if (!ckmode) 271 continue; 272 273 if (div == 1 && (duty < 49 || duty > 51)) 274 continue; 275 276 if ((rate / div) <= priv->max_clk_rate) 277 goto out; 278 } 279 280 dev_err(&pdev->dev, "adc clk selection failed\n"); 281 return -EINVAL; 282 283 out: 284 /* rate used later by each ADC instance to control BOOST mode */ 285 priv->common.rate = rate / div; 286 287 /* Set common clock mode and prescaler */ 288 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 289 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 290 val |= ckmode << STM32H7_CKMODE_SHIFT; 291 val |= presc << STM32H7_PRESC_SHIFT; 292 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 293 294 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 295 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 296 297 return 0; 298 } 299 300 /* STM32F4 common registers definitions */ 301 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 302 .csr = STM32F4_ADC_CSR, 303 .ccr = STM32F4_ADC_CCR, 304 .eoc1_msk = STM32F4_EOC1 | STM32F4_OVR1, 305 .eoc2_msk = STM32F4_EOC2 | STM32F4_OVR2, 306 .eoc3_msk = STM32F4_EOC3 | STM32F4_OVR3, 307 .ier = STM32F4_ADC_CR1, 308 .eocie_msk = STM32F4_EOCIE | STM32F4_OVRIE, 309 }; 310 311 /* STM32H7 common registers definitions */ 312 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 313 .csr = STM32H7_ADC_CSR, 314 .ccr = STM32H7_ADC_CCR, 315 .eoc1_msk = STM32H7_EOC_MST | STM32H7_OVR_MST, 316 .eoc2_msk = STM32H7_EOC_SLV | STM32H7_OVR_SLV, 317 .ier = STM32H7_ADC_IER, 318 .eocie_msk = STM32H7_EOCIE | STM32H7_OVRIE, 319 }; 320 321 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 322 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 323 }; 324 325 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 326 unsigned int adc) 327 { 328 u32 ier, offset = stm32_adc_offset[adc]; 329 330 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 331 332 return ier & priv->cfg->regs->eocie_msk; 333 } 334 335 /* ADC common interrupt for all instances */ 336 static void stm32_adc_irq_handler(struct irq_desc *desc) 337 { 338 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 339 struct irq_chip *chip = irq_desc_get_chip(desc); 340 u32 status; 341 342 chained_irq_enter(chip, desc); 343 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 344 345 /* 346 * End of conversion may be handled by using IRQ or DMA. There may be a 347 * race here when two conversions complete at the same time on several 348 * ADCs. EOC may be read 'set' for several ADCs, with: 349 * - an ADC configured to use DMA (EOC triggers the DMA request, and 350 * is then automatically cleared by DR read in hardware) 351 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 352 * be called in this case) 353 * So both EOC status bit in CSR and EOCIE control bit must be checked 354 * before invoking the interrupt handler (e.g. call ISR only for 355 * IRQ-enabled ADCs). 356 */ 357 if (status & priv->cfg->regs->eoc1_msk && 358 stm32_adc_eoc_enabled(priv, 0)) 359 generic_handle_irq(irq_find_mapping(priv->domain, 0)); 360 361 if (status & priv->cfg->regs->eoc2_msk && 362 stm32_adc_eoc_enabled(priv, 1)) 363 generic_handle_irq(irq_find_mapping(priv->domain, 1)); 364 365 if (status & priv->cfg->regs->eoc3_msk && 366 stm32_adc_eoc_enabled(priv, 2)) 367 generic_handle_irq(irq_find_mapping(priv->domain, 2)); 368 369 chained_irq_exit(chip, desc); 370 }; 371 372 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 373 irq_hw_number_t hwirq) 374 { 375 irq_set_chip_data(irq, d->host_data); 376 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 377 378 return 0; 379 } 380 381 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 382 { 383 irq_set_chip_and_handler(irq, NULL, NULL); 384 irq_set_chip_data(irq, NULL); 385 } 386 387 static const struct irq_domain_ops stm32_adc_domain_ops = { 388 .map = stm32_adc_domain_map, 389 .unmap = stm32_adc_domain_unmap, 390 .xlate = irq_domain_xlate_onecell, 391 }; 392 393 static int stm32_adc_irq_probe(struct platform_device *pdev, 394 struct stm32_adc_priv *priv) 395 { 396 struct device_node *np = pdev->dev.of_node; 397 unsigned int i; 398 399 /* 400 * Interrupt(s) must be provided, depending on the compatible: 401 * - stm32f4/h7 shares a common interrupt line. 402 * - stm32mp1, has one line per ADC 403 */ 404 for (i = 0; i < priv->cfg->num_irqs; i++) { 405 priv->irq[i] = platform_get_irq(pdev, i); 406 if (priv->irq[i] < 0) 407 return priv->irq[i]; 408 } 409 410 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 411 &stm32_adc_domain_ops, 412 priv); 413 if (!priv->domain) { 414 dev_err(&pdev->dev, "Failed to add irq domain\n"); 415 return -ENOMEM; 416 } 417 418 for (i = 0; i < priv->cfg->num_irqs; i++) { 419 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 420 irq_set_handler_data(priv->irq[i], priv); 421 } 422 423 return 0; 424 } 425 426 static void stm32_adc_irq_remove(struct platform_device *pdev, 427 struct stm32_adc_priv *priv) 428 { 429 int hwirq; 430 unsigned int i; 431 432 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 433 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 434 irq_domain_remove(priv->domain); 435 436 for (i = 0; i < priv->cfg->num_irqs; i++) 437 irq_set_chained_handler(priv->irq[i], NULL); 438 } 439 440 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 441 struct device *dev) 442 { 443 int ret; 444 445 /* 446 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 447 * switches (via PCSEL) which have reduced performances when their 448 * supply is below 2.7V (vdda by default): 449 * - Voltage booster can be used, to get full ADC performances 450 * (increases power consumption). 451 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 452 * 453 * Recommended settings for ANASWVDD and EN_BOOSTER: 454 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 455 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 456 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 457 */ 458 if (priv->vdda_uv < 2700000) { 459 if (priv->syscfg && priv->vdd_uv > 2700000) { 460 ret = regulator_enable(priv->vdd); 461 if (ret < 0) { 462 dev_err(dev, "vdd enable failed %d\n", ret); 463 return ret; 464 } 465 466 ret = regmap_write(priv->syscfg, 467 STM32MP1_SYSCFG_PMCSETR, 468 STM32MP1_SYSCFG_ANASWVDD_MASK); 469 if (ret < 0) { 470 regulator_disable(priv->vdd); 471 dev_err(dev, "vdd select failed, %d\n", ret); 472 return ret; 473 } 474 dev_dbg(dev, "analog switches supplied by vdd\n"); 475 476 return 0; 477 } 478 479 if (priv->booster) { 480 /* 481 * This is optional, as this is a trade-off between 482 * analog performance and power consumption. 483 */ 484 ret = regulator_enable(priv->booster); 485 if (ret < 0) { 486 dev_err(dev, "booster enable failed %d\n", ret); 487 return ret; 488 } 489 dev_dbg(dev, "analog switches supplied by booster\n"); 490 491 return 0; 492 } 493 } 494 495 /* Fallback using vdda (default), nothing to do */ 496 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 497 priv->vdda_uv); 498 499 return 0; 500 } 501 502 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 503 { 504 if (priv->vdda_uv < 2700000) { 505 if (priv->syscfg && priv->vdd_uv > 2700000) { 506 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 507 STM32MP1_SYSCFG_ANASWVDD_MASK); 508 regulator_disable(priv->vdd); 509 return; 510 } 511 if (priv->booster) 512 regulator_disable(priv->booster); 513 } 514 } 515 516 static int stm32_adc_core_hw_start(struct device *dev) 517 { 518 struct stm32_adc_common *common = dev_get_drvdata(dev); 519 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 520 int ret; 521 522 ret = regulator_enable(priv->vdda); 523 if (ret < 0) { 524 dev_err(dev, "vdda enable failed %d\n", ret); 525 return ret; 526 } 527 528 ret = regulator_get_voltage(priv->vdda); 529 if (ret < 0) { 530 dev_err(dev, "vdda get voltage failed, %d\n", ret); 531 goto err_vdda_disable; 532 } 533 priv->vdda_uv = ret; 534 535 ret = stm32_adc_core_switches_supply_en(priv, dev); 536 if (ret < 0) 537 goto err_vdda_disable; 538 539 ret = regulator_enable(priv->vref); 540 if (ret < 0) { 541 dev_err(dev, "vref enable failed\n"); 542 goto err_switches_dis; 543 } 544 545 if (priv->bclk) { 546 ret = clk_prepare_enable(priv->bclk); 547 if (ret < 0) { 548 dev_err(dev, "bus clk enable failed\n"); 549 goto err_regulator_disable; 550 } 551 } 552 553 if (priv->aclk) { 554 ret = clk_prepare_enable(priv->aclk); 555 if (ret < 0) { 556 dev_err(dev, "adc clk enable failed\n"); 557 goto err_bclk_disable; 558 } 559 } 560 561 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 562 563 return 0; 564 565 err_bclk_disable: 566 if (priv->bclk) 567 clk_disable_unprepare(priv->bclk); 568 err_regulator_disable: 569 regulator_disable(priv->vref); 570 err_switches_dis: 571 stm32_adc_core_switches_supply_dis(priv); 572 err_vdda_disable: 573 regulator_disable(priv->vdda); 574 575 return ret; 576 } 577 578 static void stm32_adc_core_hw_stop(struct device *dev) 579 { 580 struct stm32_adc_common *common = dev_get_drvdata(dev); 581 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 582 583 /* Backup CCR that may be lost (depends on power state to achieve) */ 584 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 585 if (priv->aclk) 586 clk_disable_unprepare(priv->aclk); 587 if (priv->bclk) 588 clk_disable_unprepare(priv->bclk); 589 regulator_disable(priv->vref); 590 stm32_adc_core_switches_supply_dis(priv); 591 regulator_disable(priv->vdda); 592 } 593 594 static int stm32_adc_core_switches_probe(struct device *dev, 595 struct stm32_adc_priv *priv) 596 { 597 struct device_node *np = dev->of_node; 598 int ret; 599 600 /* Analog switches supply can be controlled by syscfg (optional) */ 601 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 602 if (IS_ERR(priv->syscfg)) { 603 ret = PTR_ERR(priv->syscfg); 604 if (ret != -ENODEV) 605 return dev_err_probe(dev, ret, "Can't probe syscfg\n"); 606 607 priv->syscfg = NULL; 608 } 609 610 /* Booster can be used to supply analog switches (optional) */ 611 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 612 of_property_read_bool(np, "booster-supply")) { 613 priv->booster = devm_regulator_get_optional(dev, "booster"); 614 if (IS_ERR(priv->booster)) { 615 ret = PTR_ERR(priv->booster); 616 if (ret != -ENODEV) 617 return dev_err_probe(dev, ret, "can't get booster\n"); 618 619 priv->booster = NULL; 620 } 621 } 622 623 /* Vdd can be used to supply analog switches (optional) */ 624 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 625 of_property_read_bool(np, "vdd-supply")) { 626 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 627 if (IS_ERR(priv->vdd)) { 628 ret = PTR_ERR(priv->vdd); 629 if (ret != -ENODEV) 630 return dev_err_probe(dev, ret, "can't get vdd\n"); 631 632 priv->vdd = NULL; 633 } 634 } 635 636 if (priv->vdd) { 637 ret = regulator_enable(priv->vdd); 638 if (ret < 0) { 639 dev_err(dev, "vdd enable failed %d\n", ret); 640 return ret; 641 } 642 643 ret = regulator_get_voltage(priv->vdd); 644 if (ret < 0) { 645 dev_err(dev, "vdd get voltage failed %d\n", ret); 646 regulator_disable(priv->vdd); 647 return ret; 648 } 649 priv->vdd_uv = ret; 650 651 regulator_disable(priv->vdd); 652 } 653 654 return 0; 655 } 656 657 static int stm32_adc_probe(struct platform_device *pdev) 658 { 659 struct stm32_adc_priv *priv; 660 struct device *dev = &pdev->dev; 661 struct device_node *np = pdev->dev.of_node; 662 struct resource *res; 663 u32 max_rate; 664 int ret; 665 666 if (!pdev->dev.of_node) 667 return -ENODEV; 668 669 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 670 if (!priv) 671 return -ENOMEM; 672 platform_set_drvdata(pdev, &priv->common); 673 674 priv->cfg = (const struct stm32_adc_priv_cfg *) 675 of_match_device(dev->driver->of_match_table, dev)->data; 676 677 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 678 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 679 if (IS_ERR(priv->common.base)) 680 return PTR_ERR(priv->common.base); 681 priv->common.phys_base = res->start; 682 683 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 684 if (IS_ERR(priv->vdda)) 685 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), 686 "vdda get failed\n"); 687 688 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 689 if (IS_ERR(priv->vref)) 690 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), 691 "vref get failed\n"); 692 693 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); 694 if (IS_ERR(priv->aclk)) 695 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), 696 "Can't get 'adc' clock\n"); 697 698 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); 699 if (IS_ERR(priv->bclk)) 700 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), 701 "Can't get 'bus' clock\n"); 702 703 ret = stm32_adc_core_switches_probe(dev, priv); 704 if (ret) 705 return ret; 706 707 pm_runtime_get_noresume(dev); 708 pm_runtime_set_active(dev); 709 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 710 pm_runtime_use_autosuspend(dev); 711 pm_runtime_enable(dev); 712 713 ret = stm32_adc_core_hw_start(dev); 714 if (ret) 715 goto err_pm_stop; 716 717 ret = regulator_get_voltage(priv->vref); 718 if (ret < 0) { 719 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 720 goto err_hw_stop; 721 } 722 priv->common.vref_mv = ret / 1000; 723 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 724 725 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 726 &max_rate); 727 if (!ret) 728 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 729 else 730 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 731 732 ret = priv->cfg->clk_sel(pdev, priv); 733 if (ret < 0) 734 goto err_hw_stop; 735 736 ret = stm32_adc_irq_probe(pdev, priv); 737 if (ret < 0) 738 goto err_hw_stop; 739 740 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 741 if (ret < 0) { 742 dev_err(&pdev->dev, "failed to populate DT children\n"); 743 goto err_irq_remove; 744 } 745 746 pm_runtime_mark_last_busy(dev); 747 pm_runtime_put_autosuspend(dev); 748 749 return 0; 750 751 err_irq_remove: 752 stm32_adc_irq_remove(pdev, priv); 753 err_hw_stop: 754 stm32_adc_core_hw_stop(dev); 755 err_pm_stop: 756 pm_runtime_disable(dev); 757 pm_runtime_set_suspended(dev); 758 pm_runtime_put_noidle(dev); 759 760 return ret; 761 } 762 763 static int stm32_adc_remove(struct platform_device *pdev) 764 { 765 struct stm32_adc_common *common = platform_get_drvdata(pdev); 766 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 767 768 pm_runtime_get_sync(&pdev->dev); 769 of_platform_depopulate(&pdev->dev); 770 stm32_adc_irq_remove(pdev, priv); 771 stm32_adc_core_hw_stop(&pdev->dev); 772 pm_runtime_disable(&pdev->dev); 773 pm_runtime_set_suspended(&pdev->dev); 774 pm_runtime_put_noidle(&pdev->dev); 775 776 return 0; 777 } 778 779 #if defined(CONFIG_PM) 780 static int stm32_adc_core_runtime_suspend(struct device *dev) 781 { 782 stm32_adc_core_hw_stop(dev); 783 784 return 0; 785 } 786 787 static int stm32_adc_core_runtime_resume(struct device *dev) 788 { 789 return stm32_adc_core_hw_start(dev); 790 } 791 792 static int stm32_adc_core_runtime_idle(struct device *dev) 793 { 794 pm_runtime_mark_last_busy(dev); 795 796 return 0; 797 } 798 #endif 799 800 static const struct dev_pm_ops stm32_adc_core_pm_ops = { 801 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 802 pm_runtime_force_resume) 803 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend, 804 stm32_adc_core_runtime_resume, 805 stm32_adc_core_runtime_idle) 806 }; 807 808 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 809 .regs = &stm32f4_adc_common_regs, 810 .clk_sel = stm32f4_adc_clk_sel, 811 .max_clk_rate_hz = 36000000, 812 .num_irqs = 1, 813 }; 814 815 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 816 .regs = &stm32h7_adc_common_regs, 817 .clk_sel = stm32h7_adc_clk_sel, 818 .max_clk_rate_hz = 36000000, 819 .has_syscfg = HAS_VBOOSTER, 820 .num_irqs = 1, 821 }; 822 823 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 824 .regs = &stm32h7_adc_common_regs, 825 .clk_sel = stm32h7_adc_clk_sel, 826 .max_clk_rate_hz = 40000000, 827 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 828 .num_irqs = 2, 829 }; 830 831 static const struct of_device_id stm32_adc_of_match[] = { 832 { 833 .compatible = "st,stm32f4-adc-core", 834 .data = (void *)&stm32f4_adc_priv_cfg 835 }, { 836 .compatible = "st,stm32h7-adc-core", 837 .data = (void *)&stm32h7_adc_priv_cfg 838 }, { 839 .compatible = "st,stm32mp1-adc-core", 840 .data = (void *)&stm32mp1_adc_priv_cfg 841 }, { 842 }, 843 }; 844 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 845 846 static struct platform_driver stm32_adc_driver = { 847 .probe = stm32_adc_probe, 848 .remove = stm32_adc_remove, 849 .driver = { 850 .name = "stm32-adc-core", 851 .of_match_table = stm32_adc_of_match, 852 .pm = &stm32_adc_core_pm_ops, 853 }, 854 }; 855 module_platform_driver(stm32_adc_driver); 856 857 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 858 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 859 MODULE_LICENSE("GPL v2"); 860 MODULE_ALIAS("platform:stm32-adc-core"); 861