1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdesc.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include "stm32-adc-core.h" 26 27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 28 29 /* SYSCFG registers */ 30 #define STM32MP1_SYSCFG_PMCSETR 0x04 31 #define STM32MP1_SYSCFG_PMCCLRR 0x44 32 33 /* SYSCFG bit fields */ 34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 35 36 /* SYSCFG capability flags */ 37 #define HAS_VBOOSTER BIT(0) 38 #define HAS_ANASWVDD BIT(1) 39 40 /** 41 * struct stm32_adc_common_regs - stm32 common registers 42 * @csr: common status register offset 43 * @ccr: common control register offset 44 * @eoc1_msk: adc1 end of conversion flag in @csr 45 * @eoc2_msk: adc2 end of conversion flag in @csr 46 * @eoc3_msk: adc3 end of conversion flag in @csr 47 * @ier: interrupt enable register offset for each adc 48 * @eocie_msk: end of conversion interrupt enable mask in @ier 49 */ 50 struct stm32_adc_common_regs { 51 u32 csr; 52 u32 ccr; 53 u32 eoc1_msk; 54 u32 eoc2_msk; 55 u32 eoc3_msk; 56 u32 ier; 57 u32 eocie_msk; 58 }; 59 60 struct stm32_adc_priv; 61 62 /** 63 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 64 * @regs: common registers for all instances 65 * @clk_sel: clock selection routine 66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 67 * @has_syscfg: SYSCFG capability flags 68 */ 69 struct stm32_adc_priv_cfg { 70 const struct stm32_adc_common_regs *regs; 71 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 72 u32 max_clk_rate_hz; 73 unsigned int has_syscfg; 74 }; 75 76 /** 77 * struct stm32_adc_priv - stm32 ADC core private data 78 * @irq: irq(s) for ADC block 79 * @domain: irq domain reference 80 * @aclk: clock reference for the analog circuitry 81 * @bclk: bus clock common for all ADCs, depends on part used 82 * @max_clk_rate: desired maximum clock rate 83 * @booster: booster supply reference 84 * @vdd: vdd supply reference 85 * @vdda: vdda analog supply reference 86 * @vref: regulator reference 87 * @vdd_uv: vdd supply voltage (microvolts) 88 * @vdda_uv: vdda supply voltage (microvolts) 89 * @cfg: compatible configuration data 90 * @common: common data for all ADC instances 91 * @ccr_bak: backup CCR in low power mode 92 * @syscfg: reference to syscon, system control registers 93 */ 94 struct stm32_adc_priv { 95 int irq[STM32_ADC_MAX_ADCS]; 96 struct irq_domain *domain; 97 struct clk *aclk; 98 struct clk *bclk; 99 u32 max_clk_rate; 100 struct regulator *booster; 101 struct regulator *vdd; 102 struct regulator *vdda; 103 struct regulator *vref; 104 int vdd_uv; 105 int vdda_uv; 106 const struct stm32_adc_priv_cfg *cfg; 107 struct stm32_adc_common common; 108 u32 ccr_bak; 109 struct regmap *syscfg; 110 }; 111 112 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 113 { 114 return container_of(com, struct stm32_adc_priv, common); 115 } 116 117 /* STM32F4 ADC internal common clock prescaler division ratios */ 118 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 119 120 /** 121 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 122 * @pdev: platform device 123 * @priv: stm32 ADC core private data 124 * Select clock prescaler used for analog conversions, before using ADC. 125 */ 126 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 127 struct stm32_adc_priv *priv) 128 { 129 unsigned long rate; 130 u32 val; 131 int i; 132 133 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 134 if (!priv->aclk) { 135 dev_err(&pdev->dev, "No 'adc' clock found\n"); 136 return -ENOENT; 137 } 138 139 rate = clk_get_rate(priv->aclk); 140 if (!rate) { 141 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 142 return -EINVAL; 143 } 144 145 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 146 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 147 break; 148 } 149 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 150 dev_err(&pdev->dev, "adc clk selection failed\n"); 151 return -EINVAL; 152 } 153 154 priv->common.rate = rate / stm32f4_pclk_div[i]; 155 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 156 val &= ~STM32F4_ADC_ADCPRE_MASK; 157 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 158 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 159 160 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 161 priv->common.rate / 1000); 162 163 return 0; 164 } 165 166 /** 167 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 168 * @ckmode: ADC clock mode, Async or sync with prescaler. 169 * @presc: prescaler bitfield for async clock mode 170 * @div: prescaler division ratio 171 */ 172 struct stm32h7_adc_ck_spec { 173 u32 ckmode; 174 u32 presc; 175 int div; 176 }; 177 178 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 179 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 180 { 0, 0, 1 }, 181 { 0, 1, 2 }, 182 { 0, 2, 4 }, 183 { 0, 3, 6 }, 184 { 0, 4, 8 }, 185 { 0, 5, 10 }, 186 { 0, 6, 12 }, 187 { 0, 7, 16 }, 188 { 0, 8, 32 }, 189 { 0, 9, 64 }, 190 { 0, 10, 128 }, 191 { 0, 11, 256 }, 192 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 193 { 1, 0, 1 }, 194 { 2, 0, 2 }, 195 { 3, 0, 4 }, 196 }; 197 198 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 199 struct stm32_adc_priv *priv) 200 { 201 u32 ckmode, presc, val; 202 unsigned long rate; 203 int i, div; 204 205 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 206 if (!priv->bclk) { 207 dev_err(&pdev->dev, "No 'bus' clock found\n"); 208 return -ENOENT; 209 } 210 211 /* 212 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 213 * So, choice is to have bus clock mandatory and adc clock optional. 214 * If optional 'adc' clock has been found, then try to use it first. 215 */ 216 if (priv->aclk) { 217 /* 218 * Asynchronous clock modes (e.g. ckmode == 0) 219 * From spec: PLL output musn't exceed max rate 220 */ 221 rate = clk_get_rate(priv->aclk); 222 if (!rate) { 223 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 224 return -EINVAL; 225 } 226 227 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 228 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 229 presc = stm32h7_adc_ckmodes_spec[i].presc; 230 div = stm32h7_adc_ckmodes_spec[i].div; 231 232 if (ckmode) 233 continue; 234 235 if ((rate / div) <= priv->max_clk_rate) 236 goto out; 237 } 238 } 239 240 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 241 rate = clk_get_rate(priv->bclk); 242 if (!rate) { 243 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 244 return -EINVAL; 245 } 246 247 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 248 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 249 presc = stm32h7_adc_ckmodes_spec[i].presc; 250 div = stm32h7_adc_ckmodes_spec[i].div; 251 252 if (!ckmode) 253 continue; 254 255 if ((rate / div) <= priv->max_clk_rate) 256 goto out; 257 } 258 259 dev_err(&pdev->dev, "adc clk selection failed\n"); 260 return -EINVAL; 261 262 out: 263 /* rate used later by each ADC instance to control BOOST mode */ 264 priv->common.rate = rate / div; 265 266 /* Set common clock mode and prescaler */ 267 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 268 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 269 val |= ckmode << STM32H7_CKMODE_SHIFT; 270 val |= presc << STM32H7_PRESC_SHIFT; 271 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 272 273 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 274 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 275 276 return 0; 277 } 278 279 /* STM32F4 common registers definitions */ 280 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 281 .csr = STM32F4_ADC_CSR, 282 .ccr = STM32F4_ADC_CCR, 283 .eoc1_msk = STM32F4_EOC1, 284 .eoc2_msk = STM32F4_EOC2, 285 .eoc3_msk = STM32F4_EOC3, 286 .ier = STM32F4_ADC_CR1, 287 .eocie_msk = STM32F4_EOCIE, 288 }; 289 290 /* STM32H7 common registers definitions */ 291 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 292 .csr = STM32H7_ADC_CSR, 293 .ccr = STM32H7_ADC_CCR, 294 .eoc1_msk = STM32H7_EOC_MST, 295 .eoc2_msk = STM32H7_EOC_SLV, 296 .ier = STM32H7_ADC_IER, 297 .eocie_msk = STM32H7_EOCIE, 298 }; 299 300 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 301 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 302 }; 303 304 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 305 unsigned int adc) 306 { 307 u32 ier, offset = stm32_adc_offset[adc]; 308 309 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 310 311 return ier & priv->cfg->regs->eocie_msk; 312 } 313 314 /* ADC common interrupt for all instances */ 315 static void stm32_adc_irq_handler(struct irq_desc *desc) 316 { 317 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 318 struct irq_chip *chip = irq_desc_get_chip(desc); 319 u32 status; 320 321 chained_irq_enter(chip, desc); 322 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 323 324 /* 325 * End of conversion may be handled by using IRQ or DMA. There may be a 326 * race here when two conversions complete at the same time on several 327 * ADCs. EOC may be read 'set' for several ADCs, with: 328 * - an ADC configured to use DMA (EOC triggers the DMA request, and 329 * is then automatically cleared by DR read in hardware) 330 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 331 * be called in this case) 332 * So both EOC status bit in CSR and EOCIE control bit must be checked 333 * before invoking the interrupt handler (e.g. call ISR only for 334 * IRQ-enabled ADCs). 335 */ 336 if (status & priv->cfg->regs->eoc1_msk && 337 stm32_adc_eoc_enabled(priv, 0)) 338 generic_handle_irq(irq_find_mapping(priv->domain, 0)); 339 340 if (status & priv->cfg->regs->eoc2_msk && 341 stm32_adc_eoc_enabled(priv, 1)) 342 generic_handle_irq(irq_find_mapping(priv->domain, 1)); 343 344 if (status & priv->cfg->regs->eoc3_msk && 345 stm32_adc_eoc_enabled(priv, 2)) 346 generic_handle_irq(irq_find_mapping(priv->domain, 2)); 347 348 chained_irq_exit(chip, desc); 349 }; 350 351 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 352 irq_hw_number_t hwirq) 353 { 354 irq_set_chip_data(irq, d->host_data); 355 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 356 357 return 0; 358 } 359 360 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 361 { 362 irq_set_chip_and_handler(irq, NULL, NULL); 363 irq_set_chip_data(irq, NULL); 364 } 365 366 static const struct irq_domain_ops stm32_adc_domain_ops = { 367 .map = stm32_adc_domain_map, 368 .unmap = stm32_adc_domain_unmap, 369 .xlate = irq_domain_xlate_onecell, 370 }; 371 372 static int stm32_adc_irq_probe(struct platform_device *pdev, 373 struct stm32_adc_priv *priv) 374 { 375 struct device_node *np = pdev->dev.of_node; 376 unsigned int i; 377 378 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 379 priv->irq[i] = platform_get_irq(pdev, i); 380 if (priv->irq[i] < 0) { 381 /* 382 * At least one interrupt must be provided, make others 383 * optional: 384 * - stm32f4/h7 shares a common interrupt. 385 * - stm32mp1, has one line per ADC (either for ADC1, 386 * ADC2 or both). 387 */ 388 if (i && priv->irq[i] == -ENXIO) 389 continue; 390 391 return priv->irq[i]; 392 } 393 } 394 395 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 396 &stm32_adc_domain_ops, 397 priv); 398 if (!priv->domain) { 399 dev_err(&pdev->dev, "Failed to add irq domain\n"); 400 return -ENOMEM; 401 } 402 403 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 404 if (priv->irq[i] < 0) 405 continue; 406 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 407 irq_set_handler_data(priv->irq[i], priv); 408 } 409 410 return 0; 411 } 412 413 static void stm32_adc_irq_remove(struct platform_device *pdev, 414 struct stm32_adc_priv *priv) 415 { 416 int hwirq; 417 unsigned int i; 418 419 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 420 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 421 irq_domain_remove(priv->domain); 422 423 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 424 if (priv->irq[i] < 0) 425 continue; 426 irq_set_chained_handler(priv->irq[i], NULL); 427 } 428 } 429 430 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 431 struct device *dev) 432 { 433 int ret; 434 435 /* 436 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 437 * switches (via PCSEL) which have reduced performances when their 438 * supply is below 2.7V (vdda by default): 439 * - Voltage booster can be used, to get full ADC performances 440 * (increases power consumption). 441 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 442 * 443 * Recommended settings for ANASWVDD and EN_BOOSTER: 444 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 445 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 446 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 447 */ 448 if (priv->vdda_uv < 2700000) { 449 if (priv->syscfg && priv->vdd_uv > 2700000) { 450 ret = regulator_enable(priv->vdd); 451 if (ret < 0) { 452 dev_err(dev, "vdd enable failed %d\n", ret); 453 return ret; 454 } 455 456 ret = regmap_write(priv->syscfg, 457 STM32MP1_SYSCFG_PMCSETR, 458 STM32MP1_SYSCFG_ANASWVDD_MASK); 459 if (ret < 0) { 460 regulator_disable(priv->vdd); 461 dev_err(dev, "vdd select failed, %d\n", ret); 462 return ret; 463 } 464 dev_dbg(dev, "analog switches supplied by vdd\n"); 465 466 return 0; 467 } 468 469 if (priv->booster) { 470 /* 471 * This is optional, as this is a trade-off between 472 * analog performance and power consumption. 473 */ 474 ret = regulator_enable(priv->booster); 475 if (ret < 0) { 476 dev_err(dev, "booster enable failed %d\n", ret); 477 return ret; 478 } 479 dev_dbg(dev, "analog switches supplied by booster\n"); 480 481 return 0; 482 } 483 } 484 485 /* Fallback using vdda (default), nothing to do */ 486 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 487 priv->vdda_uv); 488 489 return 0; 490 } 491 492 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 493 { 494 if (priv->vdda_uv < 2700000) { 495 if (priv->syscfg && priv->vdd_uv > 2700000) { 496 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 497 STM32MP1_SYSCFG_ANASWVDD_MASK); 498 regulator_disable(priv->vdd); 499 return; 500 } 501 if (priv->booster) 502 regulator_disable(priv->booster); 503 } 504 } 505 506 static int stm32_adc_core_hw_start(struct device *dev) 507 { 508 struct stm32_adc_common *common = dev_get_drvdata(dev); 509 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 510 int ret; 511 512 ret = regulator_enable(priv->vdda); 513 if (ret < 0) { 514 dev_err(dev, "vdda enable failed %d\n", ret); 515 return ret; 516 } 517 518 ret = regulator_get_voltage(priv->vdda); 519 if (ret < 0) { 520 dev_err(dev, "vdda get voltage failed, %d\n", ret); 521 goto err_vdda_disable; 522 } 523 priv->vdda_uv = ret; 524 525 ret = stm32_adc_core_switches_supply_en(priv, dev); 526 if (ret < 0) 527 goto err_vdda_disable; 528 529 ret = regulator_enable(priv->vref); 530 if (ret < 0) { 531 dev_err(dev, "vref enable failed\n"); 532 goto err_switches_dis; 533 } 534 535 if (priv->bclk) { 536 ret = clk_prepare_enable(priv->bclk); 537 if (ret < 0) { 538 dev_err(dev, "bus clk enable failed\n"); 539 goto err_regulator_disable; 540 } 541 } 542 543 if (priv->aclk) { 544 ret = clk_prepare_enable(priv->aclk); 545 if (ret < 0) { 546 dev_err(dev, "adc clk enable failed\n"); 547 goto err_bclk_disable; 548 } 549 } 550 551 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 552 553 return 0; 554 555 err_bclk_disable: 556 if (priv->bclk) 557 clk_disable_unprepare(priv->bclk); 558 err_regulator_disable: 559 regulator_disable(priv->vref); 560 err_switches_dis: 561 stm32_adc_core_switches_supply_dis(priv); 562 err_vdda_disable: 563 regulator_disable(priv->vdda); 564 565 return ret; 566 } 567 568 static void stm32_adc_core_hw_stop(struct device *dev) 569 { 570 struct stm32_adc_common *common = dev_get_drvdata(dev); 571 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 572 573 /* Backup CCR that may be lost (depends on power state to achieve) */ 574 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 575 if (priv->aclk) 576 clk_disable_unprepare(priv->aclk); 577 if (priv->bclk) 578 clk_disable_unprepare(priv->bclk); 579 regulator_disable(priv->vref); 580 stm32_adc_core_switches_supply_dis(priv); 581 regulator_disable(priv->vdda); 582 } 583 584 static int stm32_adc_core_switches_probe(struct device *dev, 585 struct stm32_adc_priv *priv) 586 { 587 struct device_node *np = dev->of_node; 588 int ret; 589 590 /* Analog switches supply can be controlled by syscfg (optional) */ 591 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 592 if (IS_ERR(priv->syscfg)) { 593 ret = PTR_ERR(priv->syscfg); 594 if (ret != -ENODEV) { 595 if (ret != -EPROBE_DEFER) 596 dev_err(dev, "Can't probe syscfg: %d\n", ret); 597 return ret; 598 } 599 priv->syscfg = NULL; 600 } 601 602 /* Booster can be used to supply analog switches (optional) */ 603 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 604 of_property_read_bool(np, "booster-supply")) { 605 priv->booster = devm_regulator_get_optional(dev, "booster"); 606 if (IS_ERR(priv->booster)) { 607 ret = PTR_ERR(priv->booster); 608 if (ret != -ENODEV) { 609 if (ret != -EPROBE_DEFER) 610 dev_err(dev, "can't get booster %d\n", 611 ret); 612 return ret; 613 } 614 priv->booster = NULL; 615 } 616 } 617 618 /* Vdd can be used to supply analog switches (optional) */ 619 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 620 of_property_read_bool(np, "vdd-supply")) { 621 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 622 if (IS_ERR(priv->vdd)) { 623 ret = PTR_ERR(priv->vdd); 624 if (ret != -ENODEV) { 625 if (ret != -EPROBE_DEFER) 626 dev_err(dev, "can't get vdd %d\n", ret); 627 return ret; 628 } 629 priv->vdd = NULL; 630 } 631 } 632 633 if (priv->vdd) { 634 ret = regulator_enable(priv->vdd); 635 if (ret < 0) { 636 dev_err(dev, "vdd enable failed %d\n", ret); 637 return ret; 638 } 639 640 ret = regulator_get_voltage(priv->vdd); 641 if (ret < 0) { 642 dev_err(dev, "vdd get voltage failed %d\n", ret); 643 regulator_disable(priv->vdd); 644 return ret; 645 } 646 priv->vdd_uv = ret; 647 648 regulator_disable(priv->vdd); 649 } 650 651 return 0; 652 } 653 654 static int stm32_adc_probe(struct platform_device *pdev) 655 { 656 struct stm32_adc_priv *priv; 657 struct device *dev = &pdev->dev; 658 struct device_node *np = pdev->dev.of_node; 659 struct resource *res; 660 u32 max_rate; 661 int ret; 662 663 if (!pdev->dev.of_node) 664 return -ENODEV; 665 666 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 667 if (!priv) 668 return -ENOMEM; 669 platform_set_drvdata(pdev, &priv->common); 670 671 priv->cfg = (const struct stm32_adc_priv_cfg *) 672 of_match_device(dev->driver->of_match_table, dev)->data; 673 674 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 675 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 676 if (IS_ERR(priv->common.base)) 677 return PTR_ERR(priv->common.base); 678 priv->common.phys_base = res->start; 679 680 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 681 if (IS_ERR(priv->vdda)) { 682 ret = PTR_ERR(priv->vdda); 683 if (ret != -EPROBE_DEFER) 684 dev_err(&pdev->dev, "vdda get failed, %d\n", ret); 685 return ret; 686 } 687 688 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 689 if (IS_ERR(priv->vref)) { 690 ret = PTR_ERR(priv->vref); 691 dev_err(&pdev->dev, "vref get failed, %d\n", ret); 692 return ret; 693 } 694 695 priv->aclk = devm_clk_get(&pdev->dev, "adc"); 696 if (IS_ERR(priv->aclk)) { 697 ret = PTR_ERR(priv->aclk); 698 if (ret != -ENOENT) { 699 dev_err(&pdev->dev, "Can't get 'adc' clock\n"); 700 return ret; 701 } 702 priv->aclk = NULL; 703 } 704 705 priv->bclk = devm_clk_get(&pdev->dev, "bus"); 706 if (IS_ERR(priv->bclk)) { 707 ret = PTR_ERR(priv->bclk); 708 if (ret != -ENOENT) { 709 dev_err(&pdev->dev, "Can't get 'bus' clock\n"); 710 return ret; 711 } 712 priv->bclk = NULL; 713 } 714 715 ret = stm32_adc_core_switches_probe(dev, priv); 716 if (ret) 717 return ret; 718 719 pm_runtime_get_noresume(dev); 720 pm_runtime_set_active(dev); 721 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 722 pm_runtime_use_autosuspend(dev); 723 pm_runtime_enable(dev); 724 725 ret = stm32_adc_core_hw_start(dev); 726 if (ret) 727 goto err_pm_stop; 728 729 ret = regulator_get_voltage(priv->vref); 730 if (ret < 0) { 731 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 732 goto err_hw_stop; 733 } 734 priv->common.vref_mv = ret / 1000; 735 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 736 737 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 738 &max_rate); 739 if (!ret) 740 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 741 else 742 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 743 744 ret = priv->cfg->clk_sel(pdev, priv); 745 if (ret < 0) 746 goto err_hw_stop; 747 748 ret = stm32_adc_irq_probe(pdev, priv); 749 if (ret < 0) 750 goto err_hw_stop; 751 752 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 753 if (ret < 0) { 754 dev_err(&pdev->dev, "failed to populate DT children\n"); 755 goto err_irq_remove; 756 } 757 758 pm_runtime_mark_last_busy(dev); 759 pm_runtime_put_autosuspend(dev); 760 761 return 0; 762 763 err_irq_remove: 764 stm32_adc_irq_remove(pdev, priv); 765 err_hw_stop: 766 stm32_adc_core_hw_stop(dev); 767 err_pm_stop: 768 pm_runtime_disable(dev); 769 pm_runtime_set_suspended(dev); 770 pm_runtime_put_noidle(dev); 771 772 return ret; 773 } 774 775 static int stm32_adc_remove(struct platform_device *pdev) 776 { 777 struct stm32_adc_common *common = platform_get_drvdata(pdev); 778 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 779 780 pm_runtime_get_sync(&pdev->dev); 781 of_platform_depopulate(&pdev->dev); 782 stm32_adc_irq_remove(pdev, priv); 783 stm32_adc_core_hw_stop(&pdev->dev); 784 pm_runtime_disable(&pdev->dev); 785 pm_runtime_set_suspended(&pdev->dev); 786 pm_runtime_put_noidle(&pdev->dev); 787 788 return 0; 789 } 790 791 #if defined(CONFIG_PM) 792 static int stm32_adc_core_runtime_suspend(struct device *dev) 793 { 794 stm32_adc_core_hw_stop(dev); 795 796 return 0; 797 } 798 799 static int stm32_adc_core_runtime_resume(struct device *dev) 800 { 801 return stm32_adc_core_hw_start(dev); 802 } 803 #endif 804 805 static const struct dev_pm_ops stm32_adc_core_pm_ops = { 806 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 807 pm_runtime_force_resume) 808 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend, 809 stm32_adc_core_runtime_resume, 810 NULL) 811 }; 812 813 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 814 .regs = &stm32f4_adc_common_regs, 815 .clk_sel = stm32f4_adc_clk_sel, 816 .max_clk_rate_hz = 36000000, 817 }; 818 819 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 820 .regs = &stm32h7_adc_common_regs, 821 .clk_sel = stm32h7_adc_clk_sel, 822 .max_clk_rate_hz = 36000000, 823 .has_syscfg = HAS_VBOOSTER, 824 }; 825 826 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 827 .regs = &stm32h7_adc_common_regs, 828 .clk_sel = stm32h7_adc_clk_sel, 829 .max_clk_rate_hz = 40000000, 830 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 831 }; 832 833 static const struct of_device_id stm32_adc_of_match[] = { 834 { 835 .compatible = "st,stm32f4-adc-core", 836 .data = (void *)&stm32f4_adc_priv_cfg 837 }, { 838 .compatible = "st,stm32h7-adc-core", 839 .data = (void *)&stm32h7_adc_priv_cfg 840 }, { 841 .compatible = "st,stm32mp1-adc-core", 842 .data = (void *)&stm32mp1_adc_priv_cfg 843 }, { 844 }, 845 }; 846 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 847 848 static struct platform_driver stm32_adc_driver = { 849 .probe = stm32_adc_probe, 850 .remove = stm32_adc_remove, 851 .driver = { 852 .name = "stm32-adc-core", 853 .of_match_table = stm32_adc_of_match, 854 .pm = &stm32_adc_core_pm_ops, 855 }, 856 }; 857 module_platform_driver(stm32_adc_driver); 858 859 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 860 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 861 MODULE_LICENSE("GPL v2"); 862 MODULE_ALIAS("platform:stm32-adc-core"); 863