1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdesc.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 23 #include "stm32-adc-core.h" 24 25 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ 26 #define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 27 #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) 28 29 /* STM32F4_ADC_CSR - bit fields */ 30 #define STM32F4_EOC3 BIT(17) 31 #define STM32F4_EOC2 BIT(9) 32 #define STM32F4_EOC1 BIT(1) 33 34 /* STM32F4_ADC_CCR - bit fields */ 35 #define STM32F4_ADC_ADCPRE_SHIFT 16 36 #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16) 37 38 /* STM32H7 - common registers for all ADC instances */ 39 #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 40 #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) 41 42 /* STM32H7_ADC_CSR - bit fields */ 43 #define STM32H7_EOC_SLV BIT(18) 44 #define STM32H7_EOC_MST BIT(2) 45 46 /* STM32H7_ADC_CCR - bit fields */ 47 #define STM32H7_PRESC_SHIFT 18 48 #define STM32H7_PRESC_MASK GENMASK(21, 18) 49 #define STM32H7_CKMODE_SHIFT 16 50 #define STM32H7_CKMODE_MASK GENMASK(17, 16) 51 52 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 53 54 /** 55 * stm32_adc_common_regs - stm32 common registers, compatible dependent data 56 * @csr: common status register offset 57 * @ccr: common control register offset 58 * @eoc1: adc1 end of conversion flag in @csr 59 * @eoc2: adc2 end of conversion flag in @csr 60 * @eoc3: adc3 end of conversion flag in @csr 61 */ 62 struct stm32_adc_common_regs { 63 u32 csr; 64 u32 ccr; 65 u32 eoc1_msk; 66 u32 eoc2_msk; 67 u32 eoc3_msk; 68 }; 69 70 struct stm32_adc_priv; 71 72 /** 73 * stm32_adc_priv_cfg - stm32 core compatible configuration data 74 * @regs: common registers for all instances 75 * @clk_sel: clock selection routine 76 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 77 */ 78 struct stm32_adc_priv_cfg { 79 const struct stm32_adc_common_regs *regs; 80 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 81 u32 max_clk_rate_hz; 82 }; 83 84 /** 85 * struct stm32_adc_priv - stm32 ADC core private data 86 * @irq: irq(s) for ADC block 87 * @domain: irq domain reference 88 * @aclk: clock reference for the analog circuitry 89 * @bclk: bus clock common for all ADCs, depends on part used 90 * @vref: regulator reference 91 * @cfg: compatible configuration data 92 * @common: common data for all ADC instances 93 * @ccr_bak: backup CCR in low power mode 94 */ 95 struct stm32_adc_priv { 96 int irq[STM32_ADC_MAX_ADCS]; 97 struct irq_domain *domain; 98 struct clk *aclk; 99 struct clk *bclk; 100 struct regulator *vref; 101 const struct stm32_adc_priv_cfg *cfg; 102 struct stm32_adc_common common; 103 u32 ccr_bak; 104 }; 105 106 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 107 { 108 return container_of(com, struct stm32_adc_priv, common); 109 } 110 111 /* STM32F4 ADC internal common clock prescaler division ratios */ 112 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 113 114 /** 115 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 116 * @priv: stm32 ADC core private data 117 * Select clock prescaler used for analog conversions, before using ADC. 118 */ 119 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 120 struct stm32_adc_priv *priv) 121 { 122 unsigned long rate; 123 u32 val; 124 int i; 125 126 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 127 if (!priv->aclk) { 128 dev_err(&pdev->dev, "No 'adc' clock found\n"); 129 return -ENOENT; 130 } 131 132 rate = clk_get_rate(priv->aclk); 133 if (!rate) { 134 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 135 return -EINVAL; 136 } 137 138 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 139 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz) 140 break; 141 } 142 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 143 dev_err(&pdev->dev, "adc clk selection failed\n"); 144 return -EINVAL; 145 } 146 147 priv->common.rate = rate / stm32f4_pclk_div[i]; 148 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 149 val &= ~STM32F4_ADC_ADCPRE_MASK; 150 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 151 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 152 153 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 154 priv->common.rate / 1000); 155 156 return 0; 157 } 158 159 /** 160 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 161 * @ckmode: ADC clock mode, Async or sync with prescaler. 162 * @presc: prescaler bitfield for async clock mode 163 * @div: prescaler division ratio 164 */ 165 struct stm32h7_adc_ck_spec { 166 u32 ckmode; 167 u32 presc; 168 int div; 169 }; 170 171 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 172 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 173 { 0, 0, 1 }, 174 { 0, 1, 2 }, 175 { 0, 2, 4 }, 176 { 0, 3, 6 }, 177 { 0, 4, 8 }, 178 { 0, 5, 10 }, 179 { 0, 6, 12 }, 180 { 0, 7, 16 }, 181 { 0, 8, 32 }, 182 { 0, 9, 64 }, 183 { 0, 10, 128 }, 184 { 0, 11, 256 }, 185 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 186 { 1, 0, 1 }, 187 { 2, 0, 2 }, 188 { 3, 0, 4 }, 189 }; 190 191 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 192 struct stm32_adc_priv *priv) 193 { 194 u32 ckmode, presc, val; 195 unsigned long rate; 196 int i, div; 197 198 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 199 if (!priv->bclk) { 200 dev_err(&pdev->dev, "No 'bus' clock found\n"); 201 return -ENOENT; 202 } 203 204 /* 205 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 206 * So, choice is to have bus clock mandatory and adc clock optional. 207 * If optional 'adc' clock has been found, then try to use it first. 208 */ 209 if (priv->aclk) { 210 /* 211 * Asynchronous clock modes (e.g. ckmode == 0) 212 * From spec: PLL output musn't exceed max rate 213 */ 214 rate = clk_get_rate(priv->aclk); 215 if (!rate) { 216 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 217 return -EINVAL; 218 } 219 220 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 221 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 222 presc = stm32h7_adc_ckmodes_spec[i].presc; 223 div = stm32h7_adc_ckmodes_spec[i].div; 224 225 if (ckmode) 226 continue; 227 228 if ((rate / div) <= priv->cfg->max_clk_rate_hz) 229 goto out; 230 } 231 } 232 233 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 234 rate = clk_get_rate(priv->bclk); 235 if (!rate) { 236 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 237 return -EINVAL; 238 } 239 240 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 241 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 242 presc = stm32h7_adc_ckmodes_spec[i].presc; 243 div = stm32h7_adc_ckmodes_spec[i].div; 244 245 if (!ckmode) 246 continue; 247 248 if ((rate / div) <= priv->cfg->max_clk_rate_hz) 249 goto out; 250 } 251 252 dev_err(&pdev->dev, "adc clk selection failed\n"); 253 return -EINVAL; 254 255 out: 256 /* rate used later by each ADC instance to control BOOST mode */ 257 priv->common.rate = rate / div; 258 259 /* Set common clock mode and prescaler */ 260 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 261 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 262 val |= ckmode << STM32H7_CKMODE_SHIFT; 263 val |= presc << STM32H7_PRESC_SHIFT; 264 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 265 266 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 267 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 268 269 return 0; 270 } 271 272 /* STM32F4 common registers definitions */ 273 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 274 .csr = STM32F4_ADC_CSR, 275 .ccr = STM32F4_ADC_CCR, 276 .eoc1_msk = STM32F4_EOC1, 277 .eoc2_msk = STM32F4_EOC2, 278 .eoc3_msk = STM32F4_EOC3, 279 }; 280 281 /* STM32H7 common registers definitions */ 282 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 283 .csr = STM32H7_ADC_CSR, 284 .ccr = STM32H7_ADC_CCR, 285 .eoc1_msk = STM32H7_EOC_MST, 286 .eoc2_msk = STM32H7_EOC_SLV, 287 }; 288 289 /* ADC common interrupt for all instances */ 290 static void stm32_adc_irq_handler(struct irq_desc *desc) 291 { 292 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 293 struct irq_chip *chip = irq_desc_get_chip(desc); 294 u32 status; 295 296 chained_irq_enter(chip, desc); 297 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 298 299 if (status & priv->cfg->regs->eoc1_msk) 300 generic_handle_irq(irq_find_mapping(priv->domain, 0)); 301 302 if (status & priv->cfg->regs->eoc2_msk) 303 generic_handle_irq(irq_find_mapping(priv->domain, 1)); 304 305 if (status & priv->cfg->regs->eoc3_msk) 306 generic_handle_irq(irq_find_mapping(priv->domain, 2)); 307 308 chained_irq_exit(chip, desc); 309 }; 310 311 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 312 irq_hw_number_t hwirq) 313 { 314 irq_set_chip_data(irq, d->host_data); 315 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 316 317 return 0; 318 } 319 320 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 321 { 322 irq_set_chip_and_handler(irq, NULL, NULL); 323 irq_set_chip_data(irq, NULL); 324 } 325 326 static const struct irq_domain_ops stm32_adc_domain_ops = { 327 .map = stm32_adc_domain_map, 328 .unmap = stm32_adc_domain_unmap, 329 .xlate = irq_domain_xlate_onecell, 330 }; 331 332 static int stm32_adc_irq_probe(struct platform_device *pdev, 333 struct stm32_adc_priv *priv) 334 { 335 struct device_node *np = pdev->dev.of_node; 336 unsigned int i; 337 338 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 339 priv->irq[i] = platform_get_irq(pdev, i); 340 if (priv->irq[i] < 0) { 341 /* 342 * At least one interrupt must be provided, make others 343 * optional: 344 * - stm32f4/h7 shares a common interrupt. 345 * - stm32mp1, has one line per ADC (either for ADC1, 346 * ADC2 or both). 347 */ 348 if (i && priv->irq[i] == -ENXIO) 349 continue; 350 dev_err(&pdev->dev, "failed to get irq\n"); 351 352 return priv->irq[i]; 353 } 354 } 355 356 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 357 &stm32_adc_domain_ops, 358 priv); 359 if (!priv->domain) { 360 dev_err(&pdev->dev, "Failed to add irq domain\n"); 361 return -ENOMEM; 362 } 363 364 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 365 if (priv->irq[i] < 0) 366 continue; 367 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 368 irq_set_handler_data(priv->irq[i], priv); 369 } 370 371 return 0; 372 } 373 374 static void stm32_adc_irq_remove(struct platform_device *pdev, 375 struct stm32_adc_priv *priv) 376 { 377 int hwirq; 378 unsigned int i; 379 380 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 381 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 382 irq_domain_remove(priv->domain); 383 384 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 385 if (priv->irq[i] < 0) 386 continue; 387 irq_set_chained_handler(priv->irq[i], NULL); 388 } 389 } 390 391 static int stm32_adc_core_hw_start(struct device *dev) 392 { 393 struct stm32_adc_common *common = dev_get_drvdata(dev); 394 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 395 int ret; 396 397 ret = regulator_enable(priv->vref); 398 if (ret < 0) { 399 dev_err(dev, "vref enable failed\n"); 400 return ret; 401 } 402 403 if (priv->bclk) { 404 ret = clk_prepare_enable(priv->bclk); 405 if (ret < 0) { 406 dev_err(dev, "bus clk enable failed\n"); 407 goto err_regulator_disable; 408 } 409 } 410 411 if (priv->aclk) { 412 ret = clk_prepare_enable(priv->aclk); 413 if (ret < 0) { 414 dev_err(dev, "adc clk enable failed\n"); 415 goto err_bclk_disable; 416 } 417 } 418 419 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 420 421 return 0; 422 423 err_bclk_disable: 424 if (priv->bclk) 425 clk_disable_unprepare(priv->bclk); 426 err_regulator_disable: 427 regulator_disable(priv->vref); 428 429 return ret; 430 } 431 432 static void stm32_adc_core_hw_stop(struct device *dev) 433 { 434 struct stm32_adc_common *common = dev_get_drvdata(dev); 435 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 436 437 /* Backup CCR that may be lost (depends on power state to achieve) */ 438 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 439 if (priv->aclk) 440 clk_disable_unprepare(priv->aclk); 441 if (priv->bclk) 442 clk_disable_unprepare(priv->bclk); 443 regulator_disable(priv->vref); 444 } 445 446 static int stm32_adc_probe(struct platform_device *pdev) 447 { 448 struct stm32_adc_priv *priv; 449 struct device *dev = &pdev->dev; 450 struct device_node *np = pdev->dev.of_node; 451 struct resource *res; 452 int ret; 453 454 if (!pdev->dev.of_node) 455 return -ENODEV; 456 457 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 458 if (!priv) 459 return -ENOMEM; 460 platform_set_drvdata(pdev, &priv->common); 461 462 priv->cfg = (const struct stm32_adc_priv_cfg *) 463 of_match_device(dev->driver->of_match_table, dev)->data; 464 465 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 466 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 467 if (IS_ERR(priv->common.base)) 468 return PTR_ERR(priv->common.base); 469 priv->common.phys_base = res->start; 470 471 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 472 if (IS_ERR(priv->vref)) { 473 ret = PTR_ERR(priv->vref); 474 dev_err(&pdev->dev, "vref get failed, %d\n", ret); 475 return ret; 476 } 477 478 priv->aclk = devm_clk_get(&pdev->dev, "adc"); 479 if (IS_ERR(priv->aclk)) { 480 ret = PTR_ERR(priv->aclk); 481 if (ret != -ENOENT) { 482 dev_err(&pdev->dev, "Can't get 'adc' clock\n"); 483 return ret; 484 } 485 priv->aclk = NULL; 486 } 487 488 priv->bclk = devm_clk_get(&pdev->dev, "bus"); 489 if (IS_ERR(priv->bclk)) { 490 ret = PTR_ERR(priv->bclk); 491 if (ret != -ENOENT) { 492 dev_err(&pdev->dev, "Can't get 'bus' clock\n"); 493 return ret; 494 } 495 priv->bclk = NULL; 496 } 497 498 pm_runtime_get_noresume(dev); 499 pm_runtime_set_active(dev); 500 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 501 pm_runtime_use_autosuspend(dev); 502 pm_runtime_enable(dev); 503 504 ret = stm32_adc_core_hw_start(dev); 505 if (ret) 506 goto err_pm_stop; 507 508 ret = regulator_get_voltage(priv->vref); 509 if (ret < 0) { 510 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 511 goto err_hw_stop; 512 } 513 priv->common.vref_mv = ret / 1000; 514 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 515 516 ret = priv->cfg->clk_sel(pdev, priv); 517 if (ret < 0) 518 goto err_hw_stop; 519 520 ret = stm32_adc_irq_probe(pdev, priv); 521 if (ret < 0) 522 goto err_hw_stop; 523 524 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 525 if (ret < 0) { 526 dev_err(&pdev->dev, "failed to populate DT children\n"); 527 goto err_irq_remove; 528 } 529 530 pm_runtime_mark_last_busy(dev); 531 pm_runtime_put_autosuspend(dev); 532 533 return 0; 534 535 err_irq_remove: 536 stm32_adc_irq_remove(pdev, priv); 537 err_hw_stop: 538 stm32_adc_core_hw_stop(dev); 539 err_pm_stop: 540 pm_runtime_disable(dev); 541 pm_runtime_set_suspended(dev); 542 pm_runtime_put_noidle(dev); 543 544 return ret; 545 } 546 547 static int stm32_adc_remove(struct platform_device *pdev) 548 { 549 struct stm32_adc_common *common = platform_get_drvdata(pdev); 550 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 551 552 pm_runtime_get_sync(&pdev->dev); 553 of_platform_depopulate(&pdev->dev); 554 stm32_adc_irq_remove(pdev, priv); 555 stm32_adc_core_hw_stop(&pdev->dev); 556 pm_runtime_disable(&pdev->dev); 557 pm_runtime_set_suspended(&pdev->dev); 558 pm_runtime_put_noidle(&pdev->dev); 559 560 return 0; 561 } 562 563 #if defined(CONFIG_PM) 564 static int stm32_adc_core_runtime_suspend(struct device *dev) 565 { 566 stm32_adc_core_hw_stop(dev); 567 568 return 0; 569 } 570 571 static int stm32_adc_core_runtime_resume(struct device *dev) 572 { 573 return stm32_adc_core_hw_start(dev); 574 } 575 #endif 576 577 static const struct dev_pm_ops stm32_adc_core_pm_ops = { 578 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 579 pm_runtime_force_resume) 580 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend, 581 stm32_adc_core_runtime_resume, 582 NULL) 583 }; 584 585 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 586 .regs = &stm32f4_adc_common_regs, 587 .clk_sel = stm32f4_adc_clk_sel, 588 .max_clk_rate_hz = 36000000, 589 }; 590 591 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 592 .regs = &stm32h7_adc_common_regs, 593 .clk_sel = stm32h7_adc_clk_sel, 594 .max_clk_rate_hz = 36000000, 595 }; 596 597 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 598 .regs = &stm32h7_adc_common_regs, 599 .clk_sel = stm32h7_adc_clk_sel, 600 .max_clk_rate_hz = 40000000, 601 }; 602 603 static const struct of_device_id stm32_adc_of_match[] = { 604 { 605 .compatible = "st,stm32f4-adc-core", 606 .data = (void *)&stm32f4_adc_priv_cfg 607 }, { 608 .compatible = "st,stm32h7-adc-core", 609 .data = (void *)&stm32h7_adc_priv_cfg 610 }, { 611 .compatible = "st,stm32mp1-adc-core", 612 .data = (void *)&stm32mp1_adc_priv_cfg 613 }, { 614 }, 615 }; 616 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 617 618 static struct platform_driver stm32_adc_driver = { 619 .probe = stm32_adc_probe, 620 .remove = stm32_adc_remove, 621 .driver = { 622 .name = "stm32-adc-core", 623 .of_match_table = stm32_adc_of_match, 624 .pm = &stm32_adc_core_pm_ops, 625 }, 626 }; 627 module_platform_driver(stm32_adc_driver); 628 629 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 630 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 631 MODULE_LICENSE("GPL v2"); 632 MODULE_ALIAS("platform:stm32-adc-core"); 633