1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdesc.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include "stm32-adc-core.h" 26 27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 28 29 /* SYSCFG registers */ 30 #define STM32MP1_SYSCFG_PMCSETR 0x04 31 #define STM32MP1_SYSCFG_PMCCLRR 0x44 32 33 /* SYSCFG bit fields */ 34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 35 36 /* SYSCFG capability flags */ 37 #define HAS_VBOOSTER BIT(0) 38 #define HAS_ANASWVDD BIT(1) 39 40 /** 41 * struct stm32_adc_common_regs - stm32 common registers 42 * @csr: common status register offset 43 * @ccr: common control register offset 44 * @eoc1_msk: adc1 end of conversion flag in @csr 45 * @eoc2_msk: adc2 end of conversion flag in @csr 46 * @eoc3_msk: adc3 end of conversion flag in @csr 47 * @ier: interrupt enable register offset for each adc 48 * @eocie_msk: end of conversion interrupt enable mask in @ier 49 */ 50 struct stm32_adc_common_regs { 51 u32 csr; 52 u32 ccr; 53 u32 eoc1_msk; 54 u32 eoc2_msk; 55 u32 eoc3_msk; 56 u32 ier; 57 u32 eocie_msk; 58 }; 59 60 struct stm32_adc_priv; 61 62 /** 63 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 64 * @regs: common registers for all instances 65 * @clk_sel: clock selection routine 66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 67 * @has_syscfg: SYSCFG capability flags 68 * @num_irqs: number of interrupt lines 69 */ 70 struct stm32_adc_priv_cfg { 71 const struct stm32_adc_common_regs *regs; 72 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 73 u32 max_clk_rate_hz; 74 unsigned int has_syscfg; 75 unsigned int num_irqs; 76 }; 77 78 /** 79 * struct stm32_adc_priv - stm32 ADC core private data 80 * @irq: irq(s) for ADC block 81 * @domain: irq domain reference 82 * @aclk: clock reference for the analog circuitry 83 * @bclk: bus clock common for all ADCs, depends on part used 84 * @max_clk_rate: desired maximum clock rate 85 * @booster: booster supply reference 86 * @vdd: vdd supply reference 87 * @vdda: vdda analog supply reference 88 * @vref: regulator reference 89 * @vdd_uv: vdd supply voltage (microvolts) 90 * @vdda_uv: vdda supply voltage (microvolts) 91 * @cfg: compatible configuration data 92 * @common: common data for all ADC instances 93 * @ccr_bak: backup CCR in low power mode 94 * @syscfg: reference to syscon, system control registers 95 */ 96 struct stm32_adc_priv { 97 int irq[STM32_ADC_MAX_ADCS]; 98 struct irq_domain *domain; 99 struct clk *aclk; 100 struct clk *bclk; 101 u32 max_clk_rate; 102 struct regulator *booster; 103 struct regulator *vdd; 104 struct regulator *vdda; 105 struct regulator *vref; 106 int vdd_uv; 107 int vdda_uv; 108 const struct stm32_adc_priv_cfg *cfg; 109 struct stm32_adc_common common; 110 u32 ccr_bak; 111 struct regmap *syscfg; 112 }; 113 114 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 115 { 116 return container_of(com, struct stm32_adc_priv, common); 117 } 118 119 /* STM32F4 ADC internal common clock prescaler division ratios */ 120 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 121 122 /** 123 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 124 * @pdev: platform device 125 * @priv: stm32 ADC core private data 126 * Select clock prescaler used for analog conversions, before using ADC. 127 */ 128 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 129 struct stm32_adc_priv *priv) 130 { 131 unsigned long rate; 132 u32 val; 133 int i; 134 135 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 136 if (!priv->aclk) { 137 dev_err(&pdev->dev, "No 'adc' clock found\n"); 138 return -ENOENT; 139 } 140 141 rate = clk_get_rate(priv->aclk); 142 if (!rate) { 143 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 144 return -EINVAL; 145 } 146 147 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 148 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 149 break; 150 } 151 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 152 dev_err(&pdev->dev, "adc clk selection failed\n"); 153 return -EINVAL; 154 } 155 156 priv->common.rate = rate / stm32f4_pclk_div[i]; 157 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 158 val &= ~STM32F4_ADC_ADCPRE_MASK; 159 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 160 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 161 162 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 163 priv->common.rate / 1000); 164 165 return 0; 166 } 167 168 /** 169 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 170 * @ckmode: ADC clock mode, Async or sync with prescaler. 171 * @presc: prescaler bitfield for async clock mode 172 * @div: prescaler division ratio 173 */ 174 struct stm32h7_adc_ck_spec { 175 u32 ckmode; 176 u32 presc; 177 int div; 178 }; 179 180 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 181 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 182 { 0, 0, 1 }, 183 { 0, 1, 2 }, 184 { 0, 2, 4 }, 185 { 0, 3, 6 }, 186 { 0, 4, 8 }, 187 { 0, 5, 10 }, 188 { 0, 6, 12 }, 189 { 0, 7, 16 }, 190 { 0, 8, 32 }, 191 { 0, 9, 64 }, 192 { 0, 10, 128 }, 193 { 0, 11, 256 }, 194 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 195 { 1, 0, 1 }, 196 { 2, 0, 2 }, 197 { 3, 0, 4 }, 198 }; 199 200 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 201 struct stm32_adc_priv *priv) 202 { 203 u32 ckmode, presc, val; 204 unsigned long rate; 205 int i, div; 206 207 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 208 if (!priv->bclk) { 209 dev_err(&pdev->dev, "No 'bus' clock found\n"); 210 return -ENOENT; 211 } 212 213 /* 214 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 215 * So, choice is to have bus clock mandatory and adc clock optional. 216 * If optional 'adc' clock has been found, then try to use it first. 217 */ 218 if (priv->aclk) { 219 /* 220 * Asynchronous clock modes (e.g. ckmode == 0) 221 * From spec: PLL output musn't exceed max rate 222 */ 223 rate = clk_get_rate(priv->aclk); 224 if (!rate) { 225 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 226 return -EINVAL; 227 } 228 229 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 230 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 231 presc = stm32h7_adc_ckmodes_spec[i].presc; 232 div = stm32h7_adc_ckmodes_spec[i].div; 233 234 if (ckmode) 235 continue; 236 237 if ((rate / div) <= priv->max_clk_rate) 238 goto out; 239 } 240 } 241 242 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 243 rate = clk_get_rate(priv->bclk); 244 if (!rate) { 245 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 246 return -EINVAL; 247 } 248 249 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 250 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 251 presc = stm32h7_adc_ckmodes_spec[i].presc; 252 div = stm32h7_adc_ckmodes_spec[i].div; 253 254 if (!ckmode) 255 continue; 256 257 if ((rate / div) <= priv->max_clk_rate) 258 goto out; 259 } 260 261 dev_err(&pdev->dev, "adc clk selection failed\n"); 262 return -EINVAL; 263 264 out: 265 /* rate used later by each ADC instance to control BOOST mode */ 266 priv->common.rate = rate / div; 267 268 /* Set common clock mode and prescaler */ 269 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 270 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 271 val |= ckmode << STM32H7_CKMODE_SHIFT; 272 val |= presc << STM32H7_PRESC_SHIFT; 273 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 274 275 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 276 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 277 278 return 0; 279 } 280 281 /* STM32F4 common registers definitions */ 282 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 283 .csr = STM32F4_ADC_CSR, 284 .ccr = STM32F4_ADC_CCR, 285 .eoc1_msk = STM32F4_EOC1 | STM32F4_OVR1, 286 .eoc2_msk = STM32F4_EOC2 | STM32F4_OVR2, 287 .eoc3_msk = STM32F4_EOC3 | STM32F4_OVR3, 288 .ier = STM32F4_ADC_CR1, 289 .eocie_msk = STM32F4_EOCIE | STM32F4_OVRIE, 290 }; 291 292 /* STM32H7 common registers definitions */ 293 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 294 .csr = STM32H7_ADC_CSR, 295 .ccr = STM32H7_ADC_CCR, 296 .eoc1_msk = STM32H7_EOC_MST | STM32H7_OVR_MST, 297 .eoc2_msk = STM32H7_EOC_SLV | STM32H7_OVR_SLV, 298 .ier = STM32H7_ADC_IER, 299 .eocie_msk = STM32H7_EOCIE | STM32H7_OVRIE, 300 }; 301 302 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 303 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 304 }; 305 306 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 307 unsigned int adc) 308 { 309 u32 ier, offset = stm32_adc_offset[adc]; 310 311 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 312 313 return ier & priv->cfg->regs->eocie_msk; 314 } 315 316 /* ADC common interrupt for all instances */ 317 static void stm32_adc_irq_handler(struct irq_desc *desc) 318 { 319 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 320 struct irq_chip *chip = irq_desc_get_chip(desc); 321 u32 status; 322 323 chained_irq_enter(chip, desc); 324 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 325 326 /* 327 * End of conversion may be handled by using IRQ or DMA. There may be a 328 * race here when two conversions complete at the same time on several 329 * ADCs. EOC may be read 'set' for several ADCs, with: 330 * - an ADC configured to use DMA (EOC triggers the DMA request, and 331 * is then automatically cleared by DR read in hardware) 332 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 333 * be called in this case) 334 * So both EOC status bit in CSR and EOCIE control bit must be checked 335 * before invoking the interrupt handler (e.g. call ISR only for 336 * IRQ-enabled ADCs). 337 */ 338 if (status & priv->cfg->regs->eoc1_msk && 339 stm32_adc_eoc_enabled(priv, 0)) 340 generic_handle_irq(irq_find_mapping(priv->domain, 0)); 341 342 if (status & priv->cfg->regs->eoc2_msk && 343 stm32_adc_eoc_enabled(priv, 1)) 344 generic_handle_irq(irq_find_mapping(priv->domain, 1)); 345 346 if (status & priv->cfg->regs->eoc3_msk && 347 stm32_adc_eoc_enabled(priv, 2)) 348 generic_handle_irq(irq_find_mapping(priv->domain, 2)); 349 350 chained_irq_exit(chip, desc); 351 }; 352 353 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 354 irq_hw_number_t hwirq) 355 { 356 irq_set_chip_data(irq, d->host_data); 357 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 358 359 return 0; 360 } 361 362 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 363 { 364 irq_set_chip_and_handler(irq, NULL, NULL); 365 irq_set_chip_data(irq, NULL); 366 } 367 368 static const struct irq_domain_ops stm32_adc_domain_ops = { 369 .map = stm32_adc_domain_map, 370 .unmap = stm32_adc_domain_unmap, 371 .xlate = irq_domain_xlate_onecell, 372 }; 373 374 static int stm32_adc_irq_probe(struct platform_device *pdev, 375 struct stm32_adc_priv *priv) 376 { 377 struct device_node *np = pdev->dev.of_node; 378 unsigned int i; 379 380 /* 381 * Interrupt(s) must be provided, depending on the compatible: 382 * - stm32f4/h7 shares a common interrupt line. 383 * - stm32mp1, has one line per ADC 384 */ 385 for (i = 0; i < priv->cfg->num_irqs; i++) { 386 priv->irq[i] = platform_get_irq(pdev, i); 387 if (priv->irq[i] < 0) 388 return priv->irq[i]; 389 } 390 391 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 392 &stm32_adc_domain_ops, 393 priv); 394 if (!priv->domain) { 395 dev_err(&pdev->dev, "Failed to add irq domain\n"); 396 return -ENOMEM; 397 } 398 399 for (i = 0; i < priv->cfg->num_irqs; i++) { 400 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 401 irq_set_handler_data(priv->irq[i], priv); 402 } 403 404 return 0; 405 } 406 407 static void stm32_adc_irq_remove(struct platform_device *pdev, 408 struct stm32_adc_priv *priv) 409 { 410 int hwirq; 411 unsigned int i; 412 413 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 414 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 415 irq_domain_remove(priv->domain); 416 417 for (i = 0; i < priv->cfg->num_irqs; i++) 418 irq_set_chained_handler(priv->irq[i], NULL); 419 } 420 421 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 422 struct device *dev) 423 { 424 int ret; 425 426 /* 427 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 428 * switches (via PCSEL) which have reduced performances when their 429 * supply is below 2.7V (vdda by default): 430 * - Voltage booster can be used, to get full ADC performances 431 * (increases power consumption). 432 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 433 * 434 * Recommended settings for ANASWVDD and EN_BOOSTER: 435 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 436 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 437 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 438 */ 439 if (priv->vdda_uv < 2700000) { 440 if (priv->syscfg && priv->vdd_uv > 2700000) { 441 ret = regulator_enable(priv->vdd); 442 if (ret < 0) { 443 dev_err(dev, "vdd enable failed %d\n", ret); 444 return ret; 445 } 446 447 ret = regmap_write(priv->syscfg, 448 STM32MP1_SYSCFG_PMCSETR, 449 STM32MP1_SYSCFG_ANASWVDD_MASK); 450 if (ret < 0) { 451 regulator_disable(priv->vdd); 452 dev_err(dev, "vdd select failed, %d\n", ret); 453 return ret; 454 } 455 dev_dbg(dev, "analog switches supplied by vdd\n"); 456 457 return 0; 458 } 459 460 if (priv->booster) { 461 /* 462 * This is optional, as this is a trade-off between 463 * analog performance and power consumption. 464 */ 465 ret = regulator_enable(priv->booster); 466 if (ret < 0) { 467 dev_err(dev, "booster enable failed %d\n", ret); 468 return ret; 469 } 470 dev_dbg(dev, "analog switches supplied by booster\n"); 471 472 return 0; 473 } 474 } 475 476 /* Fallback using vdda (default), nothing to do */ 477 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 478 priv->vdda_uv); 479 480 return 0; 481 } 482 483 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 484 { 485 if (priv->vdda_uv < 2700000) { 486 if (priv->syscfg && priv->vdd_uv > 2700000) { 487 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 488 STM32MP1_SYSCFG_ANASWVDD_MASK); 489 regulator_disable(priv->vdd); 490 return; 491 } 492 if (priv->booster) 493 regulator_disable(priv->booster); 494 } 495 } 496 497 static int stm32_adc_core_hw_start(struct device *dev) 498 { 499 struct stm32_adc_common *common = dev_get_drvdata(dev); 500 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 501 int ret; 502 503 ret = regulator_enable(priv->vdda); 504 if (ret < 0) { 505 dev_err(dev, "vdda enable failed %d\n", ret); 506 return ret; 507 } 508 509 ret = regulator_get_voltage(priv->vdda); 510 if (ret < 0) { 511 dev_err(dev, "vdda get voltage failed, %d\n", ret); 512 goto err_vdda_disable; 513 } 514 priv->vdda_uv = ret; 515 516 ret = stm32_adc_core_switches_supply_en(priv, dev); 517 if (ret < 0) 518 goto err_vdda_disable; 519 520 ret = regulator_enable(priv->vref); 521 if (ret < 0) { 522 dev_err(dev, "vref enable failed\n"); 523 goto err_switches_dis; 524 } 525 526 if (priv->bclk) { 527 ret = clk_prepare_enable(priv->bclk); 528 if (ret < 0) { 529 dev_err(dev, "bus clk enable failed\n"); 530 goto err_regulator_disable; 531 } 532 } 533 534 if (priv->aclk) { 535 ret = clk_prepare_enable(priv->aclk); 536 if (ret < 0) { 537 dev_err(dev, "adc clk enable failed\n"); 538 goto err_bclk_disable; 539 } 540 } 541 542 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 543 544 return 0; 545 546 err_bclk_disable: 547 if (priv->bclk) 548 clk_disable_unprepare(priv->bclk); 549 err_regulator_disable: 550 regulator_disable(priv->vref); 551 err_switches_dis: 552 stm32_adc_core_switches_supply_dis(priv); 553 err_vdda_disable: 554 regulator_disable(priv->vdda); 555 556 return ret; 557 } 558 559 static void stm32_adc_core_hw_stop(struct device *dev) 560 { 561 struct stm32_adc_common *common = dev_get_drvdata(dev); 562 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 563 564 /* Backup CCR that may be lost (depends on power state to achieve) */ 565 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 566 if (priv->aclk) 567 clk_disable_unprepare(priv->aclk); 568 if (priv->bclk) 569 clk_disable_unprepare(priv->bclk); 570 regulator_disable(priv->vref); 571 stm32_adc_core_switches_supply_dis(priv); 572 regulator_disable(priv->vdda); 573 } 574 575 static int stm32_adc_core_switches_probe(struct device *dev, 576 struct stm32_adc_priv *priv) 577 { 578 struct device_node *np = dev->of_node; 579 int ret; 580 581 /* Analog switches supply can be controlled by syscfg (optional) */ 582 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 583 if (IS_ERR(priv->syscfg)) { 584 ret = PTR_ERR(priv->syscfg); 585 if (ret != -ENODEV) 586 return dev_err_probe(dev, ret, "Can't probe syscfg\n"); 587 588 priv->syscfg = NULL; 589 } 590 591 /* Booster can be used to supply analog switches (optional) */ 592 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 593 of_property_read_bool(np, "booster-supply")) { 594 priv->booster = devm_regulator_get_optional(dev, "booster"); 595 if (IS_ERR(priv->booster)) { 596 ret = PTR_ERR(priv->booster); 597 if (ret != -ENODEV) 598 return dev_err_probe(dev, ret, "can't get booster\n"); 599 600 priv->booster = NULL; 601 } 602 } 603 604 /* Vdd can be used to supply analog switches (optional) */ 605 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 606 of_property_read_bool(np, "vdd-supply")) { 607 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 608 if (IS_ERR(priv->vdd)) { 609 ret = PTR_ERR(priv->vdd); 610 if (ret != -ENODEV) 611 return dev_err_probe(dev, ret, "can't get vdd\n"); 612 613 priv->vdd = NULL; 614 } 615 } 616 617 if (priv->vdd) { 618 ret = regulator_enable(priv->vdd); 619 if (ret < 0) { 620 dev_err(dev, "vdd enable failed %d\n", ret); 621 return ret; 622 } 623 624 ret = regulator_get_voltage(priv->vdd); 625 if (ret < 0) { 626 dev_err(dev, "vdd get voltage failed %d\n", ret); 627 regulator_disable(priv->vdd); 628 return ret; 629 } 630 priv->vdd_uv = ret; 631 632 regulator_disable(priv->vdd); 633 } 634 635 return 0; 636 } 637 638 static int stm32_adc_probe(struct platform_device *pdev) 639 { 640 struct stm32_adc_priv *priv; 641 struct device *dev = &pdev->dev; 642 struct device_node *np = pdev->dev.of_node; 643 struct resource *res; 644 u32 max_rate; 645 int ret; 646 647 if (!pdev->dev.of_node) 648 return -ENODEV; 649 650 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 651 if (!priv) 652 return -ENOMEM; 653 platform_set_drvdata(pdev, &priv->common); 654 655 priv->cfg = (const struct stm32_adc_priv_cfg *) 656 of_match_device(dev->driver->of_match_table, dev)->data; 657 658 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 659 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 660 if (IS_ERR(priv->common.base)) 661 return PTR_ERR(priv->common.base); 662 priv->common.phys_base = res->start; 663 664 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 665 if (IS_ERR(priv->vdda)) 666 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), 667 "vdda get failed\n"); 668 669 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 670 if (IS_ERR(priv->vref)) 671 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), 672 "vref get failed\n"); 673 674 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); 675 if (IS_ERR(priv->aclk)) 676 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), 677 "Can't get 'adc' clock\n"); 678 679 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); 680 if (IS_ERR(priv->bclk)) 681 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), 682 "Can't get 'bus' clock\n"); 683 684 ret = stm32_adc_core_switches_probe(dev, priv); 685 if (ret) 686 return ret; 687 688 pm_runtime_get_noresume(dev); 689 pm_runtime_set_active(dev); 690 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 691 pm_runtime_use_autosuspend(dev); 692 pm_runtime_enable(dev); 693 694 ret = stm32_adc_core_hw_start(dev); 695 if (ret) 696 goto err_pm_stop; 697 698 ret = regulator_get_voltage(priv->vref); 699 if (ret < 0) { 700 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 701 goto err_hw_stop; 702 } 703 priv->common.vref_mv = ret / 1000; 704 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 705 706 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 707 &max_rate); 708 if (!ret) 709 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 710 else 711 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 712 713 ret = priv->cfg->clk_sel(pdev, priv); 714 if (ret < 0) 715 goto err_hw_stop; 716 717 ret = stm32_adc_irq_probe(pdev, priv); 718 if (ret < 0) 719 goto err_hw_stop; 720 721 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 722 if (ret < 0) { 723 dev_err(&pdev->dev, "failed to populate DT children\n"); 724 goto err_irq_remove; 725 } 726 727 pm_runtime_mark_last_busy(dev); 728 pm_runtime_put_autosuspend(dev); 729 730 return 0; 731 732 err_irq_remove: 733 stm32_adc_irq_remove(pdev, priv); 734 err_hw_stop: 735 stm32_adc_core_hw_stop(dev); 736 err_pm_stop: 737 pm_runtime_disable(dev); 738 pm_runtime_set_suspended(dev); 739 pm_runtime_put_noidle(dev); 740 741 return ret; 742 } 743 744 static int stm32_adc_remove(struct platform_device *pdev) 745 { 746 struct stm32_adc_common *common = platform_get_drvdata(pdev); 747 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 748 749 pm_runtime_get_sync(&pdev->dev); 750 of_platform_depopulate(&pdev->dev); 751 stm32_adc_irq_remove(pdev, priv); 752 stm32_adc_core_hw_stop(&pdev->dev); 753 pm_runtime_disable(&pdev->dev); 754 pm_runtime_set_suspended(&pdev->dev); 755 pm_runtime_put_noidle(&pdev->dev); 756 757 return 0; 758 } 759 760 #if defined(CONFIG_PM) 761 static int stm32_adc_core_runtime_suspend(struct device *dev) 762 { 763 stm32_adc_core_hw_stop(dev); 764 765 return 0; 766 } 767 768 static int stm32_adc_core_runtime_resume(struct device *dev) 769 { 770 return stm32_adc_core_hw_start(dev); 771 } 772 773 static int stm32_adc_core_runtime_idle(struct device *dev) 774 { 775 pm_runtime_mark_last_busy(dev); 776 777 return 0; 778 } 779 #endif 780 781 static const struct dev_pm_ops stm32_adc_core_pm_ops = { 782 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 783 pm_runtime_force_resume) 784 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend, 785 stm32_adc_core_runtime_resume, 786 stm32_adc_core_runtime_idle) 787 }; 788 789 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 790 .regs = &stm32f4_adc_common_regs, 791 .clk_sel = stm32f4_adc_clk_sel, 792 .max_clk_rate_hz = 36000000, 793 .num_irqs = 1, 794 }; 795 796 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 797 .regs = &stm32h7_adc_common_regs, 798 .clk_sel = stm32h7_adc_clk_sel, 799 .max_clk_rate_hz = 36000000, 800 .has_syscfg = HAS_VBOOSTER, 801 .num_irqs = 1, 802 }; 803 804 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 805 .regs = &stm32h7_adc_common_regs, 806 .clk_sel = stm32h7_adc_clk_sel, 807 .max_clk_rate_hz = 40000000, 808 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 809 .num_irqs = 2, 810 }; 811 812 static const struct of_device_id stm32_adc_of_match[] = { 813 { 814 .compatible = "st,stm32f4-adc-core", 815 .data = (void *)&stm32f4_adc_priv_cfg 816 }, { 817 .compatible = "st,stm32h7-adc-core", 818 .data = (void *)&stm32h7_adc_priv_cfg 819 }, { 820 .compatible = "st,stm32mp1-adc-core", 821 .data = (void *)&stm32mp1_adc_priv_cfg 822 }, { 823 }, 824 }; 825 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 826 827 static struct platform_driver stm32_adc_driver = { 828 .probe = stm32_adc_probe, 829 .remove = stm32_adc_remove, 830 .driver = { 831 .name = "stm32-adc-core", 832 .of_match_table = stm32_adc_of_match, 833 .pm = &stm32_adc_core_pm_ops, 834 }, 835 }; 836 module_platform_driver(stm32_adc_driver); 837 838 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 839 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 840 MODULE_LICENSE("GPL v2"); 841 MODULE_ALIAS("platform:stm32-adc-core"); 842