xref: /openbmc/linux/drivers/iio/adc/stm32-adc-core.c (revision 81113b04)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * This file is part of STM32 ADC driver
4  *
5  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7  *
8  * Inspired from: fsl-imx25-tsadc
9  *
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdesc.h>
16 #include <linux/irqdomain.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 
25 #include "stm32-adc-core.h"
26 
27 #define STM32_ADC_CORE_SLEEP_DELAY_MS	2000
28 
29 /* SYSCFG registers */
30 #define STM32MP1_SYSCFG_PMCSETR		0x04
31 #define STM32MP1_SYSCFG_PMCCLRR		0x44
32 
33 /* SYSCFG bit fields */
34 #define STM32MP1_SYSCFG_ANASWVDD_MASK	BIT(9)
35 
36 /* SYSCFG capability flags */
37 #define HAS_VBOOSTER		BIT(0)
38 #define HAS_ANASWVDD		BIT(1)
39 
40 /**
41  * struct stm32_adc_common_regs - stm32 common registers
42  * @csr:	common status register offset
43  * @ccr:	common control register offset
44  * @eoc_msk:    array of eoc (end of conversion flag) masks in csr for adc1..n
45  * @ovr_msk:    array of ovr (overrun flag) masks in csr for adc1..n
46  * @ier:	interrupt enable register offset for each adc
47  * @eocie_msk:	end of conversion interrupt enable mask in @ier
48  */
49 struct stm32_adc_common_regs {
50 	u32 csr;
51 	u32 ccr;
52 	u32 eoc_msk[STM32_ADC_MAX_ADCS];
53 	u32 ovr_msk[STM32_ADC_MAX_ADCS];
54 	u32 ier;
55 	u32 eocie_msk;
56 };
57 
58 struct stm32_adc_priv;
59 
60 /**
61  * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
62  * @regs:	common registers for all instances
63  * @clk_sel:	clock selection routine
64  * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
65  * @has_syscfg: SYSCFG capability flags
66  * @num_irqs:	number of interrupt lines
67  */
68 struct stm32_adc_priv_cfg {
69 	const struct stm32_adc_common_regs *regs;
70 	int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
71 	u32 max_clk_rate_hz;
72 	unsigned int has_syscfg;
73 	unsigned int num_irqs;
74 };
75 
76 /**
77  * struct stm32_adc_priv - stm32 ADC core private data
78  * @irq:		irq(s) for ADC block
79  * @domain:		irq domain reference
80  * @aclk:		clock reference for the analog circuitry
81  * @bclk:		bus clock common for all ADCs, depends on part used
82  * @max_clk_rate:	desired maximum clock rate
83  * @booster:		booster supply reference
84  * @vdd:		vdd supply reference
85  * @vdda:		vdda analog supply reference
86  * @vref:		regulator reference
87  * @vdd_uv:		vdd supply voltage (microvolts)
88  * @vdda_uv:		vdda supply voltage (microvolts)
89  * @cfg:		compatible configuration data
90  * @common:		common data for all ADC instances
91  * @ccr_bak:		backup CCR in low power mode
92  * @syscfg:		reference to syscon, system control registers
93  */
94 struct stm32_adc_priv {
95 	int				irq[STM32_ADC_MAX_ADCS];
96 	struct irq_domain		*domain;
97 	struct clk			*aclk;
98 	struct clk			*bclk;
99 	u32				max_clk_rate;
100 	struct regulator		*booster;
101 	struct regulator		*vdd;
102 	struct regulator		*vdda;
103 	struct regulator		*vref;
104 	int				vdd_uv;
105 	int				vdda_uv;
106 	const struct stm32_adc_priv_cfg	*cfg;
107 	struct stm32_adc_common		common;
108 	u32				ccr_bak;
109 	struct regmap			*syscfg;
110 };
111 
112 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
113 {
114 	return container_of(com, struct stm32_adc_priv, common);
115 }
116 
117 /* STM32F4 ADC internal common clock prescaler division ratios */
118 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
119 
120 /**
121  * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
122  * @pdev: platform device
123  * @priv: stm32 ADC core private data
124  * Select clock prescaler used for analog conversions, before using ADC.
125  */
126 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
127 			       struct stm32_adc_priv *priv)
128 {
129 	unsigned long rate;
130 	u32 val;
131 	int i;
132 
133 	/* stm32f4 has one clk input for analog (mandatory), enforce it here */
134 	if (!priv->aclk) {
135 		dev_err(&pdev->dev, "No 'adc' clock found\n");
136 		return -ENOENT;
137 	}
138 
139 	rate = clk_get_rate(priv->aclk);
140 	if (!rate) {
141 		dev_err(&pdev->dev, "Invalid clock rate: 0\n");
142 		return -EINVAL;
143 	}
144 
145 	for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
146 		if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
147 			break;
148 	}
149 	if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
150 		dev_err(&pdev->dev, "adc clk selection failed\n");
151 		return -EINVAL;
152 	}
153 
154 	priv->common.rate = rate / stm32f4_pclk_div[i];
155 	val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
156 	val &= ~STM32F4_ADC_ADCPRE_MASK;
157 	val |= i << STM32F4_ADC_ADCPRE_SHIFT;
158 	writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
159 
160 	dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
161 		priv->common.rate / 1000);
162 
163 	return 0;
164 }
165 
166 /**
167  * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
168  * @ckmode: ADC clock mode, Async or sync with prescaler.
169  * @presc: prescaler bitfield for async clock mode
170  * @div: prescaler division ratio
171  */
172 struct stm32h7_adc_ck_spec {
173 	u32 ckmode;
174 	u32 presc;
175 	int div;
176 };
177 
178 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
179 	/* 00: CK_ADC[1..3]: Asynchronous clock modes */
180 	{ 0, 0, 1 },
181 	{ 0, 1, 2 },
182 	{ 0, 2, 4 },
183 	{ 0, 3, 6 },
184 	{ 0, 4, 8 },
185 	{ 0, 5, 10 },
186 	{ 0, 6, 12 },
187 	{ 0, 7, 16 },
188 	{ 0, 8, 32 },
189 	{ 0, 9, 64 },
190 	{ 0, 10, 128 },
191 	{ 0, 11, 256 },
192 	/* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
193 	{ 1, 0, 1 },
194 	{ 2, 0, 2 },
195 	{ 3, 0, 4 },
196 };
197 
198 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
199 			       struct stm32_adc_priv *priv)
200 {
201 	u32 ckmode, presc, val;
202 	unsigned long rate;
203 	int i, div;
204 
205 	/* stm32h7 bus clock is common for all ADC instances (mandatory) */
206 	if (!priv->bclk) {
207 		dev_err(&pdev->dev, "No 'bus' clock found\n");
208 		return -ENOENT;
209 	}
210 
211 	/*
212 	 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
213 	 * So, choice is to have bus clock mandatory and adc clock optional.
214 	 * If optional 'adc' clock has been found, then try to use it first.
215 	 */
216 	if (priv->aclk) {
217 		/*
218 		 * Asynchronous clock modes (e.g. ckmode == 0)
219 		 * From spec: PLL output musn't exceed max rate
220 		 */
221 		rate = clk_get_rate(priv->aclk);
222 		if (!rate) {
223 			dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
224 			return -EINVAL;
225 		}
226 
227 		for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
228 			ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
229 			presc = stm32h7_adc_ckmodes_spec[i].presc;
230 			div = stm32h7_adc_ckmodes_spec[i].div;
231 
232 			if (ckmode)
233 				continue;
234 
235 			if ((rate / div) <= priv->max_clk_rate)
236 				goto out;
237 		}
238 	}
239 
240 	/* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
241 	rate = clk_get_rate(priv->bclk);
242 	if (!rate) {
243 		dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
244 		return -EINVAL;
245 	}
246 
247 	for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
248 		ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
249 		presc = stm32h7_adc_ckmodes_spec[i].presc;
250 		div = stm32h7_adc_ckmodes_spec[i].div;
251 
252 		if (!ckmode)
253 			continue;
254 
255 		if ((rate / div) <= priv->max_clk_rate)
256 			goto out;
257 	}
258 
259 	dev_err(&pdev->dev, "adc clk selection failed\n");
260 	return -EINVAL;
261 
262 out:
263 	/* rate used later by each ADC instance to control BOOST mode */
264 	priv->common.rate = rate / div;
265 
266 	/* Set common clock mode and prescaler */
267 	val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
268 	val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
269 	val |= ckmode << STM32H7_CKMODE_SHIFT;
270 	val |= presc << STM32H7_PRESC_SHIFT;
271 	writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
272 
273 	dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
274 		ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
275 
276 	return 0;
277 }
278 
279 /* STM32F4 common registers definitions */
280 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
281 	.csr = STM32F4_ADC_CSR,
282 	.ccr = STM32F4_ADC_CCR,
283 	.eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
284 	.ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
285 	.ier = STM32F4_ADC_CR1,
286 	.eocie_msk = STM32F4_EOCIE,
287 };
288 
289 /* STM32H7 common registers definitions */
290 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
291 	.csr = STM32H7_ADC_CSR,
292 	.ccr = STM32H7_ADC_CCR,
293 	.eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
294 	.ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
295 	.ier = STM32H7_ADC_IER,
296 	.eocie_msk = STM32H7_EOCIE,
297 };
298 
299 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
300 	0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
301 };
302 
303 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
304 					  unsigned int adc)
305 {
306 	u32 ier, offset = stm32_adc_offset[adc];
307 
308 	ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
309 
310 	return ier & priv->cfg->regs->eocie_msk;
311 }
312 
313 /* ADC common interrupt for all instances */
314 static void stm32_adc_irq_handler(struct irq_desc *desc)
315 {
316 	struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
317 	struct irq_chip *chip = irq_desc_get_chip(desc);
318 	int i;
319 	u32 status;
320 
321 	chained_irq_enter(chip, desc);
322 	status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
323 
324 	/*
325 	 * End of conversion may be handled by using IRQ or DMA. There may be a
326 	 * race here when two conversions complete at the same time on several
327 	 * ADCs. EOC may be read 'set' for several ADCs, with:
328 	 * - an ADC configured to use DMA (EOC triggers the DMA request, and
329 	 *   is then automatically cleared by DR read in hardware)
330 	 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
331 	 *   be called in this case)
332 	 * So both EOC status bit in CSR and EOCIE control bit must be checked
333 	 * before invoking the interrupt handler (e.g. call ISR only for
334 	 * IRQ-enabled ADCs).
335 	 */
336 	for (i = 0; i < priv->cfg->num_irqs; i++) {
337 		if ((status & priv->cfg->regs->eoc_msk[i] &&
338 		     stm32_adc_eoc_enabled(priv, i)) ||
339 		     (status & priv->cfg->regs->ovr_msk[i]))
340 			generic_handle_irq(irq_find_mapping(priv->domain, i));
341 	}
342 
343 	chained_irq_exit(chip, desc);
344 };
345 
346 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
347 				irq_hw_number_t hwirq)
348 {
349 	irq_set_chip_data(irq, d->host_data);
350 	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
351 
352 	return 0;
353 }
354 
355 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
356 {
357 	irq_set_chip_and_handler(irq, NULL, NULL);
358 	irq_set_chip_data(irq, NULL);
359 }
360 
361 static const struct irq_domain_ops stm32_adc_domain_ops = {
362 	.map = stm32_adc_domain_map,
363 	.unmap  = stm32_adc_domain_unmap,
364 	.xlate = irq_domain_xlate_onecell,
365 };
366 
367 static int stm32_adc_irq_probe(struct platform_device *pdev,
368 			       struct stm32_adc_priv *priv)
369 {
370 	struct device_node *np = pdev->dev.of_node;
371 	unsigned int i;
372 
373 	/*
374 	 * Interrupt(s) must be provided, depending on the compatible:
375 	 * - stm32f4/h7 shares a common interrupt line.
376 	 * - stm32mp1, has one line per ADC
377 	 */
378 	for (i = 0; i < priv->cfg->num_irqs; i++) {
379 		priv->irq[i] = platform_get_irq(pdev, i);
380 		if (priv->irq[i] < 0)
381 			return priv->irq[i];
382 	}
383 
384 	priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
385 					     &stm32_adc_domain_ops,
386 					     priv);
387 	if (!priv->domain) {
388 		dev_err(&pdev->dev, "Failed to add irq domain\n");
389 		return -ENOMEM;
390 	}
391 
392 	for (i = 0; i < priv->cfg->num_irqs; i++) {
393 		irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
394 		irq_set_handler_data(priv->irq[i], priv);
395 	}
396 
397 	return 0;
398 }
399 
400 static void stm32_adc_irq_remove(struct platform_device *pdev,
401 				 struct stm32_adc_priv *priv)
402 {
403 	int hwirq;
404 	unsigned int i;
405 
406 	for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
407 		irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
408 	irq_domain_remove(priv->domain);
409 
410 	for (i = 0; i < priv->cfg->num_irqs; i++)
411 		irq_set_chained_handler(priv->irq[i], NULL);
412 }
413 
414 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
415 					     struct device *dev)
416 {
417 	int ret;
418 
419 	/*
420 	 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
421 	 * switches (via PCSEL) which have reduced performances when their
422 	 * supply is below 2.7V (vdda by default):
423 	 * - Voltage booster can be used, to get full ADC performances
424 	 *   (increases power consumption).
425 	 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
426 	 *
427 	 * Recommended settings for ANASWVDD and EN_BOOSTER:
428 	 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
429 	 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
430 	 * - vdda >= 2.7V:               ANASWVDD = 0, EN_BOOSTER = 0 (default)
431 	 */
432 	if (priv->vdda_uv < 2700000) {
433 		if (priv->syscfg && priv->vdd_uv > 2700000) {
434 			ret = regulator_enable(priv->vdd);
435 			if (ret < 0) {
436 				dev_err(dev, "vdd enable failed %d\n", ret);
437 				return ret;
438 			}
439 
440 			ret = regmap_write(priv->syscfg,
441 					   STM32MP1_SYSCFG_PMCSETR,
442 					   STM32MP1_SYSCFG_ANASWVDD_MASK);
443 			if (ret < 0) {
444 				regulator_disable(priv->vdd);
445 				dev_err(dev, "vdd select failed, %d\n", ret);
446 				return ret;
447 			}
448 			dev_dbg(dev, "analog switches supplied by vdd\n");
449 
450 			return 0;
451 		}
452 
453 		if (priv->booster) {
454 			/*
455 			 * This is optional, as this is a trade-off between
456 			 * analog performance and power consumption.
457 			 */
458 			ret = regulator_enable(priv->booster);
459 			if (ret < 0) {
460 				dev_err(dev, "booster enable failed %d\n", ret);
461 				return ret;
462 			}
463 			dev_dbg(dev, "analog switches supplied by booster\n");
464 
465 			return 0;
466 		}
467 	}
468 
469 	/* Fallback using vdda (default), nothing to do */
470 	dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
471 		priv->vdda_uv);
472 
473 	return 0;
474 }
475 
476 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
477 {
478 	if (priv->vdda_uv < 2700000) {
479 		if (priv->syscfg && priv->vdd_uv > 2700000) {
480 			regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
481 				     STM32MP1_SYSCFG_ANASWVDD_MASK);
482 			regulator_disable(priv->vdd);
483 			return;
484 		}
485 		if (priv->booster)
486 			regulator_disable(priv->booster);
487 	}
488 }
489 
490 static int stm32_adc_core_hw_start(struct device *dev)
491 {
492 	struct stm32_adc_common *common = dev_get_drvdata(dev);
493 	struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
494 	int ret;
495 
496 	ret = regulator_enable(priv->vdda);
497 	if (ret < 0) {
498 		dev_err(dev, "vdda enable failed %d\n", ret);
499 		return ret;
500 	}
501 
502 	ret = regulator_get_voltage(priv->vdda);
503 	if (ret < 0) {
504 		dev_err(dev, "vdda get voltage failed, %d\n", ret);
505 		goto err_vdda_disable;
506 	}
507 	priv->vdda_uv = ret;
508 
509 	ret = stm32_adc_core_switches_supply_en(priv, dev);
510 	if (ret < 0)
511 		goto err_vdda_disable;
512 
513 	ret = regulator_enable(priv->vref);
514 	if (ret < 0) {
515 		dev_err(dev, "vref enable failed\n");
516 		goto err_switches_dis;
517 	}
518 
519 	if (priv->bclk) {
520 		ret = clk_prepare_enable(priv->bclk);
521 		if (ret < 0) {
522 			dev_err(dev, "bus clk enable failed\n");
523 			goto err_regulator_disable;
524 		}
525 	}
526 
527 	if (priv->aclk) {
528 		ret = clk_prepare_enable(priv->aclk);
529 		if (ret < 0) {
530 			dev_err(dev, "adc clk enable failed\n");
531 			goto err_bclk_disable;
532 		}
533 	}
534 
535 	writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
536 
537 	return 0;
538 
539 err_bclk_disable:
540 	if (priv->bclk)
541 		clk_disable_unprepare(priv->bclk);
542 err_regulator_disable:
543 	regulator_disable(priv->vref);
544 err_switches_dis:
545 	stm32_adc_core_switches_supply_dis(priv);
546 err_vdda_disable:
547 	regulator_disable(priv->vdda);
548 
549 	return ret;
550 }
551 
552 static void stm32_adc_core_hw_stop(struct device *dev)
553 {
554 	struct stm32_adc_common *common = dev_get_drvdata(dev);
555 	struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
556 
557 	/* Backup CCR that may be lost (depends on power state to achieve) */
558 	priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
559 	if (priv->aclk)
560 		clk_disable_unprepare(priv->aclk);
561 	if (priv->bclk)
562 		clk_disable_unprepare(priv->bclk);
563 	regulator_disable(priv->vref);
564 	stm32_adc_core_switches_supply_dis(priv);
565 	regulator_disable(priv->vdda);
566 }
567 
568 static int stm32_adc_core_switches_probe(struct device *dev,
569 					 struct stm32_adc_priv *priv)
570 {
571 	struct device_node *np = dev->of_node;
572 	int ret;
573 
574 	/* Analog switches supply can be controlled by syscfg (optional) */
575 	priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
576 	if (IS_ERR(priv->syscfg)) {
577 		ret = PTR_ERR(priv->syscfg);
578 		if (ret != -ENODEV)
579 			return dev_err_probe(dev, ret, "Can't probe syscfg\n");
580 
581 		priv->syscfg = NULL;
582 	}
583 
584 	/* Booster can be used to supply analog switches (optional) */
585 	if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
586 	    of_property_read_bool(np, "booster-supply")) {
587 		priv->booster = devm_regulator_get_optional(dev, "booster");
588 		if (IS_ERR(priv->booster)) {
589 			ret = PTR_ERR(priv->booster);
590 			if (ret != -ENODEV)
591 				return dev_err_probe(dev, ret, "can't get booster\n");
592 
593 			priv->booster = NULL;
594 		}
595 	}
596 
597 	/* Vdd can be used to supply analog switches (optional) */
598 	if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
599 	    of_property_read_bool(np, "vdd-supply")) {
600 		priv->vdd = devm_regulator_get_optional(dev, "vdd");
601 		if (IS_ERR(priv->vdd)) {
602 			ret = PTR_ERR(priv->vdd);
603 			if (ret != -ENODEV)
604 				return dev_err_probe(dev, ret, "can't get vdd\n");
605 
606 			priv->vdd = NULL;
607 		}
608 	}
609 
610 	if (priv->vdd) {
611 		ret = regulator_enable(priv->vdd);
612 		if (ret < 0) {
613 			dev_err(dev, "vdd enable failed %d\n", ret);
614 			return ret;
615 		}
616 
617 		ret = regulator_get_voltage(priv->vdd);
618 		if (ret < 0) {
619 			dev_err(dev, "vdd get voltage failed %d\n", ret);
620 			regulator_disable(priv->vdd);
621 			return ret;
622 		}
623 		priv->vdd_uv = ret;
624 
625 		regulator_disable(priv->vdd);
626 	}
627 
628 	return 0;
629 }
630 
631 static int stm32_adc_probe(struct platform_device *pdev)
632 {
633 	struct stm32_adc_priv *priv;
634 	struct device *dev = &pdev->dev;
635 	struct device_node *np = pdev->dev.of_node;
636 	struct resource *res;
637 	u32 max_rate;
638 	int ret;
639 
640 	if (!pdev->dev.of_node)
641 		return -ENODEV;
642 
643 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
644 	if (!priv)
645 		return -ENOMEM;
646 	platform_set_drvdata(pdev, &priv->common);
647 
648 	priv->cfg = (const struct stm32_adc_priv_cfg *)
649 		of_match_device(dev->driver->of_match_table, dev)->data;
650 
651 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652 	priv->common.base = devm_ioremap_resource(&pdev->dev, res);
653 	if (IS_ERR(priv->common.base))
654 		return PTR_ERR(priv->common.base);
655 	priv->common.phys_base = res->start;
656 
657 	priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
658 	if (IS_ERR(priv->vdda))
659 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
660 				     "vdda get failed\n");
661 
662 	priv->vref = devm_regulator_get(&pdev->dev, "vref");
663 	if (IS_ERR(priv->vref))
664 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
665 				     "vref get failed\n");
666 
667 	priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
668 	if (IS_ERR(priv->aclk))
669 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
670 				     "Can't get 'adc' clock\n");
671 
672 	priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
673 	if (IS_ERR(priv->bclk))
674 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
675 				     "Can't get 'bus' clock\n");
676 
677 	ret = stm32_adc_core_switches_probe(dev, priv);
678 	if (ret)
679 		return ret;
680 
681 	pm_runtime_get_noresume(dev);
682 	pm_runtime_set_active(dev);
683 	pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
684 	pm_runtime_use_autosuspend(dev);
685 	pm_runtime_enable(dev);
686 
687 	ret = stm32_adc_core_hw_start(dev);
688 	if (ret)
689 		goto err_pm_stop;
690 
691 	ret = regulator_get_voltage(priv->vref);
692 	if (ret < 0) {
693 		dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
694 		goto err_hw_stop;
695 	}
696 	priv->common.vref_mv = ret / 1000;
697 	dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
698 
699 	ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
700 				   &max_rate);
701 	if (!ret)
702 		priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
703 	else
704 		priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
705 
706 	ret = priv->cfg->clk_sel(pdev, priv);
707 	if (ret < 0)
708 		goto err_hw_stop;
709 
710 	ret = stm32_adc_irq_probe(pdev, priv);
711 	if (ret < 0)
712 		goto err_hw_stop;
713 
714 	ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
715 	if (ret < 0) {
716 		dev_err(&pdev->dev, "failed to populate DT children\n");
717 		goto err_irq_remove;
718 	}
719 
720 	pm_runtime_mark_last_busy(dev);
721 	pm_runtime_put_autosuspend(dev);
722 
723 	return 0;
724 
725 err_irq_remove:
726 	stm32_adc_irq_remove(pdev, priv);
727 err_hw_stop:
728 	stm32_adc_core_hw_stop(dev);
729 err_pm_stop:
730 	pm_runtime_disable(dev);
731 	pm_runtime_set_suspended(dev);
732 	pm_runtime_put_noidle(dev);
733 
734 	return ret;
735 }
736 
737 static int stm32_adc_remove(struct platform_device *pdev)
738 {
739 	struct stm32_adc_common *common = platform_get_drvdata(pdev);
740 	struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
741 
742 	pm_runtime_get_sync(&pdev->dev);
743 	of_platform_depopulate(&pdev->dev);
744 	stm32_adc_irq_remove(pdev, priv);
745 	stm32_adc_core_hw_stop(&pdev->dev);
746 	pm_runtime_disable(&pdev->dev);
747 	pm_runtime_set_suspended(&pdev->dev);
748 	pm_runtime_put_noidle(&pdev->dev);
749 
750 	return 0;
751 }
752 
753 #if defined(CONFIG_PM)
754 static int stm32_adc_core_runtime_suspend(struct device *dev)
755 {
756 	stm32_adc_core_hw_stop(dev);
757 
758 	return 0;
759 }
760 
761 static int stm32_adc_core_runtime_resume(struct device *dev)
762 {
763 	return stm32_adc_core_hw_start(dev);
764 }
765 
766 static int stm32_adc_core_runtime_idle(struct device *dev)
767 {
768 	pm_runtime_mark_last_busy(dev);
769 
770 	return 0;
771 }
772 #endif
773 
774 static const struct dev_pm_ops stm32_adc_core_pm_ops = {
775 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
776 				pm_runtime_force_resume)
777 	SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
778 			   stm32_adc_core_runtime_resume,
779 			   stm32_adc_core_runtime_idle)
780 };
781 
782 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
783 	.regs = &stm32f4_adc_common_regs,
784 	.clk_sel = stm32f4_adc_clk_sel,
785 	.max_clk_rate_hz = 36000000,
786 	.num_irqs = 1,
787 };
788 
789 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
790 	.regs = &stm32h7_adc_common_regs,
791 	.clk_sel = stm32h7_adc_clk_sel,
792 	.max_clk_rate_hz = 36000000,
793 	.has_syscfg = HAS_VBOOSTER,
794 	.num_irqs = 1,
795 };
796 
797 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
798 	.regs = &stm32h7_adc_common_regs,
799 	.clk_sel = stm32h7_adc_clk_sel,
800 	.max_clk_rate_hz = 40000000,
801 	.has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
802 	.num_irqs = 2,
803 };
804 
805 static const struct of_device_id stm32_adc_of_match[] = {
806 	{
807 		.compatible = "st,stm32f4-adc-core",
808 		.data = (void *)&stm32f4_adc_priv_cfg
809 	}, {
810 		.compatible = "st,stm32h7-adc-core",
811 		.data = (void *)&stm32h7_adc_priv_cfg
812 	}, {
813 		.compatible = "st,stm32mp1-adc-core",
814 		.data = (void *)&stm32mp1_adc_priv_cfg
815 	}, {
816 	},
817 };
818 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
819 
820 static struct platform_driver stm32_adc_driver = {
821 	.probe = stm32_adc_probe,
822 	.remove = stm32_adc_remove,
823 	.driver = {
824 		.name = "stm32-adc-core",
825 		.of_match_table = stm32_adc_of_match,
826 		.pm = &stm32_adc_core_pm_ops,
827 	},
828 };
829 module_platform_driver(stm32_adc_driver);
830 
831 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
832 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
833 MODULE_LICENSE("GPL v2");
834 MODULE_ALIAS("platform:stm32-adc-core");
835