1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdesc.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include "stm32-adc-core.h" 26 27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 28 29 /* SYSCFG registers */ 30 #define STM32MP1_SYSCFG_PMCSETR 0x04 31 #define STM32MP1_SYSCFG_PMCCLRR 0x44 32 33 /* SYSCFG bit fields */ 34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 35 36 /* SYSCFG capability flags */ 37 #define HAS_VBOOSTER BIT(0) 38 #define HAS_ANASWVDD BIT(1) 39 40 /** 41 * struct stm32_adc_common_regs - stm32 common registers 42 * @csr: common status register offset 43 * @ccr: common control register offset 44 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n 45 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n 46 * @ier: interrupt enable register offset for each adc 47 * @eocie_msk: end of conversion interrupt enable mask in @ier 48 */ 49 struct stm32_adc_common_regs { 50 u32 csr; 51 u32 ccr; 52 u32 eoc_msk[STM32_ADC_MAX_ADCS]; 53 u32 ovr_msk[STM32_ADC_MAX_ADCS]; 54 u32 ier; 55 u32 eocie_msk; 56 }; 57 58 struct stm32_adc_priv; 59 60 /** 61 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 62 * @regs: common registers for all instances 63 * @clk_sel: clock selection routine 64 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 65 * @has_syscfg: SYSCFG capability flags 66 * @num_irqs: number of interrupt lines 67 */ 68 struct stm32_adc_priv_cfg { 69 const struct stm32_adc_common_regs *regs; 70 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 71 u32 max_clk_rate_hz; 72 unsigned int has_syscfg; 73 unsigned int num_irqs; 74 }; 75 76 /** 77 * struct stm32_adc_priv - stm32 ADC core private data 78 * @irq: irq(s) for ADC block 79 * @domain: irq domain reference 80 * @aclk: clock reference for the analog circuitry 81 * @bclk: bus clock common for all ADCs, depends on part used 82 * @max_clk_rate: desired maximum clock rate 83 * @booster: booster supply reference 84 * @vdd: vdd supply reference 85 * @vdda: vdda analog supply reference 86 * @vref: regulator reference 87 * @vdd_uv: vdd supply voltage (microvolts) 88 * @vdda_uv: vdda supply voltage (microvolts) 89 * @cfg: compatible configuration data 90 * @common: common data for all ADC instances 91 * @ccr_bak: backup CCR in low power mode 92 * @syscfg: reference to syscon, system control registers 93 */ 94 struct stm32_adc_priv { 95 int irq[STM32_ADC_MAX_ADCS]; 96 struct irq_domain *domain; 97 struct clk *aclk; 98 struct clk *bclk; 99 u32 max_clk_rate; 100 struct regulator *booster; 101 struct regulator *vdd; 102 struct regulator *vdda; 103 struct regulator *vref; 104 int vdd_uv; 105 int vdda_uv; 106 const struct stm32_adc_priv_cfg *cfg; 107 struct stm32_adc_common common; 108 u32 ccr_bak; 109 struct regmap *syscfg; 110 }; 111 112 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 113 { 114 return container_of(com, struct stm32_adc_priv, common); 115 } 116 117 /* STM32F4 ADC internal common clock prescaler division ratios */ 118 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 119 120 /** 121 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 122 * @pdev: platform device 123 * @priv: stm32 ADC core private data 124 * Select clock prescaler used for analog conversions, before using ADC. 125 */ 126 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 127 struct stm32_adc_priv *priv) 128 { 129 unsigned long rate; 130 u32 val; 131 int i; 132 133 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 134 if (!priv->aclk) { 135 dev_err(&pdev->dev, "No 'adc' clock found\n"); 136 return -ENOENT; 137 } 138 139 rate = clk_get_rate(priv->aclk); 140 if (!rate) { 141 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 142 return -EINVAL; 143 } 144 145 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 146 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 147 break; 148 } 149 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 150 dev_err(&pdev->dev, "adc clk selection failed\n"); 151 return -EINVAL; 152 } 153 154 priv->common.rate = rate / stm32f4_pclk_div[i]; 155 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 156 val &= ~STM32F4_ADC_ADCPRE_MASK; 157 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 158 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 159 160 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 161 priv->common.rate / 1000); 162 163 return 0; 164 } 165 166 /** 167 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 168 * @ckmode: ADC clock mode, Async or sync with prescaler. 169 * @presc: prescaler bitfield for async clock mode 170 * @div: prescaler division ratio 171 */ 172 struct stm32h7_adc_ck_spec { 173 u32 ckmode; 174 u32 presc; 175 int div; 176 }; 177 178 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 179 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 180 { 0, 0, 1 }, 181 { 0, 1, 2 }, 182 { 0, 2, 4 }, 183 { 0, 3, 6 }, 184 { 0, 4, 8 }, 185 { 0, 5, 10 }, 186 { 0, 6, 12 }, 187 { 0, 7, 16 }, 188 { 0, 8, 32 }, 189 { 0, 9, 64 }, 190 { 0, 10, 128 }, 191 { 0, 11, 256 }, 192 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 193 { 1, 0, 1 }, 194 { 2, 0, 2 }, 195 { 3, 0, 4 }, 196 }; 197 198 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 199 struct stm32_adc_priv *priv) 200 { 201 u32 ckmode, presc, val; 202 unsigned long rate; 203 int i, div, duty; 204 205 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 206 if (!priv->bclk) { 207 dev_err(&pdev->dev, "No 'bus' clock found\n"); 208 return -ENOENT; 209 } 210 211 /* 212 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 213 * So, choice is to have bus clock mandatory and adc clock optional. 214 * If optional 'adc' clock has been found, then try to use it first. 215 */ 216 if (priv->aclk) { 217 /* 218 * Asynchronous clock modes (e.g. ckmode == 0) 219 * From spec: PLL output musn't exceed max rate 220 */ 221 rate = clk_get_rate(priv->aclk); 222 if (!rate) { 223 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 224 return -EINVAL; 225 } 226 227 /* If duty is an error, kindly use at least /2 divider */ 228 duty = clk_get_scaled_duty_cycle(priv->aclk, 100); 229 if (duty < 0) 230 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty); 231 232 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 233 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 234 presc = stm32h7_adc_ckmodes_spec[i].presc; 235 div = stm32h7_adc_ckmodes_spec[i].div; 236 237 if (ckmode) 238 continue; 239 240 /* 241 * For proper operation, clock duty cycle range is 49% 242 * to 51%. Apply at least /2 prescaler otherwise. 243 */ 244 if (div == 1 && (duty < 49 || duty > 51)) 245 continue; 246 247 if ((rate / div) <= priv->max_clk_rate) 248 goto out; 249 } 250 } 251 252 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 253 rate = clk_get_rate(priv->bclk); 254 if (!rate) { 255 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 256 return -EINVAL; 257 } 258 259 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); 260 if (duty < 0) 261 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty); 262 263 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 264 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 265 presc = stm32h7_adc_ckmodes_spec[i].presc; 266 div = stm32h7_adc_ckmodes_spec[i].div; 267 268 if (!ckmode) 269 continue; 270 271 if (div == 1 && (duty < 49 || duty > 51)) 272 continue; 273 274 if ((rate / div) <= priv->max_clk_rate) 275 goto out; 276 } 277 278 dev_err(&pdev->dev, "adc clk selection failed\n"); 279 return -EINVAL; 280 281 out: 282 /* rate used later by each ADC instance to control BOOST mode */ 283 priv->common.rate = rate / div; 284 285 /* Set common clock mode and prescaler */ 286 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 287 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 288 val |= ckmode << STM32H7_CKMODE_SHIFT; 289 val |= presc << STM32H7_PRESC_SHIFT; 290 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 291 292 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 293 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 294 295 return 0; 296 } 297 298 /* STM32F4 common registers definitions */ 299 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 300 .csr = STM32F4_ADC_CSR, 301 .ccr = STM32F4_ADC_CCR, 302 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3}, 303 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3}, 304 .ier = STM32F4_ADC_CR1, 305 .eocie_msk = STM32F4_EOCIE, 306 }; 307 308 /* STM32H7 common registers definitions */ 309 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 310 .csr = STM32H7_ADC_CSR, 311 .ccr = STM32H7_ADC_CCR, 312 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV}, 313 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV}, 314 .ier = STM32H7_ADC_IER, 315 .eocie_msk = STM32H7_EOCIE, 316 }; 317 318 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 319 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 320 }; 321 322 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 323 unsigned int adc) 324 { 325 u32 ier, offset = stm32_adc_offset[adc]; 326 327 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 328 329 return ier & priv->cfg->regs->eocie_msk; 330 } 331 332 /* ADC common interrupt for all instances */ 333 static void stm32_adc_irq_handler(struct irq_desc *desc) 334 { 335 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 336 struct irq_chip *chip = irq_desc_get_chip(desc); 337 int i; 338 u32 status; 339 340 chained_irq_enter(chip, desc); 341 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 342 343 /* 344 * End of conversion may be handled by using IRQ or DMA. There may be a 345 * race here when two conversions complete at the same time on several 346 * ADCs. EOC may be read 'set' for several ADCs, with: 347 * - an ADC configured to use DMA (EOC triggers the DMA request, and 348 * is then automatically cleared by DR read in hardware) 349 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 350 * be called in this case) 351 * So both EOC status bit in CSR and EOCIE control bit must be checked 352 * before invoking the interrupt handler (e.g. call ISR only for 353 * IRQ-enabled ADCs). 354 */ 355 for (i = 0; i < priv->cfg->num_irqs; i++) { 356 if ((status & priv->cfg->regs->eoc_msk[i] && 357 stm32_adc_eoc_enabled(priv, i)) || 358 (status & priv->cfg->regs->ovr_msk[i])) 359 generic_handle_irq(irq_find_mapping(priv->domain, i)); 360 } 361 362 chained_irq_exit(chip, desc); 363 }; 364 365 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 366 irq_hw_number_t hwirq) 367 { 368 irq_set_chip_data(irq, d->host_data); 369 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 370 371 return 0; 372 } 373 374 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 375 { 376 irq_set_chip_and_handler(irq, NULL, NULL); 377 irq_set_chip_data(irq, NULL); 378 } 379 380 static const struct irq_domain_ops stm32_adc_domain_ops = { 381 .map = stm32_adc_domain_map, 382 .unmap = stm32_adc_domain_unmap, 383 .xlate = irq_domain_xlate_onecell, 384 }; 385 386 static int stm32_adc_irq_probe(struct platform_device *pdev, 387 struct stm32_adc_priv *priv) 388 { 389 struct device_node *np = pdev->dev.of_node; 390 unsigned int i; 391 392 /* 393 * Interrupt(s) must be provided, depending on the compatible: 394 * - stm32f4/h7 shares a common interrupt line. 395 * - stm32mp1, has one line per ADC 396 */ 397 for (i = 0; i < priv->cfg->num_irqs; i++) { 398 priv->irq[i] = platform_get_irq(pdev, i); 399 if (priv->irq[i] < 0) 400 return priv->irq[i]; 401 } 402 403 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 404 &stm32_adc_domain_ops, 405 priv); 406 if (!priv->domain) { 407 dev_err(&pdev->dev, "Failed to add irq domain\n"); 408 return -ENOMEM; 409 } 410 411 for (i = 0; i < priv->cfg->num_irqs; i++) { 412 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 413 irq_set_handler_data(priv->irq[i], priv); 414 } 415 416 return 0; 417 } 418 419 static void stm32_adc_irq_remove(struct platform_device *pdev, 420 struct stm32_adc_priv *priv) 421 { 422 int hwirq; 423 unsigned int i; 424 425 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 426 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 427 irq_domain_remove(priv->domain); 428 429 for (i = 0; i < priv->cfg->num_irqs; i++) 430 irq_set_chained_handler(priv->irq[i], NULL); 431 } 432 433 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 434 struct device *dev) 435 { 436 int ret; 437 438 /* 439 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 440 * switches (via PCSEL) which have reduced performances when their 441 * supply is below 2.7V (vdda by default): 442 * - Voltage booster can be used, to get full ADC performances 443 * (increases power consumption). 444 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 445 * 446 * Recommended settings for ANASWVDD and EN_BOOSTER: 447 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 448 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 449 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 450 */ 451 if (priv->vdda_uv < 2700000) { 452 if (priv->syscfg && priv->vdd_uv > 2700000) { 453 ret = regulator_enable(priv->vdd); 454 if (ret < 0) { 455 dev_err(dev, "vdd enable failed %d\n", ret); 456 return ret; 457 } 458 459 ret = regmap_write(priv->syscfg, 460 STM32MP1_SYSCFG_PMCSETR, 461 STM32MP1_SYSCFG_ANASWVDD_MASK); 462 if (ret < 0) { 463 regulator_disable(priv->vdd); 464 dev_err(dev, "vdd select failed, %d\n", ret); 465 return ret; 466 } 467 dev_dbg(dev, "analog switches supplied by vdd\n"); 468 469 return 0; 470 } 471 472 if (priv->booster) { 473 /* 474 * This is optional, as this is a trade-off between 475 * analog performance and power consumption. 476 */ 477 ret = regulator_enable(priv->booster); 478 if (ret < 0) { 479 dev_err(dev, "booster enable failed %d\n", ret); 480 return ret; 481 } 482 dev_dbg(dev, "analog switches supplied by booster\n"); 483 484 return 0; 485 } 486 } 487 488 /* Fallback using vdda (default), nothing to do */ 489 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 490 priv->vdda_uv); 491 492 return 0; 493 } 494 495 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 496 { 497 if (priv->vdda_uv < 2700000) { 498 if (priv->syscfg && priv->vdd_uv > 2700000) { 499 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 500 STM32MP1_SYSCFG_ANASWVDD_MASK); 501 regulator_disable(priv->vdd); 502 return; 503 } 504 if (priv->booster) 505 regulator_disable(priv->booster); 506 } 507 } 508 509 static int stm32_adc_core_hw_start(struct device *dev) 510 { 511 struct stm32_adc_common *common = dev_get_drvdata(dev); 512 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 513 int ret; 514 515 ret = regulator_enable(priv->vdda); 516 if (ret < 0) { 517 dev_err(dev, "vdda enable failed %d\n", ret); 518 return ret; 519 } 520 521 ret = regulator_get_voltage(priv->vdda); 522 if (ret < 0) { 523 dev_err(dev, "vdda get voltage failed, %d\n", ret); 524 goto err_vdda_disable; 525 } 526 priv->vdda_uv = ret; 527 528 ret = stm32_adc_core_switches_supply_en(priv, dev); 529 if (ret < 0) 530 goto err_vdda_disable; 531 532 ret = regulator_enable(priv->vref); 533 if (ret < 0) { 534 dev_err(dev, "vref enable failed\n"); 535 goto err_switches_dis; 536 } 537 538 ret = clk_prepare_enable(priv->bclk); 539 if (ret < 0) { 540 dev_err(dev, "bus clk enable failed\n"); 541 goto err_regulator_disable; 542 } 543 544 ret = clk_prepare_enable(priv->aclk); 545 if (ret < 0) { 546 dev_err(dev, "adc clk enable failed\n"); 547 goto err_bclk_disable; 548 } 549 550 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 551 552 return 0; 553 554 err_bclk_disable: 555 clk_disable_unprepare(priv->bclk); 556 err_regulator_disable: 557 regulator_disable(priv->vref); 558 err_switches_dis: 559 stm32_adc_core_switches_supply_dis(priv); 560 err_vdda_disable: 561 regulator_disable(priv->vdda); 562 563 return ret; 564 } 565 566 static void stm32_adc_core_hw_stop(struct device *dev) 567 { 568 struct stm32_adc_common *common = dev_get_drvdata(dev); 569 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 570 571 /* Backup CCR that may be lost (depends on power state to achieve) */ 572 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 573 clk_disable_unprepare(priv->aclk); 574 clk_disable_unprepare(priv->bclk); 575 regulator_disable(priv->vref); 576 stm32_adc_core_switches_supply_dis(priv); 577 regulator_disable(priv->vdda); 578 } 579 580 static int stm32_adc_core_switches_probe(struct device *dev, 581 struct stm32_adc_priv *priv) 582 { 583 struct device_node *np = dev->of_node; 584 int ret; 585 586 /* Analog switches supply can be controlled by syscfg (optional) */ 587 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 588 if (IS_ERR(priv->syscfg)) { 589 ret = PTR_ERR(priv->syscfg); 590 if (ret != -ENODEV) 591 return dev_err_probe(dev, ret, "Can't probe syscfg\n"); 592 593 priv->syscfg = NULL; 594 } 595 596 /* Booster can be used to supply analog switches (optional) */ 597 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 598 of_property_read_bool(np, "booster-supply")) { 599 priv->booster = devm_regulator_get_optional(dev, "booster"); 600 if (IS_ERR(priv->booster)) { 601 ret = PTR_ERR(priv->booster); 602 if (ret != -ENODEV) 603 return dev_err_probe(dev, ret, "can't get booster\n"); 604 605 priv->booster = NULL; 606 } 607 } 608 609 /* Vdd can be used to supply analog switches (optional) */ 610 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 611 of_property_read_bool(np, "vdd-supply")) { 612 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 613 if (IS_ERR(priv->vdd)) { 614 ret = PTR_ERR(priv->vdd); 615 if (ret != -ENODEV) 616 return dev_err_probe(dev, ret, "can't get vdd\n"); 617 618 priv->vdd = NULL; 619 } 620 } 621 622 if (priv->vdd) { 623 ret = regulator_enable(priv->vdd); 624 if (ret < 0) { 625 dev_err(dev, "vdd enable failed %d\n", ret); 626 return ret; 627 } 628 629 ret = regulator_get_voltage(priv->vdd); 630 if (ret < 0) { 631 dev_err(dev, "vdd get voltage failed %d\n", ret); 632 regulator_disable(priv->vdd); 633 return ret; 634 } 635 priv->vdd_uv = ret; 636 637 regulator_disable(priv->vdd); 638 } 639 640 return 0; 641 } 642 643 static int stm32_adc_probe(struct platform_device *pdev) 644 { 645 struct stm32_adc_priv *priv; 646 struct device *dev = &pdev->dev; 647 struct device_node *np = pdev->dev.of_node; 648 struct resource *res; 649 u32 max_rate; 650 int ret; 651 652 if (!pdev->dev.of_node) 653 return -ENODEV; 654 655 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 656 if (!priv) 657 return -ENOMEM; 658 platform_set_drvdata(pdev, &priv->common); 659 660 priv->cfg = (const struct stm32_adc_priv_cfg *) 661 of_match_device(dev->driver->of_match_table, dev)->data; 662 spin_lock_init(&priv->common.lock); 663 664 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 665 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 666 if (IS_ERR(priv->common.base)) 667 return PTR_ERR(priv->common.base); 668 priv->common.phys_base = res->start; 669 670 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 671 if (IS_ERR(priv->vdda)) 672 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), 673 "vdda get failed\n"); 674 675 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 676 if (IS_ERR(priv->vref)) 677 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), 678 "vref get failed\n"); 679 680 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); 681 if (IS_ERR(priv->aclk)) 682 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), 683 "Can't get 'adc' clock\n"); 684 685 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); 686 if (IS_ERR(priv->bclk)) 687 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), 688 "Can't get 'bus' clock\n"); 689 690 ret = stm32_adc_core_switches_probe(dev, priv); 691 if (ret) 692 return ret; 693 694 pm_runtime_get_noresume(dev); 695 pm_runtime_set_active(dev); 696 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 697 pm_runtime_use_autosuspend(dev); 698 pm_runtime_enable(dev); 699 700 ret = stm32_adc_core_hw_start(dev); 701 if (ret) 702 goto err_pm_stop; 703 704 ret = regulator_get_voltage(priv->vref); 705 if (ret < 0) { 706 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 707 goto err_hw_stop; 708 } 709 priv->common.vref_mv = ret / 1000; 710 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 711 712 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 713 &max_rate); 714 if (!ret) 715 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 716 else 717 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 718 719 ret = priv->cfg->clk_sel(pdev, priv); 720 if (ret < 0) 721 goto err_hw_stop; 722 723 ret = stm32_adc_irq_probe(pdev, priv); 724 if (ret < 0) 725 goto err_hw_stop; 726 727 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 728 if (ret < 0) { 729 dev_err(&pdev->dev, "failed to populate DT children\n"); 730 goto err_irq_remove; 731 } 732 733 pm_runtime_mark_last_busy(dev); 734 pm_runtime_put_autosuspend(dev); 735 736 return 0; 737 738 err_irq_remove: 739 stm32_adc_irq_remove(pdev, priv); 740 err_hw_stop: 741 stm32_adc_core_hw_stop(dev); 742 err_pm_stop: 743 pm_runtime_disable(dev); 744 pm_runtime_set_suspended(dev); 745 pm_runtime_put_noidle(dev); 746 747 return ret; 748 } 749 750 static int stm32_adc_remove(struct platform_device *pdev) 751 { 752 struct stm32_adc_common *common = platform_get_drvdata(pdev); 753 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 754 755 pm_runtime_get_sync(&pdev->dev); 756 of_platform_depopulate(&pdev->dev); 757 stm32_adc_irq_remove(pdev, priv); 758 stm32_adc_core_hw_stop(&pdev->dev); 759 pm_runtime_disable(&pdev->dev); 760 pm_runtime_set_suspended(&pdev->dev); 761 pm_runtime_put_noidle(&pdev->dev); 762 763 return 0; 764 } 765 766 static int stm32_adc_core_runtime_suspend(struct device *dev) 767 { 768 stm32_adc_core_hw_stop(dev); 769 770 return 0; 771 } 772 773 static int stm32_adc_core_runtime_resume(struct device *dev) 774 { 775 return stm32_adc_core_hw_start(dev); 776 } 777 778 static int stm32_adc_core_runtime_idle(struct device *dev) 779 { 780 pm_runtime_mark_last_busy(dev); 781 782 return 0; 783 } 784 785 static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops, 786 stm32_adc_core_runtime_suspend, 787 stm32_adc_core_runtime_resume, 788 stm32_adc_core_runtime_idle); 789 790 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 791 .regs = &stm32f4_adc_common_regs, 792 .clk_sel = stm32f4_adc_clk_sel, 793 .max_clk_rate_hz = 36000000, 794 .num_irqs = 1, 795 }; 796 797 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 798 .regs = &stm32h7_adc_common_regs, 799 .clk_sel = stm32h7_adc_clk_sel, 800 .max_clk_rate_hz = 36000000, 801 .has_syscfg = HAS_VBOOSTER, 802 .num_irqs = 1, 803 }; 804 805 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 806 .regs = &stm32h7_adc_common_regs, 807 .clk_sel = stm32h7_adc_clk_sel, 808 .max_clk_rate_hz = 40000000, 809 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 810 .num_irqs = 2, 811 }; 812 813 static const struct of_device_id stm32_adc_of_match[] = { 814 { 815 .compatible = "st,stm32f4-adc-core", 816 .data = (void *)&stm32f4_adc_priv_cfg 817 }, { 818 .compatible = "st,stm32h7-adc-core", 819 .data = (void *)&stm32h7_adc_priv_cfg 820 }, { 821 .compatible = "st,stm32mp1-adc-core", 822 .data = (void *)&stm32mp1_adc_priv_cfg 823 }, { 824 }, 825 }; 826 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 827 828 static struct platform_driver stm32_adc_driver = { 829 .probe = stm32_adc_probe, 830 .remove = stm32_adc_remove, 831 .driver = { 832 .name = "stm32-adc-core", 833 .of_match_table = stm32_adc_of_match, 834 .pm = pm_ptr(&stm32_adc_core_pm_ops), 835 }, 836 }; 837 module_platform_driver(stm32_adc_driver); 838 839 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 840 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 841 MODULE_LICENSE("GPL v2"); 842 MODULE_ALIAS("platform:stm32-adc-core"); 843