1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdesc.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include "stm32-adc-core.h" 26 27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 28 29 /* SYSCFG registers */ 30 #define STM32MP1_SYSCFG_PMCSETR 0x04 31 #define STM32MP1_SYSCFG_PMCCLRR 0x44 32 33 /* SYSCFG bit fields */ 34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 35 36 /* SYSCFG capability flags */ 37 #define HAS_VBOOSTER BIT(0) 38 #define HAS_ANASWVDD BIT(1) 39 40 /** 41 * struct stm32_adc_common_regs - stm32 common registers 42 * @csr: common status register offset 43 * @ccr: common control register offset 44 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n 45 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n 46 * @ier: interrupt enable register offset for each adc 47 * @eocie_msk: end of conversion interrupt enable mask in @ier 48 */ 49 struct stm32_adc_common_regs { 50 u32 csr; 51 u32 ccr; 52 u32 eoc_msk[STM32_ADC_MAX_ADCS]; 53 u32 ovr_msk[STM32_ADC_MAX_ADCS]; 54 u32 ier; 55 u32 eocie_msk; 56 }; 57 58 struct stm32_adc_priv; 59 60 /** 61 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 62 * @regs: common registers for all instances 63 * @clk_sel: clock selection routine 64 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 65 * @has_syscfg: SYSCFG capability flags 66 * @num_irqs: number of interrupt lines 67 * @num_adcs: maximum number of ADC instances in the common registers 68 */ 69 struct stm32_adc_priv_cfg { 70 const struct stm32_adc_common_regs *regs; 71 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 72 u32 max_clk_rate_hz; 73 unsigned int has_syscfg; 74 unsigned int num_irqs; 75 unsigned int num_adcs; 76 }; 77 78 /** 79 * struct stm32_adc_priv - stm32 ADC core private data 80 * @irq: irq(s) for ADC block 81 * @domain: irq domain reference 82 * @aclk: clock reference for the analog circuitry 83 * @bclk: bus clock common for all ADCs, depends on part used 84 * @max_clk_rate: desired maximum clock rate 85 * @booster: booster supply reference 86 * @vdd: vdd supply reference 87 * @vdda: vdda analog supply reference 88 * @vref: regulator reference 89 * @vdd_uv: vdd supply voltage (microvolts) 90 * @vdda_uv: vdda supply voltage (microvolts) 91 * @cfg: compatible configuration data 92 * @common: common data for all ADC instances 93 * @ccr_bak: backup CCR in low power mode 94 * @syscfg: reference to syscon, system control registers 95 */ 96 struct stm32_adc_priv { 97 int irq[STM32_ADC_MAX_ADCS]; 98 struct irq_domain *domain; 99 struct clk *aclk; 100 struct clk *bclk; 101 u32 max_clk_rate; 102 struct regulator *booster; 103 struct regulator *vdd; 104 struct regulator *vdda; 105 struct regulator *vref; 106 int vdd_uv; 107 int vdda_uv; 108 const struct stm32_adc_priv_cfg *cfg; 109 struct stm32_adc_common common; 110 u32 ccr_bak; 111 struct regmap *syscfg; 112 }; 113 114 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 115 { 116 return container_of(com, struct stm32_adc_priv, common); 117 } 118 119 /* STM32F4 ADC internal common clock prescaler division ratios */ 120 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 121 122 /** 123 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 124 * @pdev: platform device 125 * @priv: stm32 ADC core private data 126 * Select clock prescaler used for analog conversions, before using ADC. 127 */ 128 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 129 struct stm32_adc_priv *priv) 130 { 131 unsigned long rate; 132 u32 val; 133 int i; 134 135 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 136 if (!priv->aclk) { 137 dev_err(&pdev->dev, "No 'adc' clock found\n"); 138 return -ENOENT; 139 } 140 141 rate = clk_get_rate(priv->aclk); 142 if (!rate) { 143 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 144 return -EINVAL; 145 } 146 147 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 148 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 149 break; 150 } 151 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 152 dev_err(&pdev->dev, "adc clk selection failed\n"); 153 return -EINVAL; 154 } 155 156 priv->common.rate = rate / stm32f4_pclk_div[i]; 157 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 158 val &= ~STM32F4_ADC_ADCPRE_MASK; 159 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 160 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 161 162 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 163 priv->common.rate / 1000); 164 165 return 0; 166 } 167 168 /** 169 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 170 * @ckmode: ADC clock mode, Async or sync with prescaler. 171 * @presc: prescaler bitfield for async clock mode 172 * @div: prescaler division ratio 173 */ 174 struct stm32h7_adc_ck_spec { 175 u32 ckmode; 176 u32 presc; 177 int div; 178 }; 179 180 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 181 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 182 { 0, 0, 1 }, 183 { 0, 1, 2 }, 184 { 0, 2, 4 }, 185 { 0, 3, 6 }, 186 { 0, 4, 8 }, 187 { 0, 5, 10 }, 188 { 0, 6, 12 }, 189 { 0, 7, 16 }, 190 { 0, 8, 32 }, 191 { 0, 9, 64 }, 192 { 0, 10, 128 }, 193 { 0, 11, 256 }, 194 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 195 { 1, 0, 1 }, 196 { 2, 0, 2 }, 197 { 3, 0, 4 }, 198 }; 199 200 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 201 struct stm32_adc_priv *priv) 202 { 203 u32 ckmode, presc, val; 204 unsigned long rate; 205 int i, div, duty; 206 207 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 208 if (!priv->bclk) { 209 dev_err(&pdev->dev, "No 'bus' clock found\n"); 210 return -ENOENT; 211 } 212 213 /* 214 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 215 * So, choice is to have bus clock mandatory and adc clock optional. 216 * If optional 'adc' clock has been found, then try to use it first. 217 */ 218 if (priv->aclk) { 219 /* 220 * Asynchronous clock modes (e.g. ckmode == 0) 221 * From spec: PLL output musn't exceed max rate 222 */ 223 rate = clk_get_rate(priv->aclk); 224 if (!rate) { 225 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 226 return -EINVAL; 227 } 228 229 /* If duty is an error, kindly use at least /2 divider */ 230 duty = clk_get_scaled_duty_cycle(priv->aclk, 100); 231 if (duty < 0) 232 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty); 233 234 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 235 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 236 presc = stm32h7_adc_ckmodes_spec[i].presc; 237 div = stm32h7_adc_ckmodes_spec[i].div; 238 239 if (ckmode) 240 continue; 241 242 /* 243 * For proper operation, clock duty cycle range is 49% 244 * to 51%. Apply at least /2 prescaler otherwise. 245 */ 246 if (div == 1 && (duty < 49 || duty > 51)) 247 continue; 248 249 if ((rate / div) <= priv->max_clk_rate) 250 goto out; 251 } 252 } 253 254 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 255 rate = clk_get_rate(priv->bclk); 256 if (!rate) { 257 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 258 return -EINVAL; 259 } 260 261 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); 262 if (duty < 0) 263 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty); 264 265 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 266 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 267 presc = stm32h7_adc_ckmodes_spec[i].presc; 268 div = stm32h7_adc_ckmodes_spec[i].div; 269 270 if (!ckmode) 271 continue; 272 273 if (div == 1 && (duty < 49 || duty > 51)) 274 continue; 275 276 if ((rate / div) <= priv->max_clk_rate) 277 goto out; 278 } 279 280 dev_err(&pdev->dev, "adc clk selection failed\n"); 281 return -EINVAL; 282 283 out: 284 /* rate used later by each ADC instance to control BOOST mode */ 285 priv->common.rate = rate / div; 286 287 /* Set common clock mode and prescaler */ 288 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 289 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 290 val |= ckmode << STM32H7_CKMODE_SHIFT; 291 val |= presc << STM32H7_PRESC_SHIFT; 292 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 293 294 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 295 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 296 297 return 0; 298 } 299 300 /* STM32F4 common registers definitions */ 301 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 302 .csr = STM32F4_ADC_CSR, 303 .ccr = STM32F4_ADC_CCR, 304 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3}, 305 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3}, 306 .ier = STM32F4_ADC_CR1, 307 .eocie_msk = STM32F4_EOCIE, 308 }; 309 310 /* STM32H7 common registers definitions */ 311 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 312 .csr = STM32H7_ADC_CSR, 313 .ccr = STM32H7_ADC_CCR, 314 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV}, 315 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV}, 316 .ier = STM32H7_ADC_IER, 317 .eocie_msk = STM32H7_EOCIE, 318 }; 319 320 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 321 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 322 }; 323 324 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 325 unsigned int adc) 326 { 327 u32 ier, offset = stm32_adc_offset[adc]; 328 329 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 330 331 return ier & priv->cfg->regs->eocie_msk; 332 } 333 334 /* ADC common interrupt for all instances */ 335 static void stm32_adc_irq_handler(struct irq_desc *desc) 336 { 337 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 338 struct irq_chip *chip = irq_desc_get_chip(desc); 339 int i; 340 u32 status; 341 342 chained_irq_enter(chip, desc); 343 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 344 345 /* 346 * End of conversion may be handled by using IRQ or DMA. There may be a 347 * race here when two conversions complete at the same time on several 348 * ADCs. EOC may be read 'set' for several ADCs, with: 349 * - an ADC configured to use DMA (EOC triggers the DMA request, and 350 * is then automatically cleared by DR read in hardware) 351 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 352 * be called in this case) 353 * So both EOC status bit in CSR and EOCIE control bit must be checked 354 * before invoking the interrupt handler (e.g. call ISR only for 355 * IRQ-enabled ADCs). 356 */ 357 for (i = 0; i < priv->cfg->num_adcs; i++) { 358 if ((status & priv->cfg->regs->eoc_msk[i] && 359 stm32_adc_eoc_enabled(priv, i)) || 360 (status & priv->cfg->regs->ovr_msk[i])) 361 generic_handle_domain_irq(priv->domain, i); 362 } 363 364 chained_irq_exit(chip, desc); 365 }; 366 367 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 368 irq_hw_number_t hwirq) 369 { 370 irq_set_chip_data(irq, d->host_data); 371 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 372 373 return 0; 374 } 375 376 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 377 { 378 irq_set_chip_and_handler(irq, NULL, NULL); 379 irq_set_chip_data(irq, NULL); 380 } 381 382 static const struct irq_domain_ops stm32_adc_domain_ops = { 383 .map = stm32_adc_domain_map, 384 .unmap = stm32_adc_domain_unmap, 385 .xlate = irq_domain_xlate_onecell, 386 }; 387 388 static int stm32_adc_irq_probe(struct platform_device *pdev, 389 struct stm32_adc_priv *priv) 390 { 391 struct device_node *np = pdev->dev.of_node; 392 unsigned int i; 393 394 /* 395 * Interrupt(s) must be provided, depending on the compatible: 396 * - stm32f4/h7 shares a common interrupt line. 397 * - stm32mp1, has one line per ADC 398 */ 399 for (i = 0; i < priv->cfg->num_irqs; i++) { 400 priv->irq[i] = platform_get_irq(pdev, i); 401 if (priv->irq[i] < 0) 402 return priv->irq[i]; 403 } 404 405 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 406 &stm32_adc_domain_ops, 407 priv); 408 if (!priv->domain) { 409 dev_err(&pdev->dev, "Failed to add irq domain\n"); 410 return -ENOMEM; 411 } 412 413 for (i = 0; i < priv->cfg->num_irqs; i++) { 414 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 415 irq_set_handler_data(priv->irq[i], priv); 416 } 417 418 return 0; 419 } 420 421 static void stm32_adc_irq_remove(struct platform_device *pdev, 422 struct stm32_adc_priv *priv) 423 { 424 int hwirq; 425 unsigned int i; 426 427 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 428 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 429 irq_domain_remove(priv->domain); 430 431 for (i = 0; i < priv->cfg->num_irqs; i++) 432 irq_set_chained_handler(priv->irq[i], NULL); 433 } 434 435 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 436 struct device *dev) 437 { 438 int ret; 439 440 /* 441 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 442 * switches (via PCSEL) which have reduced performances when their 443 * supply is below 2.7V (vdda by default): 444 * - Voltage booster can be used, to get full ADC performances 445 * (increases power consumption). 446 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 447 * 448 * Recommended settings for ANASWVDD and EN_BOOSTER: 449 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 450 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 451 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 452 */ 453 if (priv->vdda_uv < 2700000) { 454 if (priv->syscfg && priv->vdd_uv > 2700000) { 455 ret = regulator_enable(priv->vdd); 456 if (ret < 0) { 457 dev_err(dev, "vdd enable failed %d\n", ret); 458 return ret; 459 } 460 461 ret = regmap_write(priv->syscfg, 462 STM32MP1_SYSCFG_PMCSETR, 463 STM32MP1_SYSCFG_ANASWVDD_MASK); 464 if (ret < 0) { 465 regulator_disable(priv->vdd); 466 dev_err(dev, "vdd select failed, %d\n", ret); 467 return ret; 468 } 469 dev_dbg(dev, "analog switches supplied by vdd\n"); 470 471 return 0; 472 } 473 474 if (priv->booster) { 475 /* 476 * This is optional, as this is a trade-off between 477 * analog performance and power consumption. 478 */ 479 ret = regulator_enable(priv->booster); 480 if (ret < 0) { 481 dev_err(dev, "booster enable failed %d\n", ret); 482 return ret; 483 } 484 dev_dbg(dev, "analog switches supplied by booster\n"); 485 486 return 0; 487 } 488 } 489 490 /* Fallback using vdda (default), nothing to do */ 491 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 492 priv->vdda_uv); 493 494 return 0; 495 } 496 497 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 498 { 499 if (priv->vdda_uv < 2700000) { 500 if (priv->syscfg && priv->vdd_uv > 2700000) { 501 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 502 STM32MP1_SYSCFG_ANASWVDD_MASK); 503 regulator_disable(priv->vdd); 504 return; 505 } 506 if (priv->booster) 507 regulator_disable(priv->booster); 508 } 509 } 510 511 static int stm32_adc_core_hw_start(struct device *dev) 512 { 513 struct stm32_adc_common *common = dev_get_drvdata(dev); 514 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 515 int ret; 516 517 ret = regulator_enable(priv->vdda); 518 if (ret < 0) { 519 dev_err(dev, "vdda enable failed %d\n", ret); 520 return ret; 521 } 522 523 ret = regulator_get_voltage(priv->vdda); 524 if (ret < 0) { 525 dev_err(dev, "vdda get voltage failed, %d\n", ret); 526 goto err_vdda_disable; 527 } 528 priv->vdda_uv = ret; 529 530 ret = stm32_adc_core_switches_supply_en(priv, dev); 531 if (ret < 0) 532 goto err_vdda_disable; 533 534 ret = regulator_enable(priv->vref); 535 if (ret < 0) { 536 dev_err(dev, "vref enable failed\n"); 537 goto err_switches_dis; 538 } 539 540 ret = clk_prepare_enable(priv->bclk); 541 if (ret < 0) { 542 dev_err(dev, "bus clk enable failed\n"); 543 goto err_regulator_disable; 544 } 545 546 ret = clk_prepare_enable(priv->aclk); 547 if (ret < 0) { 548 dev_err(dev, "adc clk enable failed\n"); 549 goto err_bclk_disable; 550 } 551 552 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 553 554 return 0; 555 556 err_bclk_disable: 557 clk_disable_unprepare(priv->bclk); 558 err_regulator_disable: 559 regulator_disable(priv->vref); 560 err_switches_dis: 561 stm32_adc_core_switches_supply_dis(priv); 562 err_vdda_disable: 563 regulator_disable(priv->vdda); 564 565 return ret; 566 } 567 568 static void stm32_adc_core_hw_stop(struct device *dev) 569 { 570 struct stm32_adc_common *common = dev_get_drvdata(dev); 571 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 572 573 /* Backup CCR that may be lost (depends on power state to achieve) */ 574 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 575 clk_disable_unprepare(priv->aclk); 576 clk_disable_unprepare(priv->bclk); 577 regulator_disable(priv->vref); 578 stm32_adc_core_switches_supply_dis(priv); 579 regulator_disable(priv->vdda); 580 } 581 582 static int stm32_adc_core_switches_probe(struct device *dev, 583 struct stm32_adc_priv *priv) 584 { 585 struct device_node *np = dev->of_node; 586 int ret; 587 588 /* Analog switches supply can be controlled by syscfg (optional) */ 589 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 590 if (IS_ERR(priv->syscfg)) { 591 ret = PTR_ERR(priv->syscfg); 592 if (ret != -ENODEV) 593 return dev_err_probe(dev, ret, "Can't probe syscfg\n"); 594 595 priv->syscfg = NULL; 596 } 597 598 /* Booster can be used to supply analog switches (optional) */ 599 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 600 of_property_read_bool(np, "booster-supply")) { 601 priv->booster = devm_regulator_get_optional(dev, "booster"); 602 if (IS_ERR(priv->booster)) { 603 ret = PTR_ERR(priv->booster); 604 if (ret != -ENODEV) 605 return dev_err_probe(dev, ret, "can't get booster\n"); 606 607 priv->booster = NULL; 608 } 609 } 610 611 /* Vdd can be used to supply analog switches (optional) */ 612 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 613 of_property_read_bool(np, "vdd-supply")) { 614 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 615 if (IS_ERR(priv->vdd)) { 616 ret = PTR_ERR(priv->vdd); 617 if (ret != -ENODEV) 618 return dev_err_probe(dev, ret, "can't get vdd\n"); 619 620 priv->vdd = NULL; 621 } 622 } 623 624 if (priv->vdd) { 625 ret = regulator_enable(priv->vdd); 626 if (ret < 0) { 627 dev_err(dev, "vdd enable failed %d\n", ret); 628 return ret; 629 } 630 631 ret = regulator_get_voltage(priv->vdd); 632 if (ret < 0) { 633 dev_err(dev, "vdd get voltage failed %d\n", ret); 634 regulator_disable(priv->vdd); 635 return ret; 636 } 637 priv->vdd_uv = ret; 638 639 regulator_disable(priv->vdd); 640 } 641 642 return 0; 643 } 644 645 static int stm32_adc_probe(struct platform_device *pdev) 646 { 647 struct stm32_adc_priv *priv; 648 struct device *dev = &pdev->dev; 649 struct device_node *np = pdev->dev.of_node; 650 struct resource *res; 651 u32 max_rate; 652 int ret; 653 654 if (!pdev->dev.of_node) 655 return -ENODEV; 656 657 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 658 if (!priv) 659 return -ENOMEM; 660 platform_set_drvdata(pdev, &priv->common); 661 662 priv->cfg = (const struct stm32_adc_priv_cfg *) 663 of_match_device(dev->driver->of_match_table, dev)->data; 664 spin_lock_init(&priv->common.lock); 665 666 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 667 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 668 if (IS_ERR(priv->common.base)) 669 return PTR_ERR(priv->common.base); 670 priv->common.phys_base = res->start; 671 672 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 673 if (IS_ERR(priv->vdda)) 674 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), 675 "vdda get failed\n"); 676 677 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 678 if (IS_ERR(priv->vref)) 679 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), 680 "vref get failed\n"); 681 682 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); 683 if (IS_ERR(priv->aclk)) 684 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), 685 "Can't get 'adc' clock\n"); 686 687 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); 688 if (IS_ERR(priv->bclk)) 689 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), 690 "Can't get 'bus' clock\n"); 691 692 ret = stm32_adc_core_switches_probe(dev, priv); 693 if (ret) 694 return ret; 695 696 pm_runtime_get_noresume(dev); 697 pm_runtime_set_active(dev); 698 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 699 pm_runtime_use_autosuspend(dev); 700 pm_runtime_enable(dev); 701 702 ret = stm32_adc_core_hw_start(dev); 703 if (ret) 704 goto err_pm_stop; 705 706 ret = regulator_get_voltage(priv->vref); 707 if (ret < 0) { 708 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 709 goto err_hw_stop; 710 } 711 priv->common.vref_mv = ret / 1000; 712 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 713 714 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 715 &max_rate); 716 if (!ret) 717 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 718 else 719 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 720 721 ret = priv->cfg->clk_sel(pdev, priv); 722 if (ret < 0) 723 goto err_hw_stop; 724 725 ret = stm32_adc_irq_probe(pdev, priv); 726 if (ret < 0) 727 goto err_hw_stop; 728 729 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 730 if (ret < 0) { 731 dev_err(&pdev->dev, "failed to populate DT children\n"); 732 goto err_irq_remove; 733 } 734 735 pm_runtime_mark_last_busy(dev); 736 pm_runtime_put_autosuspend(dev); 737 738 return 0; 739 740 err_irq_remove: 741 stm32_adc_irq_remove(pdev, priv); 742 err_hw_stop: 743 stm32_adc_core_hw_stop(dev); 744 err_pm_stop: 745 pm_runtime_disable(dev); 746 pm_runtime_set_suspended(dev); 747 pm_runtime_put_noidle(dev); 748 749 return ret; 750 } 751 752 static int stm32_adc_remove(struct platform_device *pdev) 753 { 754 struct stm32_adc_common *common = platform_get_drvdata(pdev); 755 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 756 757 pm_runtime_get_sync(&pdev->dev); 758 of_platform_depopulate(&pdev->dev); 759 stm32_adc_irq_remove(pdev, priv); 760 stm32_adc_core_hw_stop(&pdev->dev); 761 pm_runtime_disable(&pdev->dev); 762 pm_runtime_set_suspended(&pdev->dev); 763 pm_runtime_put_noidle(&pdev->dev); 764 765 return 0; 766 } 767 768 static int stm32_adc_core_runtime_suspend(struct device *dev) 769 { 770 stm32_adc_core_hw_stop(dev); 771 772 return 0; 773 } 774 775 static int stm32_adc_core_runtime_resume(struct device *dev) 776 { 777 return stm32_adc_core_hw_start(dev); 778 } 779 780 static int stm32_adc_core_runtime_idle(struct device *dev) 781 { 782 pm_runtime_mark_last_busy(dev); 783 784 return 0; 785 } 786 787 static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops, 788 stm32_adc_core_runtime_suspend, 789 stm32_adc_core_runtime_resume, 790 stm32_adc_core_runtime_idle); 791 792 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 793 .regs = &stm32f4_adc_common_regs, 794 .clk_sel = stm32f4_adc_clk_sel, 795 .max_clk_rate_hz = 36000000, 796 .num_irqs = 1, 797 .num_adcs = 3, 798 }; 799 800 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 801 .regs = &stm32h7_adc_common_regs, 802 .clk_sel = stm32h7_adc_clk_sel, 803 .max_clk_rate_hz = 36000000, 804 .has_syscfg = HAS_VBOOSTER, 805 .num_irqs = 1, 806 .num_adcs = 2, 807 }; 808 809 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 810 .regs = &stm32h7_adc_common_regs, 811 .clk_sel = stm32h7_adc_clk_sel, 812 .max_clk_rate_hz = 36000000, 813 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 814 .num_irqs = 2, 815 .num_adcs = 2, 816 }; 817 818 static const struct of_device_id stm32_adc_of_match[] = { 819 { 820 .compatible = "st,stm32f4-adc-core", 821 .data = (void *)&stm32f4_adc_priv_cfg 822 }, { 823 .compatible = "st,stm32h7-adc-core", 824 .data = (void *)&stm32h7_adc_priv_cfg 825 }, { 826 .compatible = "st,stm32mp1-adc-core", 827 .data = (void *)&stm32mp1_adc_priv_cfg 828 }, { 829 }, 830 }; 831 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 832 833 static struct platform_driver stm32_adc_driver = { 834 .probe = stm32_adc_probe, 835 .remove = stm32_adc_remove, 836 .driver = { 837 .name = "stm32-adc-core", 838 .of_match_table = stm32_adc_of_match, 839 .pm = pm_ptr(&stm32_adc_core_pm_ops), 840 }, 841 }; 842 module_platform_driver(stm32_adc_driver); 843 844 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 845 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 846 MODULE_LICENSE("GPL v2"); 847 MODULE_ALIAS("platform:stm32-adc-core"); 848