1 /* 2 * This file is part of STM32 ADC driver 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 6 * 7 * Inspired from: fsl-imx25-tsadc 8 * 9 * License type: GPLv2 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License version 2 as published by 13 * the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 * or FITNESS FOR A PARTICULAR PURPOSE. 18 * See the GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along with 21 * this program. If not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include <linux/clk.h> 25 #include <linux/interrupt.h> 26 #include <linux/irqchip/chained_irq.h> 27 #include <linux/irqdesc.h> 28 #include <linux/irqdomain.h> 29 #include <linux/module.h> 30 #include <linux/of_device.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 34 #include "stm32-adc-core.h" 35 36 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ 37 #define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 38 #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) 39 40 /* STM32F4_ADC_CSR - bit fields */ 41 #define STM32F4_EOC3 BIT(17) 42 #define STM32F4_EOC2 BIT(9) 43 #define STM32F4_EOC1 BIT(1) 44 45 /* STM32F4_ADC_CCR - bit fields */ 46 #define STM32F4_ADC_ADCPRE_SHIFT 16 47 #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16) 48 49 /* STM32 F4 maximum analog clock rate (from datasheet) */ 50 #define STM32F4_ADC_MAX_CLK_RATE 36000000 51 52 /* STM32H7 - common registers for all ADC instances */ 53 #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 54 #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) 55 56 /* STM32H7_ADC_CSR - bit fields */ 57 #define STM32H7_EOC_SLV BIT(18) 58 #define STM32H7_EOC_MST BIT(2) 59 60 /* STM32H7_ADC_CCR - bit fields */ 61 #define STM32H7_PRESC_SHIFT 18 62 #define STM32H7_PRESC_MASK GENMASK(21, 18) 63 #define STM32H7_CKMODE_SHIFT 16 64 #define STM32H7_CKMODE_MASK GENMASK(17, 16) 65 66 /* STM32 H7 maximum analog clock rate (from datasheet) */ 67 #define STM32H7_ADC_MAX_CLK_RATE 36000000 68 69 /** 70 * stm32_adc_common_regs - stm32 common registers, compatible dependent data 71 * @csr: common status register offset 72 * @eoc1: adc1 end of conversion flag in @csr 73 * @eoc2: adc2 end of conversion flag in @csr 74 * @eoc3: adc3 end of conversion flag in @csr 75 */ 76 struct stm32_adc_common_regs { 77 u32 csr; 78 u32 eoc1_msk; 79 u32 eoc2_msk; 80 u32 eoc3_msk; 81 }; 82 83 struct stm32_adc_priv; 84 85 /** 86 * stm32_adc_priv_cfg - stm32 core compatible configuration data 87 * @regs: common registers for all instances 88 * @clk_sel: clock selection routine 89 */ 90 struct stm32_adc_priv_cfg { 91 const struct stm32_adc_common_regs *regs; 92 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 93 }; 94 95 /** 96 * struct stm32_adc_priv - stm32 ADC core private data 97 * @irq: irq for ADC block 98 * @domain: irq domain reference 99 * @aclk: clock reference for the analog circuitry 100 * @bclk: bus clock common for all ADCs, depends on part used 101 * @vref: regulator reference 102 * @cfg: compatible configuration data 103 * @common: common data for all ADC instances 104 */ 105 struct stm32_adc_priv { 106 int irq; 107 struct irq_domain *domain; 108 struct clk *aclk; 109 struct clk *bclk; 110 struct regulator *vref; 111 const struct stm32_adc_priv_cfg *cfg; 112 struct stm32_adc_common common; 113 }; 114 115 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 116 { 117 return container_of(com, struct stm32_adc_priv, common); 118 } 119 120 /* STM32F4 ADC internal common clock prescaler division ratios */ 121 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 122 123 /** 124 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 125 * @priv: stm32 ADC core private data 126 * Select clock prescaler used for analog conversions, before using ADC. 127 */ 128 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 129 struct stm32_adc_priv *priv) 130 { 131 unsigned long rate; 132 u32 val; 133 int i; 134 135 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 136 if (!priv->aclk) { 137 dev_err(&pdev->dev, "No 'adc' clock found\n"); 138 return -ENOENT; 139 } 140 141 rate = clk_get_rate(priv->aclk); 142 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 143 if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE) 144 break; 145 } 146 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 147 dev_err(&pdev->dev, "adc clk selection failed\n"); 148 return -EINVAL; 149 } 150 151 priv->common.rate = rate / stm32f4_pclk_div[i]; 152 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 153 val &= ~STM32F4_ADC_ADCPRE_MASK; 154 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 155 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 156 157 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 158 priv->common.rate / 1000); 159 160 return 0; 161 } 162 163 /** 164 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 165 * @ckmode: ADC clock mode, Async or sync with prescaler. 166 * @presc: prescaler bitfield for async clock mode 167 * @div: prescaler division ratio 168 */ 169 struct stm32h7_adc_ck_spec { 170 u32 ckmode; 171 u32 presc; 172 int div; 173 }; 174 175 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 176 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 177 { 0, 0, 1 }, 178 { 0, 1, 2 }, 179 { 0, 2, 4 }, 180 { 0, 3, 6 }, 181 { 0, 4, 8 }, 182 { 0, 5, 10 }, 183 { 0, 6, 12 }, 184 { 0, 7, 16 }, 185 { 0, 8, 32 }, 186 { 0, 9, 64 }, 187 { 0, 10, 128 }, 188 { 0, 11, 256 }, 189 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 190 { 1, 0, 1 }, 191 { 2, 0, 2 }, 192 { 3, 0, 4 }, 193 }; 194 195 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 196 struct stm32_adc_priv *priv) 197 { 198 u32 ckmode, presc, val; 199 unsigned long rate; 200 int i, div; 201 202 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 203 if (!priv->bclk) { 204 dev_err(&pdev->dev, "No 'bus' clock found\n"); 205 return -ENOENT; 206 } 207 208 /* 209 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 210 * So, choice is to have bus clock mandatory and adc clock optional. 211 * If optional 'adc' clock has been found, then try to use it first. 212 */ 213 if (priv->aclk) { 214 /* 215 * Asynchronous clock modes (e.g. ckmode == 0) 216 * From spec: PLL output musn't exceed max rate 217 */ 218 rate = clk_get_rate(priv->aclk); 219 220 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 221 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 222 presc = stm32h7_adc_ckmodes_spec[i].presc; 223 div = stm32h7_adc_ckmodes_spec[i].div; 224 225 if (ckmode) 226 continue; 227 228 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) 229 goto out; 230 } 231 } 232 233 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 234 rate = clk_get_rate(priv->bclk); 235 236 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 237 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 238 presc = stm32h7_adc_ckmodes_spec[i].presc; 239 div = stm32h7_adc_ckmodes_spec[i].div; 240 241 if (!ckmode) 242 continue; 243 244 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) 245 goto out; 246 } 247 248 dev_err(&pdev->dev, "adc clk selection failed\n"); 249 return -EINVAL; 250 251 out: 252 /* rate used later by each ADC instance to control BOOST mode */ 253 priv->common.rate = rate / div; 254 255 /* Set common clock mode and prescaler */ 256 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 257 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 258 val |= ckmode << STM32H7_CKMODE_SHIFT; 259 val |= presc << STM32H7_PRESC_SHIFT; 260 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 261 262 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 263 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 264 265 return 0; 266 } 267 268 /* STM32F4 common registers definitions */ 269 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 270 .csr = STM32F4_ADC_CSR, 271 .eoc1_msk = STM32F4_EOC1, 272 .eoc2_msk = STM32F4_EOC2, 273 .eoc3_msk = STM32F4_EOC3, 274 }; 275 276 /* STM32H7 common registers definitions */ 277 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 278 .csr = STM32H7_ADC_CSR, 279 .eoc1_msk = STM32H7_EOC_MST, 280 .eoc2_msk = STM32H7_EOC_SLV, 281 }; 282 283 /* ADC common interrupt for all instances */ 284 static void stm32_adc_irq_handler(struct irq_desc *desc) 285 { 286 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 287 struct irq_chip *chip = irq_desc_get_chip(desc); 288 u32 status; 289 290 chained_irq_enter(chip, desc); 291 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 292 293 if (status & priv->cfg->regs->eoc1_msk) 294 generic_handle_irq(irq_find_mapping(priv->domain, 0)); 295 296 if (status & priv->cfg->regs->eoc2_msk) 297 generic_handle_irq(irq_find_mapping(priv->domain, 1)); 298 299 if (status & priv->cfg->regs->eoc3_msk) 300 generic_handle_irq(irq_find_mapping(priv->domain, 2)); 301 302 chained_irq_exit(chip, desc); 303 }; 304 305 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 306 irq_hw_number_t hwirq) 307 { 308 irq_set_chip_data(irq, d->host_data); 309 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 310 311 return 0; 312 } 313 314 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 315 { 316 irq_set_chip_and_handler(irq, NULL, NULL); 317 irq_set_chip_data(irq, NULL); 318 } 319 320 static const struct irq_domain_ops stm32_adc_domain_ops = { 321 .map = stm32_adc_domain_map, 322 .unmap = stm32_adc_domain_unmap, 323 .xlate = irq_domain_xlate_onecell, 324 }; 325 326 static int stm32_adc_irq_probe(struct platform_device *pdev, 327 struct stm32_adc_priv *priv) 328 { 329 struct device_node *np = pdev->dev.of_node; 330 331 priv->irq = platform_get_irq(pdev, 0); 332 if (priv->irq < 0) { 333 dev_err(&pdev->dev, "failed to get irq\n"); 334 return priv->irq; 335 } 336 337 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 338 &stm32_adc_domain_ops, 339 priv); 340 if (!priv->domain) { 341 dev_err(&pdev->dev, "Failed to add irq domain\n"); 342 return -ENOMEM; 343 } 344 345 irq_set_chained_handler(priv->irq, stm32_adc_irq_handler); 346 irq_set_handler_data(priv->irq, priv); 347 348 return 0; 349 } 350 351 static void stm32_adc_irq_remove(struct platform_device *pdev, 352 struct stm32_adc_priv *priv) 353 { 354 int hwirq; 355 356 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 357 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 358 irq_domain_remove(priv->domain); 359 irq_set_chained_handler(priv->irq, NULL); 360 } 361 362 static int stm32_adc_probe(struct platform_device *pdev) 363 { 364 struct stm32_adc_priv *priv; 365 struct device *dev = &pdev->dev; 366 struct device_node *np = pdev->dev.of_node; 367 struct resource *res; 368 int ret; 369 370 if (!pdev->dev.of_node) 371 return -ENODEV; 372 373 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 374 if (!priv) 375 return -ENOMEM; 376 377 priv->cfg = (const struct stm32_adc_priv_cfg *) 378 of_match_device(dev->driver->of_match_table, dev)->data; 379 380 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 381 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 382 if (IS_ERR(priv->common.base)) 383 return PTR_ERR(priv->common.base); 384 priv->common.phys_base = res->start; 385 386 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 387 if (IS_ERR(priv->vref)) { 388 ret = PTR_ERR(priv->vref); 389 dev_err(&pdev->dev, "vref get failed, %d\n", ret); 390 return ret; 391 } 392 393 ret = regulator_enable(priv->vref); 394 if (ret < 0) { 395 dev_err(&pdev->dev, "vref enable failed\n"); 396 return ret; 397 } 398 399 ret = regulator_get_voltage(priv->vref); 400 if (ret < 0) { 401 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 402 goto err_regulator_disable; 403 } 404 priv->common.vref_mv = ret / 1000; 405 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 406 407 priv->aclk = devm_clk_get(&pdev->dev, "adc"); 408 if (IS_ERR(priv->aclk)) { 409 ret = PTR_ERR(priv->aclk); 410 if (ret == -ENOENT) { 411 priv->aclk = NULL; 412 } else { 413 dev_err(&pdev->dev, "Can't get 'adc' clock\n"); 414 goto err_regulator_disable; 415 } 416 } 417 418 if (priv->aclk) { 419 ret = clk_prepare_enable(priv->aclk); 420 if (ret < 0) { 421 dev_err(&pdev->dev, "adc clk enable failed\n"); 422 goto err_regulator_disable; 423 } 424 } 425 426 priv->bclk = devm_clk_get(&pdev->dev, "bus"); 427 if (IS_ERR(priv->bclk)) { 428 ret = PTR_ERR(priv->bclk); 429 if (ret == -ENOENT) { 430 priv->bclk = NULL; 431 } else { 432 dev_err(&pdev->dev, "Can't get 'bus' clock\n"); 433 goto err_aclk_disable; 434 } 435 } 436 437 if (priv->bclk) { 438 ret = clk_prepare_enable(priv->bclk); 439 if (ret < 0) { 440 dev_err(&pdev->dev, "adc clk enable failed\n"); 441 goto err_aclk_disable; 442 } 443 } 444 445 ret = priv->cfg->clk_sel(pdev, priv); 446 if (ret < 0) 447 goto err_bclk_disable; 448 449 ret = stm32_adc_irq_probe(pdev, priv); 450 if (ret < 0) 451 goto err_bclk_disable; 452 453 platform_set_drvdata(pdev, &priv->common); 454 455 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 456 if (ret < 0) { 457 dev_err(&pdev->dev, "failed to populate DT children\n"); 458 goto err_irq_remove; 459 } 460 461 return 0; 462 463 err_irq_remove: 464 stm32_adc_irq_remove(pdev, priv); 465 466 err_bclk_disable: 467 if (priv->bclk) 468 clk_disable_unprepare(priv->bclk); 469 470 err_aclk_disable: 471 if (priv->aclk) 472 clk_disable_unprepare(priv->aclk); 473 474 err_regulator_disable: 475 regulator_disable(priv->vref); 476 477 return ret; 478 } 479 480 static int stm32_adc_remove(struct platform_device *pdev) 481 { 482 struct stm32_adc_common *common = platform_get_drvdata(pdev); 483 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 484 485 of_platform_depopulate(&pdev->dev); 486 stm32_adc_irq_remove(pdev, priv); 487 if (priv->bclk) 488 clk_disable_unprepare(priv->bclk); 489 if (priv->aclk) 490 clk_disable_unprepare(priv->aclk); 491 regulator_disable(priv->vref); 492 493 return 0; 494 } 495 496 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 497 .regs = &stm32f4_adc_common_regs, 498 .clk_sel = stm32f4_adc_clk_sel, 499 }; 500 501 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 502 .regs = &stm32h7_adc_common_regs, 503 .clk_sel = stm32h7_adc_clk_sel, 504 }; 505 506 static const struct of_device_id stm32_adc_of_match[] = { 507 { 508 .compatible = "st,stm32f4-adc-core", 509 .data = (void *)&stm32f4_adc_priv_cfg 510 }, { 511 .compatible = "st,stm32h7-adc-core", 512 .data = (void *)&stm32h7_adc_priv_cfg 513 }, { 514 }, 515 }; 516 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 517 518 static struct platform_driver stm32_adc_driver = { 519 .probe = stm32_adc_probe, 520 .remove = stm32_adc_remove, 521 .driver = { 522 .name = "stm32-adc-core", 523 .of_match_table = stm32_adc_of_match, 524 }, 525 }; 526 module_platform_driver(stm32_adc_driver); 527 528 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 529 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 530 MODULE_LICENSE("GPL v2"); 531 MODULE_ALIAS("platform:stm32-adc-core"); 532