1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdesc.h> 17 #include <linux/irqdomain.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/of_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <linux/units.h> 26 27 #include "stm32-adc-core.h" 28 29 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 30 31 /* SYSCFG registers */ 32 #define STM32MP1_SYSCFG_PMCSETR 0x04 33 #define STM32MP1_SYSCFG_PMCCLRR 0x44 34 35 /* SYSCFG bit fields */ 36 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 37 38 /* SYSCFG capability flags */ 39 #define HAS_VBOOSTER BIT(0) 40 #define HAS_ANASWVDD BIT(1) 41 42 /** 43 * struct stm32_adc_common_regs - stm32 common registers 44 * @csr: common status register offset 45 * @ccr: common control register offset 46 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n 47 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n 48 * @ier: interrupt enable register offset for each adc 49 * @eocie_msk: end of conversion interrupt enable mask in @ier 50 */ 51 struct stm32_adc_common_regs { 52 u32 csr; 53 u32 ccr; 54 u32 eoc_msk[STM32_ADC_MAX_ADCS]; 55 u32 ovr_msk[STM32_ADC_MAX_ADCS]; 56 u32 ier; 57 u32 eocie_msk; 58 }; 59 60 struct stm32_adc_priv; 61 62 /** 63 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 64 * @regs: common registers for all instances 65 * @clk_sel: clock selection routine 66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 67 * @ipid: adc identification number 68 * @has_syscfg: SYSCFG capability flags 69 * @num_irqs: number of interrupt lines 70 * @num_adcs: maximum number of ADC instances in the common registers 71 */ 72 struct stm32_adc_priv_cfg { 73 const struct stm32_adc_common_regs *regs; 74 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 75 u32 max_clk_rate_hz; 76 u32 ipid; 77 unsigned int has_syscfg; 78 unsigned int num_irqs; 79 unsigned int num_adcs; 80 }; 81 82 /** 83 * struct stm32_adc_priv - stm32 ADC core private data 84 * @irq: irq(s) for ADC block 85 * @nb_adc_max: actual maximum number of instance per ADC block 86 * @domain: irq domain reference 87 * @aclk: clock reference for the analog circuitry 88 * @bclk: bus clock common for all ADCs, depends on part used 89 * @max_clk_rate: desired maximum clock rate 90 * @booster: booster supply reference 91 * @vdd: vdd supply reference 92 * @vdda: vdda analog supply reference 93 * @vref: regulator reference 94 * @vdd_uv: vdd supply voltage (microvolts) 95 * @vdda_uv: vdda supply voltage (microvolts) 96 * @cfg: compatible configuration data 97 * @common: common data for all ADC instances 98 * @ccr_bak: backup CCR in low power mode 99 * @syscfg: reference to syscon, system control registers 100 */ 101 struct stm32_adc_priv { 102 int irq[STM32_ADC_MAX_ADCS]; 103 unsigned int nb_adc_max; 104 struct irq_domain *domain; 105 struct clk *aclk; 106 struct clk *bclk; 107 u32 max_clk_rate; 108 struct regulator *booster; 109 struct regulator *vdd; 110 struct regulator *vdda; 111 struct regulator *vref; 112 int vdd_uv; 113 int vdda_uv; 114 const struct stm32_adc_priv_cfg *cfg; 115 struct stm32_adc_common common; 116 u32 ccr_bak; 117 struct regmap *syscfg; 118 }; 119 120 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 121 { 122 return container_of(com, struct stm32_adc_priv, common); 123 } 124 125 /* STM32F4 ADC internal common clock prescaler division ratios */ 126 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 127 128 /** 129 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 130 * @pdev: platform device 131 * @priv: stm32 ADC core private data 132 * Select clock prescaler used for analog conversions, before using ADC. 133 */ 134 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 135 struct stm32_adc_priv *priv) 136 { 137 unsigned long rate; 138 u32 val; 139 int i; 140 141 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 142 if (!priv->aclk) { 143 dev_err(&pdev->dev, "No 'adc' clock found\n"); 144 return -ENOENT; 145 } 146 147 rate = clk_get_rate(priv->aclk); 148 if (!rate) { 149 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 150 return -EINVAL; 151 } 152 153 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 154 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 155 break; 156 } 157 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 158 dev_err(&pdev->dev, "adc clk selection failed\n"); 159 return -EINVAL; 160 } 161 162 priv->common.rate = rate / stm32f4_pclk_div[i]; 163 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 164 val &= ~STM32F4_ADC_ADCPRE_MASK; 165 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 166 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 167 168 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 169 priv->common.rate / 1000); 170 171 return 0; 172 } 173 174 /** 175 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 176 * @ckmode: ADC clock mode, Async or sync with prescaler. 177 * @presc: prescaler bitfield for async clock mode 178 * @div: prescaler division ratio 179 */ 180 struct stm32h7_adc_ck_spec { 181 u32 ckmode; 182 u32 presc; 183 int div; 184 }; 185 186 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 187 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 188 { 0, 0, 1 }, 189 { 0, 1, 2 }, 190 { 0, 2, 4 }, 191 { 0, 3, 6 }, 192 { 0, 4, 8 }, 193 { 0, 5, 10 }, 194 { 0, 6, 12 }, 195 { 0, 7, 16 }, 196 { 0, 8, 32 }, 197 { 0, 9, 64 }, 198 { 0, 10, 128 }, 199 { 0, 11, 256 }, 200 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 201 { 1, 0, 1 }, 202 { 2, 0, 2 }, 203 { 3, 0, 4 }, 204 }; 205 206 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 207 struct stm32_adc_priv *priv) 208 { 209 u32 ckmode, presc, val; 210 unsigned long rate; 211 int i, div, duty; 212 213 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 214 if (!priv->bclk) { 215 dev_err(&pdev->dev, "No 'bus' clock found\n"); 216 return -ENOENT; 217 } 218 219 /* 220 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 221 * So, choice is to have bus clock mandatory and adc clock optional. 222 * If optional 'adc' clock has been found, then try to use it first. 223 */ 224 if (priv->aclk) { 225 /* 226 * Asynchronous clock modes (e.g. ckmode == 0) 227 * From spec: PLL output musn't exceed max rate 228 */ 229 rate = clk_get_rate(priv->aclk); 230 if (!rate) { 231 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 232 return -EINVAL; 233 } 234 235 /* If duty is an error, kindly use at least /2 divider */ 236 duty = clk_get_scaled_duty_cycle(priv->aclk, 100); 237 if (duty < 0) 238 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty); 239 240 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 241 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 242 presc = stm32h7_adc_ckmodes_spec[i].presc; 243 div = stm32h7_adc_ckmodes_spec[i].div; 244 245 if (ckmode) 246 continue; 247 248 /* 249 * For proper operation, clock duty cycle range is 49% 250 * to 51%. Apply at least /2 prescaler otherwise. 251 */ 252 if (div == 1 && (duty < 49 || duty > 51)) 253 continue; 254 255 if ((rate / div) <= priv->max_clk_rate) 256 goto out; 257 } 258 } 259 260 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 261 rate = clk_get_rate(priv->bclk); 262 if (!rate) { 263 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 264 return -EINVAL; 265 } 266 267 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); 268 if (duty < 0) 269 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty); 270 271 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 272 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 273 presc = stm32h7_adc_ckmodes_spec[i].presc; 274 div = stm32h7_adc_ckmodes_spec[i].div; 275 276 if (!ckmode) 277 continue; 278 279 if (div == 1 && (duty < 49 || duty > 51)) 280 continue; 281 282 if ((rate / div) <= priv->max_clk_rate) 283 goto out; 284 } 285 286 dev_err(&pdev->dev, "adc clk selection failed\n"); 287 return -EINVAL; 288 289 out: 290 /* rate used later by each ADC instance to control BOOST mode */ 291 priv->common.rate = rate / div; 292 293 /* Set common clock mode and prescaler */ 294 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 295 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 296 val |= ckmode << STM32H7_CKMODE_SHIFT; 297 val |= presc << STM32H7_PRESC_SHIFT; 298 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 299 300 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 301 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 302 303 return 0; 304 } 305 306 /* STM32F4 common registers definitions */ 307 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 308 .csr = STM32F4_ADC_CSR, 309 .ccr = STM32F4_ADC_CCR, 310 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3 }, 311 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3 }, 312 .ier = STM32F4_ADC_CR1, 313 .eocie_msk = STM32F4_EOCIE, 314 }; 315 316 /* STM32H7 common registers definitions */ 317 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 318 .csr = STM32H7_ADC_CSR, 319 .ccr = STM32H7_ADC_CCR, 320 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV }, 321 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV }, 322 .ier = STM32H7_ADC_IER, 323 .eocie_msk = STM32H7_EOCIE, 324 }; 325 326 /* STM32MP13 common registers definitions */ 327 static const struct stm32_adc_common_regs stm32mp13_adc_common_regs = { 328 .csr = STM32H7_ADC_CSR, 329 .ccr = STM32H7_ADC_CCR, 330 .eoc_msk = { STM32H7_EOC_MST }, 331 .ovr_msk = { STM32H7_OVR_MST }, 332 .ier = STM32H7_ADC_IER, 333 .eocie_msk = STM32H7_EOCIE, 334 }; 335 336 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 337 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 338 }; 339 340 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 341 unsigned int adc) 342 { 343 u32 ier, offset = stm32_adc_offset[adc]; 344 345 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 346 347 return ier & priv->cfg->regs->eocie_msk; 348 } 349 350 /* ADC common interrupt for all instances */ 351 static void stm32_adc_irq_handler(struct irq_desc *desc) 352 { 353 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 354 struct irq_chip *chip = irq_desc_get_chip(desc); 355 int i; 356 u32 status; 357 358 chained_irq_enter(chip, desc); 359 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 360 361 /* 362 * End of conversion may be handled by using IRQ or DMA. There may be a 363 * race here when two conversions complete at the same time on several 364 * ADCs. EOC may be read 'set' for several ADCs, with: 365 * - an ADC configured to use DMA (EOC triggers the DMA request, and 366 * is then automatically cleared by DR read in hardware) 367 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 368 * be called in this case) 369 * So both EOC status bit in CSR and EOCIE control bit must be checked 370 * before invoking the interrupt handler (e.g. call ISR only for 371 * IRQ-enabled ADCs). 372 */ 373 for (i = 0; i < priv->nb_adc_max; i++) { 374 if ((status & priv->cfg->regs->eoc_msk[i] && 375 stm32_adc_eoc_enabled(priv, i)) || 376 (status & priv->cfg->regs->ovr_msk[i])) 377 generic_handle_domain_irq(priv->domain, i); 378 } 379 380 chained_irq_exit(chip, desc); 381 }; 382 383 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 384 irq_hw_number_t hwirq) 385 { 386 irq_set_chip_data(irq, d->host_data); 387 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 388 389 return 0; 390 } 391 392 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 393 { 394 irq_set_chip_and_handler(irq, NULL, NULL); 395 irq_set_chip_data(irq, NULL); 396 } 397 398 static const struct irq_domain_ops stm32_adc_domain_ops = { 399 .map = stm32_adc_domain_map, 400 .unmap = stm32_adc_domain_unmap, 401 .xlate = irq_domain_xlate_onecell, 402 }; 403 404 static int stm32_adc_irq_probe(struct platform_device *pdev, 405 struct stm32_adc_priv *priv) 406 { 407 struct device_node *np = pdev->dev.of_node; 408 unsigned int i; 409 410 /* 411 * Interrupt(s) must be provided, depending on the compatible: 412 * - stm32f4/h7 shares a common interrupt line. 413 * - stm32mp1, has one line per ADC 414 */ 415 for (i = 0; i < priv->cfg->num_irqs; i++) { 416 priv->irq[i] = platform_get_irq(pdev, i); 417 if (priv->irq[i] < 0) 418 return priv->irq[i]; 419 } 420 421 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 422 &stm32_adc_domain_ops, 423 priv); 424 if (!priv->domain) { 425 dev_err(&pdev->dev, "Failed to add irq domain\n"); 426 return -ENOMEM; 427 } 428 429 for (i = 0; i < priv->cfg->num_irqs; i++) { 430 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 431 irq_set_handler_data(priv->irq[i], priv); 432 } 433 434 return 0; 435 } 436 437 static void stm32_adc_irq_remove(struct platform_device *pdev, 438 struct stm32_adc_priv *priv) 439 { 440 int hwirq; 441 unsigned int i; 442 443 for (hwirq = 0; hwirq < priv->nb_adc_max; hwirq++) 444 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 445 irq_domain_remove(priv->domain); 446 447 for (i = 0; i < priv->cfg->num_irqs; i++) 448 irq_set_chained_handler(priv->irq[i], NULL); 449 } 450 451 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 452 struct device *dev) 453 { 454 int ret; 455 456 /* 457 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 458 * switches (via PCSEL) which have reduced performances when their 459 * supply is below 2.7V (vdda by default): 460 * - Voltage booster can be used, to get full ADC performances 461 * (increases power consumption). 462 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 463 * 464 * Recommended settings for ANASWVDD and EN_BOOSTER: 465 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 466 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 467 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 468 */ 469 if (priv->vdda_uv < 2700000) { 470 if (priv->syscfg && priv->vdd_uv > 2700000) { 471 ret = regulator_enable(priv->vdd); 472 if (ret < 0) { 473 dev_err(dev, "vdd enable failed %d\n", ret); 474 return ret; 475 } 476 477 ret = regmap_write(priv->syscfg, 478 STM32MP1_SYSCFG_PMCSETR, 479 STM32MP1_SYSCFG_ANASWVDD_MASK); 480 if (ret < 0) { 481 regulator_disable(priv->vdd); 482 dev_err(dev, "vdd select failed, %d\n", ret); 483 return ret; 484 } 485 dev_dbg(dev, "analog switches supplied by vdd\n"); 486 487 return 0; 488 } 489 490 if (priv->booster) { 491 /* 492 * This is optional, as this is a trade-off between 493 * analog performance and power consumption. 494 */ 495 ret = regulator_enable(priv->booster); 496 if (ret < 0) { 497 dev_err(dev, "booster enable failed %d\n", ret); 498 return ret; 499 } 500 dev_dbg(dev, "analog switches supplied by booster\n"); 501 502 return 0; 503 } 504 } 505 506 /* Fallback using vdda (default), nothing to do */ 507 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 508 priv->vdda_uv); 509 510 return 0; 511 } 512 513 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 514 { 515 if (priv->vdda_uv < 2700000) { 516 if (priv->syscfg && priv->vdd_uv > 2700000) { 517 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 518 STM32MP1_SYSCFG_ANASWVDD_MASK); 519 regulator_disable(priv->vdd); 520 return; 521 } 522 if (priv->booster) 523 regulator_disable(priv->booster); 524 } 525 } 526 527 static int stm32_adc_core_hw_start(struct device *dev) 528 { 529 struct stm32_adc_common *common = dev_get_drvdata(dev); 530 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 531 int ret; 532 533 ret = regulator_enable(priv->vdda); 534 if (ret < 0) { 535 dev_err(dev, "vdda enable failed %d\n", ret); 536 return ret; 537 } 538 539 ret = regulator_get_voltage(priv->vdda); 540 if (ret < 0) { 541 dev_err(dev, "vdda get voltage failed, %d\n", ret); 542 goto err_vdda_disable; 543 } 544 priv->vdda_uv = ret; 545 546 ret = stm32_adc_core_switches_supply_en(priv, dev); 547 if (ret < 0) 548 goto err_vdda_disable; 549 550 ret = regulator_enable(priv->vref); 551 if (ret < 0) { 552 dev_err(dev, "vref enable failed\n"); 553 goto err_switches_dis; 554 } 555 556 ret = clk_prepare_enable(priv->bclk); 557 if (ret < 0) { 558 dev_err(dev, "bus clk enable failed\n"); 559 goto err_regulator_disable; 560 } 561 562 ret = clk_prepare_enable(priv->aclk); 563 if (ret < 0) { 564 dev_err(dev, "adc clk enable failed\n"); 565 goto err_bclk_disable; 566 } 567 568 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 569 570 return 0; 571 572 err_bclk_disable: 573 clk_disable_unprepare(priv->bclk); 574 err_regulator_disable: 575 regulator_disable(priv->vref); 576 err_switches_dis: 577 stm32_adc_core_switches_supply_dis(priv); 578 err_vdda_disable: 579 regulator_disable(priv->vdda); 580 581 return ret; 582 } 583 584 static void stm32_adc_core_hw_stop(struct device *dev) 585 { 586 struct stm32_adc_common *common = dev_get_drvdata(dev); 587 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 588 589 /* Backup CCR that may be lost (depends on power state to achieve) */ 590 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 591 clk_disable_unprepare(priv->aclk); 592 clk_disable_unprepare(priv->bclk); 593 regulator_disable(priv->vref); 594 stm32_adc_core_switches_supply_dis(priv); 595 regulator_disable(priv->vdda); 596 } 597 598 static int stm32_adc_core_switches_probe(struct device *dev, 599 struct stm32_adc_priv *priv) 600 { 601 struct device_node *np = dev->of_node; 602 int ret; 603 604 /* Analog switches supply can be controlled by syscfg (optional) */ 605 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 606 if (IS_ERR(priv->syscfg)) { 607 ret = PTR_ERR(priv->syscfg); 608 if (ret != -ENODEV) 609 return dev_err_probe(dev, ret, "Can't probe syscfg\n"); 610 611 priv->syscfg = NULL; 612 } 613 614 /* Booster can be used to supply analog switches (optional) */ 615 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 616 of_property_read_bool(np, "booster-supply")) { 617 priv->booster = devm_regulator_get_optional(dev, "booster"); 618 if (IS_ERR(priv->booster)) { 619 ret = PTR_ERR(priv->booster); 620 if (ret != -ENODEV) 621 return dev_err_probe(dev, ret, "can't get booster\n"); 622 623 priv->booster = NULL; 624 } 625 } 626 627 /* Vdd can be used to supply analog switches (optional) */ 628 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 629 of_property_read_bool(np, "vdd-supply")) { 630 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 631 if (IS_ERR(priv->vdd)) { 632 ret = PTR_ERR(priv->vdd); 633 if (ret != -ENODEV) 634 return dev_err_probe(dev, ret, "can't get vdd\n"); 635 636 priv->vdd = NULL; 637 } 638 } 639 640 if (priv->vdd) { 641 ret = regulator_enable(priv->vdd); 642 if (ret < 0) { 643 dev_err(dev, "vdd enable failed %d\n", ret); 644 return ret; 645 } 646 647 ret = regulator_get_voltage(priv->vdd); 648 if (ret < 0) { 649 dev_err(dev, "vdd get voltage failed %d\n", ret); 650 regulator_disable(priv->vdd); 651 return ret; 652 } 653 priv->vdd_uv = ret; 654 655 regulator_disable(priv->vdd); 656 } 657 658 return 0; 659 } 660 661 static int stm32_adc_probe_identification(struct platform_device *pdev, 662 struct stm32_adc_priv *priv) 663 { 664 struct device_node *np = pdev->dev.of_node; 665 struct device_node *child; 666 const char *compat; 667 int ret, count = 0; 668 u32 id, val; 669 670 if (!priv->cfg->ipid) 671 return 0; 672 673 id = FIELD_GET(STM32MP1_IPIDR_MASK, 674 readl_relaxed(priv->common.base + STM32MP1_ADC_IPDR)); 675 if (id != priv->cfg->ipid) { 676 dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id); 677 return -EINVAL; 678 } 679 680 for_each_child_of_node(np, child) { 681 ret = of_property_read_string(child, "compatible", &compat); 682 if (ret) 683 continue; 684 /* Count child nodes with stm32 adc compatible */ 685 if (strstr(compat, "st,stm32") && strstr(compat, "adc")) 686 count++; 687 } 688 689 val = readl_relaxed(priv->common.base + STM32MP1_ADC_HWCFGR0); 690 priv->nb_adc_max = FIELD_GET(STM32MP1_ADCNUM_MASK, val); 691 if (count > priv->nb_adc_max) { 692 dev_err(&pdev->dev, "Unexpected child number: %d", count); 693 return -EINVAL; 694 } 695 696 val = readl_relaxed(priv->common.base + STM32MP1_ADC_VERR); 697 dev_dbg(&pdev->dev, "ADC version: %lu.%lu\n", 698 FIELD_GET(STM32MP1_MAJREV_MASK, val), 699 FIELD_GET(STM32MP1_MINREV_MASK, val)); 700 701 return 0; 702 } 703 704 static int stm32_adc_probe(struct platform_device *pdev) 705 { 706 struct stm32_adc_priv *priv; 707 struct device *dev = &pdev->dev; 708 struct device_node *np = pdev->dev.of_node; 709 struct resource *res; 710 u32 max_rate; 711 int ret; 712 713 if (!pdev->dev.of_node) 714 return -ENODEV; 715 716 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 717 if (!priv) 718 return -ENOMEM; 719 platform_set_drvdata(pdev, &priv->common); 720 721 priv->cfg = (const struct stm32_adc_priv_cfg *) 722 of_match_device(dev->driver->of_match_table, dev)->data; 723 priv->nb_adc_max = priv->cfg->num_adcs; 724 spin_lock_init(&priv->common.lock); 725 726 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 727 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 728 if (IS_ERR(priv->common.base)) 729 return PTR_ERR(priv->common.base); 730 priv->common.phys_base = res->start; 731 732 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 733 if (IS_ERR(priv->vdda)) 734 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), 735 "vdda get failed\n"); 736 737 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 738 if (IS_ERR(priv->vref)) 739 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), 740 "vref get failed\n"); 741 742 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); 743 if (IS_ERR(priv->aclk)) 744 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), 745 "Can't get 'adc' clock\n"); 746 747 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); 748 if (IS_ERR(priv->bclk)) 749 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), 750 "Can't get 'bus' clock\n"); 751 752 ret = stm32_adc_core_switches_probe(dev, priv); 753 if (ret) 754 return ret; 755 756 pm_runtime_get_noresume(dev); 757 pm_runtime_set_active(dev); 758 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 759 pm_runtime_use_autosuspend(dev); 760 pm_runtime_enable(dev); 761 762 ret = stm32_adc_core_hw_start(dev); 763 if (ret) 764 goto err_pm_stop; 765 766 ret = stm32_adc_probe_identification(pdev, priv); 767 if (ret < 0) 768 goto err_hw_stop; 769 770 ret = regulator_get_voltage(priv->vref); 771 if (ret < 0) { 772 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 773 goto err_hw_stop; 774 } 775 priv->common.vref_mv = ret / 1000; 776 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 777 778 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 779 &max_rate); 780 if (!ret) 781 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 782 else 783 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 784 785 ret = priv->cfg->clk_sel(pdev, priv); 786 if (ret < 0) 787 goto err_hw_stop; 788 789 ret = stm32_adc_irq_probe(pdev, priv); 790 if (ret < 0) 791 goto err_hw_stop; 792 793 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 794 if (ret < 0) { 795 dev_err(&pdev->dev, "failed to populate DT children\n"); 796 goto err_irq_remove; 797 } 798 799 pm_runtime_mark_last_busy(dev); 800 pm_runtime_put_autosuspend(dev); 801 802 return 0; 803 804 err_irq_remove: 805 stm32_adc_irq_remove(pdev, priv); 806 err_hw_stop: 807 stm32_adc_core_hw_stop(dev); 808 err_pm_stop: 809 pm_runtime_disable(dev); 810 pm_runtime_set_suspended(dev); 811 pm_runtime_put_noidle(dev); 812 813 return ret; 814 } 815 816 static int stm32_adc_remove(struct platform_device *pdev) 817 { 818 struct stm32_adc_common *common = platform_get_drvdata(pdev); 819 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 820 821 pm_runtime_get_sync(&pdev->dev); 822 of_platform_depopulate(&pdev->dev); 823 stm32_adc_irq_remove(pdev, priv); 824 stm32_adc_core_hw_stop(&pdev->dev); 825 pm_runtime_disable(&pdev->dev); 826 pm_runtime_set_suspended(&pdev->dev); 827 pm_runtime_put_noidle(&pdev->dev); 828 829 return 0; 830 } 831 832 static int stm32_adc_core_runtime_suspend(struct device *dev) 833 { 834 stm32_adc_core_hw_stop(dev); 835 836 return 0; 837 } 838 839 static int stm32_adc_core_runtime_resume(struct device *dev) 840 { 841 return stm32_adc_core_hw_start(dev); 842 } 843 844 static int stm32_adc_core_runtime_idle(struct device *dev) 845 { 846 pm_runtime_mark_last_busy(dev); 847 848 return 0; 849 } 850 851 static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops, 852 stm32_adc_core_runtime_suspend, 853 stm32_adc_core_runtime_resume, 854 stm32_adc_core_runtime_idle); 855 856 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 857 .regs = &stm32f4_adc_common_regs, 858 .clk_sel = stm32f4_adc_clk_sel, 859 .max_clk_rate_hz = 36000000, 860 .num_irqs = 1, 861 .num_adcs = 3, 862 }; 863 864 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 865 .regs = &stm32h7_adc_common_regs, 866 .clk_sel = stm32h7_adc_clk_sel, 867 .max_clk_rate_hz = 36000000, 868 .has_syscfg = HAS_VBOOSTER, 869 .num_irqs = 1, 870 .num_adcs = 2, 871 }; 872 873 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 874 .regs = &stm32h7_adc_common_regs, 875 .clk_sel = stm32h7_adc_clk_sel, 876 .max_clk_rate_hz = 36000000, 877 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 878 .ipid = STM32MP15_IPIDR_NUMBER, 879 .num_irqs = 2, 880 }; 881 882 static const struct stm32_adc_priv_cfg stm32mp13_adc_priv_cfg = { 883 .regs = &stm32mp13_adc_common_regs, 884 .clk_sel = stm32h7_adc_clk_sel, 885 .max_clk_rate_hz = 75 * HZ_PER_MHZ, 886 .ipid = STM32MP13_IPIDR_NUMBER, 887 .num_irqs = 1, 888 }; 889 890 static const struct of_device_id stm32_adc_of_match[] = { 891 { 892 .compatible = "st,stm32f4-adc-core", 893 .data = (void *)&stm32f4_adc_priv_cfg 894 }, { 895 .compatible = "st,stm32h7-adc-core", 896 .data = (void *)&stm32h7_adc_priv_cfg 897 }, { 898 .compatible = "st,stm32mp1-adc-core", 899 .data = (void *)&stm32mp1_adc_priv_cfg 900 }, { 901 .compatible = "st,stm32mp13-adc-core", 902 .data = (void *)&stm32mp13_adc_priv_cfg 903 }, { 904 }, 905 }; 906 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 907 908 static struct platform_driver stm32_adc_driver = { 909 .probe = stm32_adc_probe, 910 .remove = stm32_adc_remove, 911 .driver = { 912 .name = "stm32-adc-core", 913 .of_match_table = stm32_adc_of_match, 914 .pm = pm_ptr(&stm32_adc_core_pm_ops), 915 }, 916 }; 917 module_platform_driver(stm32_adc_driver); 918 919 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 920 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 921 MODULE_LICENSE("GPL v2"); 922 MODULE_ALIAS("platform:stm32-adc-core"); 923