1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdesc.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include "stm32-adc-core.h" 26 27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 28 29 /* SYSCFG registers */ 30 #define STM32MP1_SYSCFG_PMCSETR 0x04 31 #define STM32MP1_SYSCFG_PMCCLRR 0x44 32 33 /* SYSCFG bit fields */ 34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 35 36 /* SYSCFG capability flags */ 37 #define HAS_VBOOSTER BIT(0) 38 #define HAS_ANASWVDD BIT(1) 39 40 /** 41 * struct stm32_adc_common_regs - stm32 common registers 42 * @csr: common status register offset 43 * @ccr: common control register offset 44 * @eoc1_msk: adc1 end of conversion flag in @csr 45 * @eoc2_msk: adc2 end of conversion flag in @csr 46 * @eoc3_msk: adc3 end of conversion flag in @csr 47 * @ier: interrupt enable register offset for each adc 48 * @eocie_msk: end of conversion interrupt enable mask in @ier 49 */ 50 struct stm32_adc_common_regs { 51 u32 csr; 52 u32 ccr; 53 u32 eoc1_msk; 54 u32 eoc2_msk; 55 u32 eoc3_msk; 56 u32 ier; 57 u32 eocie_msk; 58 }; 59 60 struct stm32_adc_priv; 61 62 /** 63 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 64 * @regs: common registers for all instances 65 * @clk_sel: clock selection routine 66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 67 * @has_syscfg: SYSCFG capability flags 68 */ 69 struct stm32_adc_priv_cfg { 70 const struct stm32_adc_common_regs *regs; 71 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 72 u32 max_clk_rate_hz; 73 unsigned int has_syscfg; 74 }; 75 76 /** 77 * struct stm32_adc_priv - stm32 ADC core private data 78 * @irq: irq(s) for ADC block 79 * @domain: irq domain reference 80 * @aclk: clock reference for the analog circuitry 81 * @bclk: bus clock common for all ADCs, depends on part used 82 * @booster: booster supply reference 83 * @vdd: vdd supply reference 84 * @vdda: vdda analog supply reference 85 * @vref: regulator reference 86 * @vdd_uv: vdd supply voltage (microvolts) 87 * @vdda_uv: vdda supply voltage (microvolts) 88 * @cfg: compatible configuration data 89 * @common: common data for all ADC instances 90 * @ccr_bak: backup CCR in low power mode 91 * @syscfg: reference to syscon, system control registers 92 */ 93 struct stm32_adc_priv { 94 int irq[STM32_ADC_MAX_ADCS]; 95 struct irq_domain *domain; 96 struct clk *aclk; 97 struct clk *bclk; 98 struct regulator *booster; 99 struct regulator *vdd; 100 struct regulator *vdda; 101 struct regulator *vref; 102 int vdd_uv; 103 int vdda_uv; 104 const struct stm32_adc_priv_cfg *cfg; 105 struct stm32_adc_common common; 106 u32 ccr_bak; 107 struct regmap *syscfg; 108 }; 109 110 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 111 { 112 return container_of(com, struct stm32_adc_priv, common); 113 } 114 115 /* STM32F4 ADC internal common clock prescaler division ratios */ 116 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 117 118 /** 119 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 120 * @pdev: platform device 121 * @priv: stm32 ADC core private data 122 * Select clock prescaler used for analog conversions, before using ADC. 123 */ 124 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 125 struct stm32_adc_priv *priv) 126 { 127 unsigned long rate; 128 u32 val; 129 int i; 130 131 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 132 if (!priv->aclk) { 133 dev_err(&pdev->dev, "No 'adc' clock found\n"); 134 return -ENOENT; 135 } 136 137 rate = clk_get_rate(priv->aclk); 138 if (!rate) { 139 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 140 return -EINVAL; 141 } 142 143 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 144 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz) 145 break; 146 } 147 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 148 dev_err(&pdev->dev, "adc clk selection failed\n"); 149 return -EINVAL; 150 } 151 152 priv->common.rate = rate / stm32f4_pclk_div[i]; 153 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 154 val &= ~STM32F4_ADC_ADCPRE_MASK; 155 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 156 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 157 158 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 159 priv->common.rate / 1000); 160 161 return 0; 162 } 163 164 /** 165 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 166 * @ckmode: ADC clock mode, Async or sync with prescaler. 167 * @presc: prescaler bitfield for async clock mode 168 * @div: prescaler division ratio 169 */ 170 struct stm32h7_adc_ck_spec { 171 u32 ckmode; 172 u32 presc; 173 int div; 174 }; 175 176 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 177 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 178 { 0, 0, 1 }, 179 { 0, 1, 2 }, 180 { 0, 2, 4 }, 181 { 0, 3, 6 }, 182 { 0, 4, 8 }, 183 { 0, 5, 10 }, 184 { 0, 6, 12 }, 185 { 0, 7, 16 }, 186 { 0, 8, 32 }, 187 { 0, 9, 64 }, 188 { 0, 10, 128 }, 189 { 0, 11, 256 }, 190 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 191 { 1, 0, 1 }, 192 { 2, 0, 2 }, 193 { 3, 0, 4 }, 194 }; 195 196 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 197 struct stm32_adc_priv *priv) 198 { 199 u32 ckmode, presc, val; 200 unsigned long rate; 201 int i, div; 202 203 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 204 if (!priv->bclk) { 205 dev_err(&pdev->dev, "No 'bus' clock found\n"); 206 return -ENOENT; 207 } 208 209 /* 210 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 211 * So, choice is to have bus clock mandatory and adc clock optional. 212 * If optional 'adc' clock has been found, then try to use it first. 213 */ 214 if (priv->aclk) { 215 /* 216 * Asynchronous clock modes (e.g. ckmode == 0) 217 * From spec: PLL output musn't exceed max rate 218 */ 219 rate = clk_get_rate(priv->aclk); 220 if (!rate) { 221 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 222 return -EINVAL; 223 } 224 225 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 226 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 227 presc = stm32h7_adc_ckmodes_spec[i].presc; 228 div = stm32h7_adc_ckmodes_spec[i].div; 229 230 if (ckmode) 231 continue; 232 233 if ((rate / div) <= priv->cfg->max_clk_rate_hz) 234 goto out; 235 } 236 } 237 238 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 239 rate = clk_get_rate(priv->bclk); 240 if (!rate) { 241 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 242 return -EINVAL; 243 } 244 245 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 246 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 247 presc = stm32h7_adc_ckmodes_spec[i].presc; 248 div = stm32h7_adc_ckmodes_spec[i].div; 249 250 if (!ckmode) 251 continue; 252 253 if ((rate / div) <= priv->cfg->max_clk_rate_hz) 254 goto out; 255 } 256 257 dev_err(&pdev->dev, "adc clk selection failed\n"); 258 return -EINVAL; 259 260 out: 261 /* rate used later by each ADC instance to control BOOST mode */ 262 priv->common.rate = rate / div; 263 264 /* Set common clock mode and prescaler */ 265 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 266 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 267 val |= ckmode << STM32H7_CKMODE_SHIFT; 268 val |= presc << STM32H7_PRESC_SHIFT; 269 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 270 271 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 272 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 273 274 return 0; 275 } 276 277 /* STM32F4 common registers definitions */ 278 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 279 .csr = STM32F4_ADC_CSR, 280 .ccr = STM32F4_ADC_CCR, 281 .eoc1_msk = STM32F4_EOC1, 282 .eoc2_msk = STM32F4_EOC2, 283 .eoc3_msk = STM32F4_EOC3, 284 .ier = STM32F4_ADC_CR1, 285 .eocie_msk = STM32F4_EOCIE, 286 }; 287 288 /* STM32H7 common registers definitions */ 289 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 290 .csr = STM32H7_ADC_CSR, 291 .ccr = STM32H7_ADC_CCR, 292 .eoc1_msk = STM32H7_EOC_MST, 293 .eoc2_msk = STM32H7_EOC_SLV, 294 .ier = STM32H7_ADC_IER, 295 .eocie_msk = STM32H7_EOCIE, 296 }; 297 298 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 299 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 300 }; 301 302 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 303 unsigned int adc) 304 { 305 u32 ier, offset = stm32_adc_offset[adc]; 306 307 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 308 309 return ier & priv->cfg->regs->eocie_msk; 310 } 311 312 /* ADC common interrupt for all instances */ 313 static void stm32_adc_irq_handler(struct irq_desc *desc) 314 { 315 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 316 struct irq_chip *chip = irq_desc_get_chip(desc); 317 u32 status; 318 319 chained_irq_enter(chip, desc); 320 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 321 322 /* 323 * End of conversion may be handled by using IRQ or DMA. There may be a 324 * race here when two conversions complete at the same time on several 325 * ADCs. EOC may be read 'set' for several ADCs, with: 326 * - an ADC configured to use DMA (EOC triggers the DMA request, and 327 * is then automatically cleared by DR read in hardware) 328 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 329 * be called in this case) 330 * So both EOC status bit in CSR and EOCIE control bit must be checked 331 * before invoking the interrupt handler (e.g. call ISR only for 332 * IRQ-enabled ADCs). 333 */ 334 if (status & priv->cfg->regs->eoc1_msk && 335 stm32_adc_eoc_enabled(priv, 0)) 336 generic_handle_irq(irq_find_mapping(priv->domain, 0)); 337 338 if (status & priv->cfg->regs->eoc2_msk && 339 stm32_adc_eoc_enabled(priv, 1)) 340 generic_handle_irq(irq_find_mapping(priv->domain, 1)); 341 342 if (status & priv->cfg->regs->eoc3_msk && 343 stm32_adc_eoc_enabled(priv, 2)) 344 generic_handle_irq(irq_find_mapping(priv->domain, 2)); 345 346 chained_irq_exit(chip, desc); 347 }; 348 349 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 350 irq_hw_number_t hwirq) 351 { 352 irq_set_chip_data(irq, d->host_data); 353 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 354 355 return 0; 356 } 357 358 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 359 { 360 irq_set_chip_and_handler(irq, NULL, NULL); 361 irq_set_chip_data(irq, NULL); 362 } 363 364 static const struct irq_domain_ops stm32_adc_domain_ops = { 365 .map = stm32_adc_domain_map, 366 .unmap = stm32_adc_domain_unmap, 367 .xlate = irq_domain_xlate_onecell, 368 }; 369 370 static int stm32_adc_irq_probe(struct platform_device *pdev, 371 struct stm32_adc_priv *priv) 372 { 373 struct device_node *np = pdev->dev.of_node; 374 unsigned int i; 375 376 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 377 priv->irq[i] = platform_get_irq(pdev, i); 378 if (priv->irq[i] < 0) { 379 /* 380 * At least one interrupt must be provided, make others 381 * optional: 382 * - stm32f4/h7 shares a common interrupt. 383 * - stm32mp1, has one line per ADC (either for ADC1, 384 * ADC2 or both). 385 */ 386 if (i && priv->irq[i] == -ENXIO) 387 continue; 388 389 return priv->irq[i]; 390 } 391 } 392 393 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 394 &stm32_adc_domain_ops, 395 priv); 396 if (!priv->domain) { 397 dev_err(&pdev->dev, "Failed to add irq domain\n"); 398 return -ENOMEM; 399 } 400 401 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 402 if (priv->irq[i] < 0) 403 continue; 404 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 405 irq_set_handler_data(priv->irq[i], priv); 406 } 407 408 return 0; 409 } 410 411 static void stm32_adc_irq_remove(struct platform_device *pdev, 412 struct stm32_adc_priv *priv) 413 { 414 int hwirq; 415 unsigned int i; 416 417 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 418 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 419 irq_domain_remove(priv->domain); 420 421 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 422 if (priv->irq[i] < 0) 423 continue; 424 irq_set_chained_handler(priv->irq[i], NULL); 425 } 426 } 427 428 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 429 struct device *dev) 430 { 431 int ret; 432 433 /* 434 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 435 * switches (via PCSEL) which have reduced performances when their 436 * supply is below 2.7V (vdda by default): 437 * - Voltage booster can be used, to get full ADC performances 438 * (increases power consumption). 439 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 440 * 441 * Recommended settings for ANASWVDD and EN_BOOSTER: 442 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 443 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 444 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 445 */ 446 if (priv->vdda_uv < 2700000) { 447 if (priv->syscfg && priv->vdd_uv > 2700000) { 448 ret = regulator_enable(priv->vdd); 449 if (ret < 0) { 450 dev_err(dev, "vdd enable failed %d\n", ret); 451 return ret; 452 } 453 454 ret = regmap_write(priv->syscfg, 455 STM32MP1_SYSCFG_PMCSETR, 456 STM32MP1_SYSCFG_ANASWVDD_MASK); 457 if (ret < 0) { 458 regulator_disable(priv->vdd); 459 dev_err(dev, "vdd select failed, %d\n", ret); 460 return ret; 461 } 462 dev_dbg(dev, "analog switches supplied by vdd\n"); 463 464 return 0; 465 } 466 467 if (priv->booster) { 468 /* 469 * This is optional, as this is a trade-off between 470 * analog performance and power consumption. 471 */ 472 ret = regulator_enable(priv->booster); 473 if (ret < 0) { 474 dev_err(dev, "booster enable failed %d\n", ret); 475 return ret; 476 } 477 dev_dbg(dev, "analog switches supplied by booster\n"); 478 479 return 0; 480 } 481 } 482 483 /* Fallback using vdda (default), nothing to do */ 484 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 485 priv->vdda_uv); 486 487 return 0; 488 } 489 490 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 491 { 492 if (priv->vdda_uv < 2700000) { 493 if (priv->syscfg && priv->vdd_uv > 2700000) { 494 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 495 STM32MP1_SYSCFG_ANASWVDD_MASK); 496 regulator_disable(priv->vdd); 497 return; 498 } 499 if (priv->booster) 500 regulator_disable(priv->booster); 501 } 502 } 503 504 static int stm32_adc_core_hw_start(struct device *dev) 505 { 506 struct stm32_adc_common *common = dev_get_drvdata(dev); 507 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 508 int ret; 509 510 ret = regulator_enable(priv->vdda); 511 if (ret < 0) { 512 dev_err(dev, "vdda enable failed %d\n", ret); 513 return ret; 514 } 515 516 ret = regulator_get_voltage(priv->vdda); 517 if (ret < 0) { 518 dev_err(dev, "vdda get voltage failed, %d\n", ret); 519 goto err_vdda_disable; 520 } 521 priv->vdda_uv = ret; 522 523 ret = stm32_adc_core_switches_supply_en(priv, dev); 524 if (ret < 0) 525 goto err_vdda_disable; 526 527 ret = regulator_enable(priv->vref); 528 if (ret < 0) { 529 dev_err(dev, "vref enable failed\n"); 530 goto err_switches_dis; 531 } 532 533 if (priv->bclk) { 534 ret = clk_prepare_enable(priv->bclk); 535 if (ret < 0) { 536 dev_err(dev, "bus clk enable failed\n"); 537 goto err_regulator_disable; 538 } 539 } 540 541 if (priv->aclk) { 542 ret = clk_prepare_enable(priv->aclk); 543 if (ret < 0) { 544 dev_err(dev, "adc clk enable failed\n"); 545 goto err_bclk_disable; 546 } 547 } 548 549 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 550 551 return 0; 552 553 err_bclk_disable: 554 if (priv->bclk) 555 clk_disable_unprepare(priv->bclk); 556 err_regulator_disable: 557 regulator_disable(priv->vref); 558 err_switches_dis: 559 stm32_adc_core_switches_supply_dis(priv); 560 err_vdda_disable: 561 regulator_disable(priv->vdda); 562 563 return ret; 564 } 565 566 static void stm32_adc_core_hw_stop(struct device *dev) 567 { 568 struct stm32_adc_common *common = dev_get_drvdata(dev); 569 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 570 571 /* Backup CCR that may be lost (depends on power state to achieve) */ 572 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 573 if (priv->aclk) 574 clk_disable_unprepare(priv->aclk); 575 if (priv->bclk) 576 clk_disable_unprepare(priv->bclk); 577 regulator_disable(priv->vref); 578 stm32_adc_core_switches_supply_dis(priv); 579 regulator_disable(priv->vdda); 580 } 581 582 static int stm32_adc_core_switches_probe(struct device *dev, 583 struct stm32_adc_priv *priv) 584 { 585 struct device_node *np = dev->of_node; 586 int ret; 587 588 /* Analog switches supply can be controlled by syscfg (optional) */ 589 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 590 if (IS_ERR(priv->syscfg)) { 591 ret = PTR_ERR(priv->syscfg); 592 if (ret != -ENODEV) { 593 if (ret != -EPROBE_DEFER) 594 dev_err(dev, "Can't probe syscfg: %d\n", ret); 595 return ret; 596 } 597 priv->syscfg = NULL; 598 } 599 600 /* Booster can be used to supply analog switches (optional) */ 601 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 602 of_property_read_bool(np, "booster-supply")) { 603 priv->booster = devm_regulator_get_optional(dev, "booster"); 604 if (IS_ERR(priv->booster)) { 605 ret = PTR_ERR(priv->booster); 606 if (ret != -ENODEV) { 607 if (ret != -EPROBE_DEFER) 608 dev_err(dev, "can't get booster %d\n", 609 ret); 610 return ret; 611 } 612 priv->booster = NULL; 613 } 614 } 615 616 /* Vdd can be used to supply analog switches (optional) */ 617 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 618 of_property_read_bool(np, "vdd-supply")) { 619 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 620 if (IS_ERR(priv->vdd)) { 621 ret = PTR_ERR(priv->vdd); 622 if (ret != -ENODEV) { 623 if (ret != -EPROBE_DEFER) 624 dev_err(dev, "can't get vdd %d\n", ret); 625 return ret; 626 } 627 priv->vdd = NULL; 628 } 629 } 630 631 if (priv->vdd) { 632 ret = regulator_enable(priv->vdd); 633 if (ret < 0) { 634 dev_err(dev, "vdd enable failed %d\n", ret); 635 return ret; 636 } 637 638 ret = regulator_get_voltage(priv->vdd); 639 if (ret < 0) { 640 dev_err(dev, "vdd get voltage failed %d\n", ret); 641 regulator_disable(priv->vdd); 642 return ret; 643 } 644 priv->vdd_uv = ret; 645 646 regulator_disable(priv->vdd); 647 } 648 649 return 0; 650 } 651 652 static int stm32_adc_probe(struct platform_device *pdev) 653 { 654 struct stm32_adc_priv *priv; 655 struct device *dev = &pdev->dev; 656 struct device_node *np = pdev->dev.of_node; 657 struct resource *res; 658 int ret; 659 660 if (!pdev->dev.of_node) 661 return -ENODEV; 662 663 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 664 if (!priv) 665 return -ENOMEM; 666 platform_set_drvdata(pdev, &priv->common); 667 668 priv->cfg = (const struct stm32_adc_priv_cfg *) 669 of_match_device(dev->driver->of_match_table, dev)->data; 670 671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 672 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 673 if (IS_ERR(priv->common.base)) 674 return PTR_ERR(priv->common.base); 675 priv->common.phys_base = res->start; 676 677 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 678 if (IS_ERR(priv->vdda)) { 679 ret = PTR_ERR(priv->vdda); 680 if (ret != -EPROBE_DEFER) 681 dev_err(&pdev->dev, "vdda get failed, %d\n", ret); 682 return ret; 683 } 684 685 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 686 if (IS_ERR(priv->vref)) { 687 ret = PTR_ERR(priv->vref); 688 dev_err(&pdev->dev, "vref get failed, %d\n", ret); 689 return ret; 690 } 691 692 priv->aclk = devm_clk_get(&pdev->dev, "adc"); 693 if (IS_ERR(priv->aclk)) { 694 ret = PTR_ERR(priv->aclk); 695 if (ret != -ENOENT) { 696 dev_err(&pdev->dev, "Can't get 'adc' clock\n"); 697 return ret; 698 } 699 priv->aclk = NULL; 700 } 701 702 priv->bclk = devm_clk_get(&pdev->dev, "bus"); 703 if (IS_ERR(priv->bclk)) { 704 ret = PTR_ERR(priv->bclk); 705 if (ret != -ENOENT) { 706 dev_err(&pdev->dev, "Can't get 'bus' clock\n"); 707 return ret; 708 } 709 priv->bclk = NULL; 710 } 711 712 ret = stm32_adc_core_switches_probe(dev, priv); 713 if (ret) 714 return ret; 715 716 pm_runtime_get_noresume(dev); 717 pm_runtime_set_active(dev); 718 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 719 pm_runtime_use_autosuspend(dev); 720 pm_runtime_enable(dev); 721 722 ret = stm32_adc_core_hw_start(dev); 723 if (ret) 724 goto err_pm_stop; 725 726 ret = regulator_get_voltage(priv->vref); 727 if (ret < 0) { 728 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 729 goto err_hw_stop; 730 } 731 priv->common.vref_mv = ret / 1000; 732 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 733 734 ret = priv->cfg->clk_sel(pdev, priv); 735 if (ret < 0) 736 goto err_hw_stop; 737 738 ret = stm32_adc_irq_probe(pdev, priv); 739 if (ret < 0) 740 goto err_hw_stop; 741 742 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 743 if (ret < 0) { 744 dev_err(&pdev->dev, "failed to populate DT children\n"); 745 goto err_irq_remove; 746 } 747 748 pm_runtime_mark_last_busy(dev); 749 pm_runtime_put_autosuspend(dev); 750 751 return 0; 752 753 err_irq_remove: 754 stm32_adc_irq_remove(pdev, priv); 755 err_hw_stop: 756 stm32_adc_core_hw_stop(dev); 757 err_pm_stop: 758 pm_runtime_disable(dev); 759 pm_runtime_set_suspended(dev); 760 pm_runtime_put_noidle(dev); 761 762 return ret; 763 } 764 765 static int stm32_adc_remove(struct platform_device *pdev) 766 { 767 struct stm32_adc_common *common = platform_get_drvdata(pdev); 768 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 769 770 pm_runtime_get_sync(&pdev->dev); 771 of_platform_depopulate(&pdev->dev); 772 stm32_adc_irq_remove(pdev, priv); 773 stm32_adc_core_hw_stop(&pdev->dev); 774 pm_runtime_disable(&pdev->dev); 775 pm_runtime_set_suspended(&pdev->dev); 776 pm_runtime_put_noidle(&pdev->dev); 777 778 return 0; 779 } 780 781 #if defined(CONFIG_PM) 782 static int stm32_adc_core_runtime_suspend(struct device *dev) 783 { 784 stm32_adc_core_hw_stop(dev); 785 786 return 0; 787 } 788 789 static int stm32_adc_core_runtime_resume(struct device *dev) 790 { 791 return stm32_adc_core_hw_start(dev); 792 } 793 #endif 794 795 static const struct dev_pm_ops stm32_adc_core_pm_ops = { 796 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 797 pm_runtime_force_resume) 798 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend, 799 stm32_adc_core_runtime_resume, 800 NULL) 801 }; 802 803 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 804 .regs = &stm32f4_adc_common_regs, 805 .clk_sel = stm32f4_adc_clk_sel, 806 .max_clk_rate_hz = 36000000, 807 }; 808 809 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 810 .regs = &stm32h7_adc_common_regs, 811 .clk_sel = stm32h7_adc_clk_sel, 812 .max_clk_rate_hz = 36000000, 813 .has_syscfg = HAS_VBOOSTER, 814 }; 815 816 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 817 .regs = &stm32h7_adc_common_regs, 818 .clk_sel = stm32h7_adc_clk_sel, 819 .max_clk_rate_hz = 40000000, 820 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 821 }; 822 823 static const struct of_device_id stm32_adc_of_match[] = { 824 { 825 .compatible = "st,stm32f4-adc-core", 826 .data = (void *)&stm32f4_adc_priv_cfg 827 }, { 828 .compatible = "st,stm32h7-adc-core", 829 .data = (void *)&stm32h7_adc_priv_cfg 830 }, { 831 .compatible = "st,stm32mp1-adc-core", 832 .data = (void *)&stm32mp1_adc_priv_cfg 833 }, { 834 }, 835 }; 836 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 837 838 static struct platform_driver stm32_adc_driver = { 839 .probe = stm32_adc_probe, 840 .remove = stm32_adc_remove, 841 .driver = { 842 .name = "stm32-adc-core", 843 .of_match_table = stm32_adc_of_match, 844 .pm = &stm32_adc_core_pm_ops, 845 }, 846 }; 847 module_platform_driver(stm32_adc_driver); 848 849 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 850 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 851 MODULE_LICENSE("GPL v2"); 852 MODULE_ALIAS("platform:stm32-adc-core"); 853