1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdesc.h> 17 #include <linux/irqdomain.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/of_device.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/slab.h> 27 #include <linux/units.h> 28 29 #include "stm32-adc-core.h" 30 31 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 32 33 /* SYSCFG registers */ 34 #define STM32MP1_SYSCFG_PMCSETR 0x04 35 #define STM32MP1_SYSCFG_PMCCLRR 0x44 36 37 /* SYSCFG bit fields */ 38 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 39 40 /* SYSCFG capability flags */ 41 #define HAS_VBOOSTER BIT(0) 42 #define HAS_ANASWVDD BIT(1) 43 44 /** 45 * struct stm32_adc_common_regs - stm32 common registers 46 * @csr: common status register offset 47 * @ccr: common control register offset 48 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n 49 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n 50 * @ier: interrupt enable register offset for each adc 51 * @eocie_msk: end of conversion interrupt enable mask in @ier 52 */ 53 struct stm32_adc_common_regs { 54 u32 csr; 55 u32 ccr; 56 u32 eoc_msk[STM32_ADC_MAX_ADCS]; 57 u32 ovr_msk[STM32_ADC_MAX_ADCS]; 58 u32 ier; 59 u32 eocie_msk; 60 }; 61 62 struct stm32_adc_priv; 63 64 /** 65 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 66 * @regs: common registers for all instances 67 * @clk_sel: clock selection routine 68 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 69 * @ipid: adc identification number 70 * @has_syscfg: SYSCFG capability flags 71 * @num_irqs: number of interrupt lines 72 * @num_adcs: maximum number of ADC instances in the common registers 73 */ 74 struct stm32_adc_priv_cfg { 75 const struct stm32_adc_common_regs *regs; 76 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 77 u32 max_clk_rate_hz; 78 u32 ipid; 79 unsigned int has_syscfg; 80 unsigned int num_irqs; 81 unsigned int num_adcs; 82 }; 83 84 /** 85 * struct stm32_adc_priv - stm32 ADC core private data 86 * @irq: irq(s) for ADC block 87 * @nb_adc_max: actual maximum number of instance per ADC block 88 * @domain: irq domain reference 89 * @aclk: clock reference for the analog circuitry 90 * @bclk: bus clock common for all ADCs, depends on part used 91 * @max_clk_rate: desired maximum clock rate 92 * @booster: booster supply reference 93 * @vdd: vdd supply reference 94 * @vdda: vdda analog supply reference 95 * @vref: regulator reference 96 * @vdd_uv: vdd supply voltage (microvolts) 97 * @vdda_uv: vdda supply voltage (microvolts) 98 * @cfg: compatible configuration data 99 * @common: common data for all ADC instances 100 * @ccr_bak: backup CCR in low power mode 101 * @syscfg: reference to syscon, system control registers 102 */ 103 struct stm32_adc_priv { 104 int irq[STM32_ADC_MAX_ADCS]; 105 unsigned int nb_adc_max; 106 struct irq_domain *domain; 107 struct clk *aclk; 108 struct clk *bclk; 109 u32 max_clk_rate; 110 struct regulator *booster; 111 struct regulator *vdd; 112 struct regulator *vdda; 113 struct regulator *vref; 114 int vdd_uv; 115 int vdda_uv; 116 const struct stm32_adc_priv_cfg *cfg; 117 struct stm32_adc_common common; 118 u32 ccr_bak; 119 struct regmap *syscfg; 120 }; 121 122 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 123 { 124 return container_of(com, struct stm32_adc_priv, common); 125 } 126 127 /* STM32F4 ADC internal common clock prescaler division ratios */ 128 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 129 130 /** 131 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 132 * @pdev: platform device 133 * @priv: stm32 ADC core private data 134 * Select clock prescaler used for analog conversions, before using ADC. 135 */ 136 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 137 struct stm32_adc_priv *priv) 138 { 139 unsigned long rate; 140 u32 val; 141 int i; 142 143 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 144 if (!priv->aclk) { 145 dev_err(&pdev->dev, "No 'adc' clock found\n"); 146 return -ENOENT; 147 } 148 149 rate = clk_get_rate(priv->aclk); 150 if (!rate) { 151 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 152 return -EINVAL; 153 } 154 155 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 156 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 157 break; 158 } 159 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 160 dev_err(&pdev->dev, "adc clk selection failed\n"); 161 return -EINVAL; 162 } 163 164 priv->common.rate = rate / stm32f4_pclk_div[i]; 165 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 166 val &= ~STM32F4_ADC_ADCPRE_MASK; 167 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 168 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 169 170 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 171 priv->common.rate / 1000); 172 173 return 0; 174 } 175 176 /** 177 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 178 * @ckmode: ADC clock mode, Async or sync with prescaler. 179 * @presc: prescaler bitfield for async clock mode 180 * @div: prescaler division ratio 181 */ 182 struct stm32h7_adc_ck_spec { 183 u32 ckmode; 184 u32 presc; 185 int div; 186 }; 187 188 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 189 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 190 { 0, 0, 1 }, 191 { 0, 1, 2 }, 192 { 0, 2, 4 }, 193 { 0, 3, 6 }, 194 { 0, 4, 8 }, 195 { 0, 5, 10 }, 196 { 0, 6, 12 }, 197 { 0, 7, 16 }, 198 { 0, 8, 32 }, 199 { 0, 9, 64 }, 200 { 0, 10, 128 }, 201 { 0, 11, 256 }, 202 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 203 { 1, 0, 1 }, 204 { 2, 0, 2 }, 205 { 3, 0, 4 }, 206 }; 207 208 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 209 struct stm32_adc_priv *priv) 210 { 211 u32 ckmode, presc, val; 212 unsigned long rate; 213 int i, div, duty; 214 215 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 216 if (!priv->bclk) { 217 dev_err(&pdev->dev, "No 'bus' clock found\n"); 218 return -ENOENT; 219 } 220 221 /* 222 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 223 * So, choice is to have bus clock mandatory and adc clock optional. 224 * If optional 'adc' clock has been found, then try to use it first. 225 */ 226 if (priv->aclk) { 227 /* 228 * Asynchronous clock modes (e.g. ckmode == 0) 229 * From spec: PLL output musn't exceed max rate 230 */ 231 rate = clk_get_rate(priv->aclk); 232 if (!rate) { 233 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 234 return -EINVAL; 235 } 236 237 /* If duty is an error, kindly use at least /2 divider */ 238 duty = clk_get_scaled_duty_cycle(priv->aclk, 100); 239 if (duty < 0) 240 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty); 241 242 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 243 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 244 presc = stm32h7_adc_ckmodes_spec[i].presc; 245 div = stm32h7_adc_ckmodes_spec[i].div; 246 247 if (ckmode) 248 continue; 249 250 /* 251 * For proper operation, clock duty cycle range is 49% 252 * to 51%. Apply at least /2 prescaler otherwise. 253 */ 254 if (div == 1 && (duty < 49 || duty > 51)) 255 continue; 256 257 if ((rate / div) <= priv->max_clk_rate) 258 goto out; 259 } 260 } 261 262 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 263 rate = clk_get_rate(priv->bclk); 264 if (!rate) { 265 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 266 return -EINVAL; 267 } 268 269 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); 270 if (duty < 0) 271 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty); 272 273 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 274 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 275 presc = stm32h7_adc_ckmodes_spec[i].presc; 276 div = stm32h7_adc_ckmodes_spec[i].div; 277 278 if (!ckmode) 279 continue; 280 281 if (div == 1 && (duty < 49 || duty > 51)) 282 continue; 283 284 if ((rate / div) <= priv->max_clk_rate) 285 goto out; 286 } 287 288 dev_err(&pdev->dev, "adc clk selection failed\n"); 289 return -EINVAL; 290 291 out: 292 /* rate used later by each ADC instance to control BOOST mode */ 293 priv->common.rate = rate / div; 294 295 /* Set common clock mode and prescaler */ 296 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 297 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 298 val |= ckmode << STM32H7_CKMODE_SHIFT; 299 val |= presc << STM32H7_PRESC_SHIFT; 300 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 301 302 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 303 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 304 305 return 0; 306 } 307 308 /* STM32F4 common registers definitions */ 309 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 310 .csr = STM32F4_ADC_CSR, 311 .ccr = STM32F4_ADC_CCR, 312 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3 }, 313 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3 }, 314 .ier = STM32F4_ADC_CR1, 315 .eocie_msk = STM32F4_EOCIE, 316 }; 317 318 /* STM32H7 common registers definitions */ 319 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 320 .csr = STM32H7_ADC_CSR, 321 .ccr = STM32H7_ADC_CCR, 322 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV }, 323 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV }, 324 .ier = STM32H7_ADC_IER, 325 .eocie_msk = STM32H7_EOCIE, 326 }; 327 328 /* STM32MP13 common registers definitions */ 329 static const struct stm32_adc_common_regs stm32mp13_adc_common_regs = { 330 .csr = STM32H7_ADC_CSR, 331 .ccr = STM32H7_ADC_CCR, 332 .eoc_msk = { STM32H7_EOC_MST }, 333 .ovr_msk = { STM32H7_OVR_MST }, 334 .ier = STM32H7_ADC_IER, 335 .eocie_msk = STM32H7_EOCIE, 336 }; 337 338 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 339 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 340 }; 341 342 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 343 unsigned int adc) 344 { 345 u32 ier, offset = stm32_adc_offset[adc]; 346 347 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 348 349 return ier & priv->cfg->regs->eocie_msk; 350 } 351 352 /* ADC common interrupt for all instances */ 353 static void stm32_adc_irq_handler(struct irq_desc *desc) 354 { 355 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 356 struct irq_chip *chip = irq_desc_get_chip(desc); 357 int i; 358 u32 status; 359 360 chained_irq_enter(chip, desc); 361 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 362 363 /* 364 * End of conversion may be handled by using IRQ or DMA. There may be a 365 * race here when two conversions complete at the same time on several 366 * ADCs. EOC may be read 'set' for several ADCs, with: 367 * - an ADC configured to use DMA (EOC triggers the DMA request, and 368 * is then automatically cleared by DR read in hardware) 369 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 370 * be called in this case) 371 * So both EOC status bit in CSR and EOCIE control bit must be checked 372 * before invoking the interrupt handler (e.g. call ISR only for 373 * IRQ-enabled ADCs). 374 */ 375 for (i = 0; i < priv->nb_adc_max; i++) { 376 if ((status & priv->cfg->regs->eoc_msk[i] && 377 stm32_adc_eoc_enabled(priv, i)) || 378 (status & priv->cfg->regs->ovr_msk[i])) 379 generic_handle_domain_irq(priv->domain, i); 380 } 381 382 chained_irq_exit(chip, desc); 383 }; 384 385 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 386 irq_hw_number_t hwirq) 387 { 388 irq_set_chip_data(irq, d->host_data); 389 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 390 391 return 0; 392 } 393 394 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 395 { 396 irq_set_chip_and_handler(irq, NULL, NULL); 397 irq_set_chip_data(irq, NULL); 398 } 399 400 static const struct irq_domain_ops stm32_adc_domain_ops = { 401 .map = stm32_adc_domain_map, 402 .unmap = stm32_adc_domain_unmap, 403 .xlate = irq_domain_xlate_onecell, 404 }; 405 406 static int stm32_adc_irq_probe(struct platform_device *pdev, 407 struct stm32_adc_priv *priv) 408 { 409 struct device_node *np = pdev->dev.of_node; 410 unsigned int i; 411 412 /* 413 * Interrupt(s) must be provided, depending on the compatible: 414 * - stm32f4/h7 shares a common interrupt line. 415 * - stm32mp1, has one line per ADC 416 */ 417 for (i = 0; i < priv->cfg->num_irqs; i++) { 418 priv->irq[i] = platform_get_irq(pdev, i); 419 if (priv->irq[i] < 0) 420 return priv->irq[i]; 421 } 422 423 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 424 &stm32_adc_domain_ops, 425 priv); 426 if (!priv->domain) { 427 dev_err(&pdev->dev, "Failed to add irq domain\n"); 428 return -ENOMEM; 429 } 430 431 for (i = 0; i < priv->cfg->num_irqs; i++) { 432 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 433 irq_set_handler_data(priv->irq[i], priv); 434 } 435 436 return 0; 437 } 438 439 static void stm32_adc_irq_remove(struct platform_device *pdev, 440 struct stm32_adc_priv *priv) 441 { 442 int hwirq; 443 unsigned int i; 444 445 for (hwirq = 0; hwirq < priv->nb_adc_max; hwirq++) 446 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 447 irq_domain_remove(priv->domain); 448 449 for (i = 0; i < priv->cfg->num_irqs; i++) 450 irq_set_chained_handler(priv->irq[i], NULL); 451 } 452 453 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 454 struct device *dev) 455 { 456 int ret; 457 458 /* 459 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 460 * switches (via PCSEL) which have reduced performances when their 461 * supply is below 2.7V (vdda by default): 462 * - Voltage booster can be used, to get full ADC performances 463 * (increases power consumption). 464 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 465 * 466 * Recommended settings for ANASWVDD and EN_BOOSTER: 467 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 468 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 469 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 470 */ 471 if (priv->vdda_uv < 2700000) { 472 if (priv->syscfg && priv->vdd_uv > 2700000) { 473 ret = regulator_enable(priv->vdd); 474 if (ret < 0) { 475 dev_err(dev, "vdd enable failed %d\n", ret); 476 return ret; 477 } 478 479 ret = regmap_write(priv->syscfg, 480 STM32MP1_SYSCFG_PMCSETR, 481 STM32MP1_SYSCFG_ANASWVDD_MASK); 482 if (ret < 0) { 483 regulator_disable(priv->vdd); 484 dev_err(dev, "vdd select failed, %d\n", ret); 485 return ret; 486 } 487 dev_dbg(dev, "analog switches supplied by vdd\n"); 488 489 return 0; 490 } 491 492 if (priv->booster) { 493 /* 494 * This is optional, as this is a trade-off between 495 * analog performance and power consumption. 496 */ 497 ret = regulator_enable(priv->booster); 498 if (ret < 0) { 499 dev_err(dev, "booster enable failed %d\n", ret); 500 return ret; 501 } 502 dev_dbg(dev, "analog switches supplied by booster\n"); 503 504 return 0; 505 } 506 } 507 508 /* Fallback using vdda (default), nothing to do */ 509 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 510 priv->vdda_uv); 511 512 return 0; 513 } 514 515 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 516 { 517 if (priv->vdda_uv < 2700000) { 518 if (priv->syscfg && priv->vdd_uv > 2700000) { 519 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 520 STM32MP1_SYSCFG_ANASWVDD_MASK); 521 regulator_disable(priv->vdd); 522 return; 523 } 524 if (priv->booster) 525 regulator_disable(priv->booster); 526 } 527 } 528 529 static int stm32_adc_core_hw_start(struct device *dev) 530 { 531 struct stm32_adc_common *common = dev_get_drvdata(dev); 532 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 533 int ret; 534 535 ret = regulator_enable(priv->vdda); 536 if (ret < 0) { 537 dev_err(dev, "vdda enable failed %d\n", ret); 538 return ret; 539 } 540 541 ret = regulator_get_voltage(priv->vdda); 542 if (ret < 0) { 543 dev_err(dev, "vdda get voltage failed, %d\n", ret); 544 goto err_vdda_disable; 545 } 546 priv->vdda_uv = ret; 547 548 ret = stm32_adc_core_switches_supply_en(priv, dev); 549 if (ret < 0) 550 goto err_vdda_disable; 551 552 ret = regulator_enable(priv->vref); 553 if (ret < 0) { 554 dev_err(dev, "vref enable failed\n"); 555 goto err_switches_dis; 556 } 557 558 ret = clk_prepare_enable(priv->bclk); 559 if (ret < 0) { 560 dev_err(dev, "bus clk enable failed\n"); 561 goto err_regulator_disable; 562 } 563 564 ret = clk_prepare_enable(priv->aclk); 565 if (ret < 0) { 566 dev_err(dev, "adc clk enable failed\n"); 567 goto err_bclk_disable; 568 } 569 570 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 571 572 return 0; 573 574 err_bclk_disable: 575 clk_disable_unprepare(priv->bclk); 576 err_regulator_disable: 577 regulator_disable(priv->vref); 578 err_switches_dis: 579 stm32_adc_core_switches_supply_dis(priv); 580 err_vdda_disable: 581 regulator_disable(priv->vdda); 582 583 return ret; 584 } 585 586 static void stm32_adc_core_hw_stop(struct device *dev) 587 { 588 struct stm32_adc_common *common = dev_get_drvdata(dev); 589 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 590 591 /* Backup CCR that may be lost (depends on power state to achieve) */ 592 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 593 clk_disable_unprepare(priv->aclk); 594 clk_disable_unprepare(priv->bclk); 595 regulator_disable(priv->vref); 596 stm32_adc_core_switches_supply_dis(priv); 597 regulator_disable(priv->vdda); 598 } 599 600 static int stm32_adc_core_switches_probe(struct device *dev, 601 struct stm32_adc_priv *priv) 602 { 603 struct device_node *np = dev->of_node; 604 int ret; 605 606 /* Analog switches supply can be controlled by syscfg (optional) */ 607 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 608 if (IS_ERR(priv->syscfg)) { 609 ret = PTR_ERR(priv->syscfg); 610 if (ret != -ENODEV) 611 return dev_err_probe(dev, ret, "Can't probe syscfg\n"); 612 613 priv->syscfg = NULL; 614 } 615 616 /* Booster can be used to supply analog switches (optional) */ 617 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 618 of_property_read_bool(np, "booster-supply")) { 619 priv->booster = devm_regulator_get_optional(dev, "booster"); 620 if (IS_ERR(priv->booster)) { 621 ret = PTR_ERR(priv->booster); 622 if (ret != -ENODEV) 623 return dev_err_probe(dev, ret, "can't get booster\n"); 624 625 priv->booster = NULL; 626 } 627 } 628 629 /* Vdd can be used to supply analog switches (optional) */ 630 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 631 of_property_read_bool(np, "vdd-supply")) { 632 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 633 if (IS_ERR(priv->vdd)) { 634 ret = PTR_ERR(priv->vdd); 635 if (ret != -ENODEV) 636 return dev_err_probe(dev, ret, "can't get vdd\n"); 637 638 priv->vdd = NULL; 639 } 640 } 641 642 if (priv->vdd) { 643 ret = regulator_enable(priv->vdd); 644 if (ret < 0) { 645 dev_err(dev, "vdd enable failed %d\n", ret); 646 return ret; 647 } 648 649 ret = regulator_get_voltage(priv->vdd); 650 if (ret < 0) { 651 dev_err(dev, "vdd get voltage failed %d\n", ret); 652 regulator_disable(priv->vdd); 653 return ret; 654 } 655 priv->vdd_uv = ret; 656 657 regulator_disable(priv->vdd); 658 } 659 660 return 0; 661 } 662 663 static int stm32_adc_probe_identification(struct platform_device *pdev, 664 struct stm32_adc_priv *priv) 665 { 666 struct device_node *np = pdev->dev.of_node; 667 struct device_node *child; 668 const char *compat; 669 int ret, count = 0; 670 u32 id, val; 671 672 if (!priv->cfg->ipid) 673 return 0; 674 675 id = FIELD_GET(STM32MP1_IPIDR_MASK, 676 readl_relaxed(priv->common.base + STM32MP1_ADC_IPDR)); 677 if (id != priv->cfg->ipid) { 678 dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id); 679 return -EINVAL; 680 } 681 682 for_each_child_of_node(np, child) { 683 ret = of_property_read_string(child, "compatible", &compat); 684 if (ret) 685 continue; 686 /* Count child nodes with stm32 adc compatible */ 687 if (strstr(compat, "st,stm32") && strstr(compat, "adc")) 688 count++; 689 } 690 691 val = readl_relaxed(priv->common.base + STM32MP1_ADC_HWCFGR0); 692 priv->nb_adc_max = FIELD_GET(STM32MP1_ADCNUM_MASK, val); 693 if (count > priv->nb_adc_max) { 694 dev_err(&pdev->dev, "Unexpected child number: %d", count); 695 return -EINVAL; 696 } 697 698 val = readl_relaxed(priv->common.base + STM32MP1_ADC_VERR); 699 dev_dbg(&pdev->dev, "ADC version: %lu.%lu\n", 700 FIELD_GET(STM32MP1_MAJREV_MASK, val), 701 FIELD_GET(STM32MP1_MINREV_MASK, val)); 702 703 return 0; 704 } 705 706 static int stm32_adc_probe(struct platform_device *pdev) 707 { 708 struct stm32_adc_priv *priv; 709 struct device *dev = &pdev->dev; 710 struct device_node *np = pdev->dev.of_node; 711 struct resource *res; 712 u32 max_rate; 713 int ret; 714 715 if (!pdev->dev.of_node) 716 return -ENODEV; 717 718 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 719 if (!priv) 720 return -ENOMEM; 721 platform_set_drvdata(pdev, &priv->common); 722 723 priv->cfg = (const struct stm32_adc_priv_cfg *) 724 of_match_device(dev->driver->of_match_table, dev)->data; 725 priv->nb_adc_max = priv->cfg->num_adcs; 726 spin_lock_init(&priv->common.lock); 727 728 priv->common.base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 729 if (IS_ERR(priv->common.base)) 730 return PTR_ERR(priv->common.base); 731 priv->common.phys_base = res->start; 732 733 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 734 if (IS_ERR(priv->vdda)) 735 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), 736 "vdda get failed\n"); 737 738 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 739 if (IS_ERR(priv->vref)) 740 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), 741 "vref get failed\n"); 742 743 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); 744 if (IS_ERR(priv->aclk)) 745 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), 746 "Can't get 'adc' clock\n"); 747 748 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); 749 if (IS_ERR(priv->bclk)) 750 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), 751 "Can't get 'bus' clock\n"); 752 753 ret = stm32_adc_core_switches_probe(dev, priv); 754 if (ret) 755 return ret; 756 757 pm_runtime_get_noresume(dev); 758 pm_runtime_set_active(dev); 759 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 760 pm_runtime_use_autosuspend(dev); 761 pm_runtime_enable(dev); 762 763 ret = stm32_adc_core_hw_start(dev); 764 if (ret) 765 goto err_pm_stop; 766 767 ret = stm32_adc_probe_identification(pdev, priv); 768 if (ret < 0) 769 goto err_hw_stop; 770 771 ret = regulator_get_voltage(priv->vref); 772 if (ret < 0) { 773 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 774 goto err_hw_stop; 775 } 776 priv->common.vref_mv = ret / 1000; 777 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 778 779 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 780 &max_rate); 781 if (!ret) 782 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 783 else 784 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 785 786 ret = priv->cfg->clk_sel(pdev, priv); 787 if (ret < 0) 788 goto err_hw_stop; 789 790 ret = stm32_adc_irq_probe(pdev, priv); 791 if (ret < 0) 792 goto err_hw_stop; 793 794 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 795 if (ret < 0) { 796 dev_err(&pdev->dev, "failed to populate DT children\n"); 797 goto err_irq_remove; 798 } 799 800 pm_runtime_mark_last_busy(dev); 801 pm_runtime_put_autosuspend(dev); 802 803 return 0; 804 805 err_irq_remove: 806 stm32_adc_irq_remove(pdev, priv); 807 err_hw_stop: 808 stm32_adc_core_hw_stop(dev); 809 err_pm_stop: 810 pm_runtime_disable(dev); 811 pm_runtime_set_suspended(dev); 812 pm_runtime_put_noidle(dev); 813 814 return ret; 815 } 816 817 static int stm32_adc_remove(struct platform_device *pdev) 818 { 819 struct stm32_adc_common *common = platform_get_drvdata(pdev); 820 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 821 822 pm_runtime_get_sync(&pdev->dev); 823 of_platform_depopulate(&pdev->dev); 824 stm32_adc_irq_remove(pdev, priv); 825 stm32_adc_core_hw_stop(&pdev->dev); 826 pm_runtime_disable(&pdev->dev); 827 pm_runtime_set_suspended(&pdev->dev); 828 pm_runtime_put_noidle(&pdev->dev); 829 830 return 0; 831 } 832 833 static int stm32_adc_core_runtime_suspend(struct device *dev) 834 { 835 stm32_adc_core_hw_stop(dev); 836 837 return 0; 838 } 839 840 static int stm32_adc_core_runtime_resume(struct device *dev) 841 { 842 return stm32_adc_core_hw_start(dev); 843 } 844 845 static int stm32_adc_core_runtime_idle(struct device *dev) 846 { 847 pm_runtime_mark_last_busy(dev); 848 849 return 0; 850 } 851 852 static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops, 853 stm32_adc_core_runtime_suspend, 854 stm32_adc_core_runtime_resume, 855 stm32_adc_core_runtime_idle); 856 857 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 858 .regs = &stm32f4_adc_common_regs, 859 .clk_sel = stm32f4_adc_clk_sel, 860 .max_clk_rate_hz = 36000000, 861 .num_irqs = 1, 862 .num_adcs = 3, 863 }; 864 865 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 866 .regs = &stm32h7_adc_common_regs, 867 .clk_sel = stm32h7_adc_clk_sel, 868 .max_clk_rate_hz = 36000000, 869 .has_syscfg = HAS_VBOOSTER, 870 .num_irqs = 1, 871 .num_adcs = 2, 872 }; 873 874 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 875 .regs = &stm32h7_adc_common_regs, 876 .clk_sel = stm32h7_adc_clk_sel, 877 .max_clk_rate_hz = 36000000, 878 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 879 .ipid = STM32MP15_IPIDR_NUMBER, 880 .num_irqs = 2, 881 }; 882 883 static const struct stm32_adc_priv_cfg stm32mp13_adc_priv_cfg = { 884 .regs = &stm32mp13_adc_common_regs, 885 .clk_sel = stm32h7_adc_clk_sel, 886 .max_clk_rate_hz = 75 * HZ_PER_MHZ, 887 .ipid = STM32MP13_IPIDR_NUMBER, 888 .num_irqs = 1, 889 }; 890 891 static const struct of_device_id stm32_adc_of_match[] = { 892 { 893 .compatible = "st,stm32f4-adc-core", 894 .data = (void *)&stm32f4_adc_priv_cfg 895 }, { 896 .compatible = "st,stm32h7-adc-core", 897 .data = (void *)&stm32h7_adc_priv_cfg 898 }, { 899 .compatible = "st,stm32mp1-adc-core", 900 .data = (void *)&stm32mp1_adc_priv_cfg 901 }, { 902 .compatible = "st,stm32mp13-adc-core", 903 .data = (void *)&stm32mp13_adc_priv_cfg 904 }, { 905 }, 906 }; 907 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 908 909 static struct platform_driver stm32_adc_driver = { 910 .probe = stm32_adc_probe, 911 .remove = stm32_adc_remove, 912 .driver = { 913 .name = "stm32-adc-core", 914 .of_match_table = stm32_adc_of_match, 915 .pm = pm_ptr(&stm32_adc_core_pm_ops), 916 }, 917 }; 918 module_platform_driver(stm32_adc_driver); 919 920 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 921 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 922 MODULE_LICENSE("GPL v2"); 923 MODULE_ALIAS("platform:stm32-adc-core"); 924