1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Spreadtrum Communications Inc. 3 4 #include <linux/hwspinlock.h> 5 #include <linux/iio/iio.h> 6 #include <linux/interrupt.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/of_device.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 /* PMIC global registers definition */ 14 #define SC27XX_MODULE_EN 0xc08 15 #define SC27XX_MODULE_ADC_EN BIT(5) 16 #define SC27XX_ARM_CLK_EN 0xc10 17 #define SC27XX_CLK_ADC_EN BIT(5) 18 #define SC27XX_CLK_ADC_CLK_EN BIT(6) 19 20 /* ADC controller registers definition */ 21 #define SC27XX_ADC_CTL 0x0 22 #define SC27XX_ADC_CH_CFG 0x4 23 #define SC27XX_ADC_DATA 0x4c 24 #define SC27XX_ADC_INT_EN 0x50 25 #define SC27XX_ADC_INT_CLR 0x54 26 #define SC27XX_ADC_INT_STS 0x58 27 #define SC27XX_ADC_INT_RAW 0x5c 28 29 /* Bits and mask definition for SC27XX_ADC_CTL register */ 30 #define SC27XX_ADC_EN BIT(0) 31 #define SC27XX_ADC_CHN_RUN BIT(1) 32 #define SC27XX_ADC_12BIT_MODE BIT(2) 33 #define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4) 34 #define SC27XX_ADC_RUN_NUM_SHIFT 4 35 36 /* Bits and mask definition for SC27XX_ADC_CH_CFG register */ 37 #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0) 38 #define SC27XX_ADC_SCALE_MASK GENMASK(10, 8) 39 #define SC27XX_ADC_SCALE_SHIFT 8 40 41 /* Bits definitions for SC27XX_ADC_INT_EN registers */ 42 #define SC27XX_ADC_IRQ_EN BIT(0) 43 44 /* Bits definitions for SC27XX_ADC_INT_CLR registers */ 45 #define SC27XX_ADC_IRQ_CLR BIT(0) 46 47 /* Mask definition for SC27XX_ADC_DATA register */ 48 #define SC27XX_ADC_DATA_MASK GENMASK(11, 0) 49 50 /* Timeout (ms) for the trylock of hardware spinlocks */ 51 #define SC27XX_ADC_HWLOCK_TIMEOUT 5000 52 53 /* Maximum ADC channel number */ 54 #define SC27XX_ADC_CHANNEL_MAX 32 55 56 /* ADC voltage ratio definition */ 57 #define SC27XX_VOLT_RATIO(n, d) \ 58 (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d)) 59 #define SC27XX_RATIO_NUMERATOR_OFFSET 16 60 #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0) 61 62 struct sc27xx_adc_data { 63 struct device *dev; 64 struct regmap *regmap; 65 /* 66 * One hardware spinlock to synchronize between the multiple 67 * subsystems which will access the unique ADC controller. 68 */ 69 struct hwspinlock *hwlock; 70 struct completion completion; 71 int channel_scale[SC27XX_ADC_CHANNEL_MAX]; 72 u32 base; 73 int value; 74 int irq; 75 }; 76 77 struct sc27xx_adc_linear_graph { 78 int volt0; 79 int adc0; 80 int volt1; 81 int adc1; 82 }; 83 84 /* 85 * According to the datasheet, we can convert one ADC value to one voltage value 86 * through 2 points in the linear graph. If the voltage is less than 1.2v, we 87 * should use the small-scale graph, and if more than 1.2v, we should use the 88 * big-scale graph. 89 */ 90 static const struct sc27xx_adc_linear_graph big_scale_graph = { 91 4200, 3310, 92 3600, 2832, 93 }; 94 95 static const struct sc27xx_adc_linear_graph small_scale_graph = { 96 1000, 3413, 97 100, 341, 98 }; 99 100 static int sc27xx_adc_get_ratio(int channel, int scale) 101 { 102 switch (channel) { 103 case 1: 104 case 2: 105 case 3: 106 case 4: 107 return scale ? SC27XX_VOLT_RATIO(400, 1025) : 108 SC27XX_VOLT_RATIO(1, 1); 109 case 5: 110 return SC27XX_VOLT_RATIO(7, 29); 111 case 6: 112 return SC27XX_VOLT_RATIO(375, 9000); 113 case 7: 114 case 8: 115 return scale ? SC27XX_VOLT_RATIO(100, 125) : 116 SC27XX_VOLT_RATIO(1, 1); 117 case 19: 118 return SC27XX_VOLT_RATIO(1, 3); 119 default: 120 return SC27XX_VOLT_RATIO(1, 1); 121 } 122 return SC27XX_VOLT_RATIO(1, 1); 123 } 124 125 static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, 126 int scale, int *val) 127 { 128 int ret; 129 u32 tmp; 130 131 reinit_completion(&data->completion); 132 133 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT); 134 if (ret) { 135 dev_err(data->dev, "timeout to get the hwspinlock\n"); 136 return ret; 137 } 138 139 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 140 SC27XX_ADC_EN, SC27XX_ADC_EN); 141 if (ret) 142 goto unlock_adc; 143 144 /* Configure the channel id and scale */ 145 tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK; 146 tmp |= channel & SC27XX_ADC_CHN_ID_MASK; 147 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG, 148 SC27XX_ADC_CHN_ID_MASK | SC27XX_ADC_SCALE_MASK, 149 tmp); 150 if (ret) 151 goto disable_adc; 152 153 /* Select 12bit conversion mode, and only sample 1 time */ 154 tmp = SC27XX_ADC_12BIT_MODE; 155 tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK; 156 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 157 SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE, 158 tmp); 159 if (ret) 160 goto disable_adc; 161 162 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 163 SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN); 164 if (ret) 165 goto disable_adc; 166 167 wait_for_completion(&data->completion); 168 169 disable_adc: 170 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 171 SC27XX_ADC_EN, 0); 172 unlock_adc: 173 hwspin_unlock_raw(data->hwlock); 174 175 if (!ret) 176 *val = data->value; 177 178 return ret; 179 } 180 181 static irqreturn_t sc27xx_adc_isr(int irq, void *dev_id) 182 { 183 struct sc27xx_adc_data *data = dev_id; 184 int ret; 185 186 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, 187 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR); 188 if (ret) 189 return IRQ_RETVAL(ret); 190 191 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, 192 &data->value); 193 if (ret) 194 return IRQ_RETVAL(ret); 195 196 data->value &= SC27XX_ADC_DATA_MASK; 197 complete(&data->completion); 198 199 return IRQ_HANDLED; 200 } 201 202 static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, 203 int channel, int scale, 204 u32 *div_numerator, u32 *div_denominator) 205 { 206 u32 ratio = sc27xx_adc_get_ratio(channel, scale); 207 208 *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; 209 *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; 210 } 211 212 static int sc27xx_adc_to_volt(const struct sc27xx_adc_linear_graph *graph, 213 int raw_adc) 214 { 215 int tmp; 216 217 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1); 218 tmp /= (graph->adc0 - graph->adc1); 219 tmp += graph->volt1; 220 221 return tmp < 0 ? 0 : tmp; 222 } 223 224 static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, 225 int scale, int raw_adc) 226 { 227 u32 numerator, denominator; 228 u32 volt; 229 230 /* 231 * Convert ADC values to voltage values according to the linear graph, 232 * and channel 5 and channel 1 has been calibrated, so we can just 233 * return the voltage values calculated by the linear graph. But other 234 * channels need be calculated to the real voltage values with the 235 * voltage ratio. 236 */ 237 switch (channel) { 238 case 5: 239 return sc27xx_adc_to_volt(&big_scale_graph, raw_adc); 240 241 case 1: 242 return sc27xx_adc_to_volt(&small_scale_graph, raw_adc); 243 244 default: 245 volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc); 246 break; 247 } 248 249 sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator); 250 251 return (volt * denominator + numerator / 2) / numerator; 252 } 253 254 static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data, 255 int channel, int scale, int *val) 256 { 257 int ret, raw_adc; 258 259 ret = sc27xx_adc_read(data, channel, scale, &raw_adc); 260 if (ret) 261 return ret; 262 263 *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc); 264 return 0; 265 } 266 267 static int sc27xx_adc_read_raw(struct iio_dev *indio_dev, 268 struct iio_chan_spec const *chan, 269 int *val, int *val2, long mask) 270 { 271 struct sc27xx_adc_data *data = iio_priv(indio_dev); 272 int scale = data->channel_scale[chan->channel]; 273 int ret, tmp; 274 275 switch (mask) { 276 case IIO_CHAN_INFO_PROCESSED: 277 mutex_lock(&indio_dev->mlock); 278 ret = sc27xx_adc_read_processed(data, chan->channel, scale, 279 &tmp); 280 mutex_unlock(&indio_dev->mlock); 281 282 if (ret) 283 return ret; 284 285 *val = tmp; 286 return IIO_VAL_INT; 287 288 case IIO_CHAN_INFO_SCALE: 289 *val = scale; 290 return IIO_VAL_INT; 291 292 default: 293 return -EINVAL; 294 } 295 } 296 297 static int sc27xx_adc_write_raw(struct iio_dev *indio_dev, 298 struct iio_chan_spec const *chan, 299 int val, int val2, long mask) 300 { 301 struct sc27xx_adc_data *data = iio_priv(indio_dev); 302 303 switch (mask) { 304 case IIO_CHAN_INFO_SCALE: 305 data->channel_scale[chan->channel] = val; 306 return IIO_VAL_INT; 307 308 default: 309 return -EINVAL; 310 } 311 } 312 313 static const struct iio_info sc27xx_info = { 314 .read_raw = &sc27xx_adc_read_raw, 315 .write_raw = &sc27xx_adc_write_raw, 316 }; 317 318 #define SC27XX_ADC_CHANNEL(index) { \ 319 .type = IIO_VOLTAGE, \ 320 .channel = index, \ 321 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | \ 322 BIT(IIO_CHAN_INFO_SCALE), \ 323 .datasheet_name = "CH##index", \ 324 .indexed = 1, \ 325 } 326 327 static const struct iio_chan_spec sc27xx_channels[] = { 328 SC27XX_ADC_CHANNEL(0), 329 SC27XX_ADC_CHANNEL(1), 330 SC27XX_ADC_CHANNEL(2), 331 SC27XX_ADC_CHANNEL(3), 332 SC27XX_ADC_CHANNEL(4), 333 SC27XX_ADC_CHANNEL(5), 334 SC27XX_ADC_CHANNEL(6), 335 SC27XX_ADC_CHANNEL(7), 336 SC27XX_ADC_CHANNEL(8), 337 SC27XX_ADC_CHANNEL(9), 338 SC27XX_ADC_CHANNEL(10), 339 SC27XX_ADC_CHANNEL(11), 340 SC27XX_ADC_CHANNEL(12), 341 SC27XX_ADC_CHANNEL(13), 342 SC27XX_ADC_CHANNEL(14), 343 SC27XX_ADC_CHANNEL(15), 344 SC27XX_ADC_CHANNEL(16), 345 SC27XX_ADC_CHANNEL(17), 346 SC27XX_ADC_CHANNEL(18), 347 SC27XX_ADC_CHANNEL(19), 348 SC27XX_ADC_CHANNEL(20), 349 SC27XX_ADC_CHANNEL(21), 350 SC27XX_ADC_CHANNEL(22), 351 SC27XX_ADC_CHANNEL(23), 352 SC27XX_ADC_CHANNEL(24), 353 SC27XX_ADC_CHANNEL(25), 354 SC27XX_ADC_CHANNEL(26), 355 SC27XX_ADC_CHANNEL(27), 356 SC27XX_ADC_CHANNEL(28), 357 SC27XX_ADC_CHANNEL(29), 358 SC27XX_ADC_CHANNEL(30), 359 SC27XX_ADC_CHANNEL(31), 360 }; 361 362 static int sc27xx_adc_enable(struct sc27xx_adc_data *data) 363 { 364 int ret; 365 366 ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 367 SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN); 368 if (ret) 369 return ret; 370 371 /* Enable ADC work clock and controller clock */ 372 ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 373 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 374 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); 375 if (ret) 376 goto disable_adc; 377 378 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN, 379 SC27XX_ADC_IRQ_EN, SC27XX_ADC_IRQ_EN); 380 if (ret) 381 goto disable_clk; 382 383 return 0; 384 385 disable_clk: 386 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 387 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); 388 disable_adc: 389 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 390 SC27XX_MODULE_ADC_EN, 0); 391 392 return ret; 393 } 394 395 static void sc27xx_adc_disable(void *_data) 396 { 397 struct sc27xx_adc_data *data = _data; 398 399 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN, 400 SC27XX_ADC_IRQ_EN, 0); 401 402 /* Disable ADC work clock and controller clock */ 403 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 404 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); 405 406 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 407 SC27XX_MODULE_ADC_EN, 0); 408 } 409 410 static void sc27xx_adc_free_hwlock(void *_data) 411 { 412 struct hwspinlock *hwlock = _data; 413 414 hwspin_lock_free(hwlock); 415 } 416 417 static int sc27xx_adc_probe(struct platform_device *pdev) 418 { 419 struct device_node *np = pdev->dev.of_node; 420 struct sc27xx_adc_data *sc27xx_data; 421 struct iio_dev *indio_dev; 422 int ret; 423 424 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*sc27xx_data)); 425 if (!indio_dev) 426 return -ENOMEM; 427 428 sc27xx_data = iio_priv(indio_dev); 429 430 sc27xx_data->regmap = dev_get_regmap(pdev->dev.parent, NULL); 431 if (!sc27xx_data->regmap) { 432 dev_err(&pdev->dev, "failed to get ADC regmap\n"); 433 return -ENODEV; 434 } 435 436 ret = of_property_read_u32(np, "reg", &sc27xx_data->base); 437 if (ret) { 438 dev_err(&pdev->dev, "failed to get ADC base address\n"); 439 return ret; 440 } 441 442 sc27xx_data->irq = platform_get_irq(pdev, 0); 443 if (sc27xx_data->irq < 0) { 444 dev_err(&pdev->dev, "failed to get ADC irq number\n"); 445 return sc27xx_data->irq; 446 } 447 448 ret = of_hwspin_lock_get_id(np, 0); 449 if (ret < 0) { 450 dev_err(&pdev->dev, "failed to get hwspinlock id\n"); 451 return ret; 452 } 453 454 sc27xx_data->hwlock = hwspin_lock_request_specific(ret); 455 if (!sc27xx_data->hwlock) { 456 dev_err(&pdev->dev, "failed to request hwspinlock\n"); 457 return -ENXIO; 458 } 459 460 ret = devm_add_action(&pdev->dev, sc27xx_adc_free_hwlock, 461 sc27xx_data->hwlock); 462 if (ret) { 463 sc27xx_adc_free_hwlock(sc27xx_data->hwlock); 464 dev_err(&pdev->dev, "failed to add hwspinlock action\n"); 465 return ret; 466 } 467 468 init_completion(&sc27xx_data->completion); 469 sc27xx_data->dev = &pdev->dev; 470 471 ret = sc27xx_adc_enable(sc27xx_data); 472 if (ret) { 473 dev_err(&pdev->dev, "failed to enable ADC module\n"); 474 return ret; 475 } 476 477 ret = devm_add_action(&pdev->dev, sc27xx_adc_disable, sc27xx_data); 478 if (ret) { 479 sc27xx_adc_disable(sc27xx_data); 480 dev_err(&pdev->dev, "failed to add ADC disable action\n"); 481 return ret; 482 } 483 484 ret = devm_request_threaded_irq(&pdev->dev, sc27xx_data->irq, NULL, 485 sc27xx_adc_isr, IRQF_ONESHOT, 486 pdev->name, sc27xx_data); 487 if (ret) { 488 dev_err(&pdev->dev, "failed to request ADC irq\n"); 489 return ret; 490 } 491 492 indio_dev->dev.parent = &pdev->dev; 493 indio_dev->name = dev_name(&pdev->dev); 494 indio_dev->modes = INDIO_DIRECT_MODE; 495 indio_dev->info = &sc27xx_info; 496 indio_dev->channels = sc27xx_channels; 497 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels); 498 ret = devm_iio_device_register(&pdev->dev, indio_dev); 499 if (ret) 500 dev_err(&pdev->dev, "could not register iio (ADC)"); 501 502 return ret; 503 } 504 505 static const struct of_device_id sc27xx_adc_of_match[] = { 506 { .compatible = "sprd,sc2731-adc", }, 507 { } 508 }; 509 510 static struct platform_driver sc27xx_adc_driver = { 511 .probe = sc27xx_adc_probe, 512 .driver = { 513 .name = "sc27xx-adc", 514 .of_match_table = sc27xx_adc_of_match, 515 }, 516 }; 517 518 module_platform_driver(sc27xx_adc_driver); 519 520 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>"); 521 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver"); 522 MODULE_LICENSE("GPL v2"); 523