1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Spreadtrum Communications Inc. 3 4 #include <linux/hwspinlock.h> 5 #include <linux/iio/iio.h> 6 #include <linux/interrupt.h> 7 #include <linux/module.h> 8 #include <linux/nvmem-consumer.h> 9 #include <linux/of.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/slab.h> 14 15 /* PMIC global registers definition */ 16 #define SC27XX_MODULE_EN 0xc08 17 #define SC27XX_MODULE_ADC_EN BIT(5) 18 #define SC27XX_ARM_CLK_EN 0xc10 19 #define SC27XX_CLK_ADC_EN BIT(5) 20 #define SC27XX_CLK_ADC_CLK_EN BIT(6) 21 22 /* ADC controller registers definition */ 23 #define SC27XX_ADC_CTL 0x0 24 #define SC27XX_ADC_CH_CFG 0x4 25 #define SC27XX_ADC_DATA 0x4c 26 #define SC27XX_ADC_INT_EN 0x50 27 #define SC27XX_ADC_INT_CLR 0x54 28 #define SC27XX_ADC_INT_STS 0x58 29 #define SC27XX_ADC_INT_RAW 0x5c 30 31 /* Bits and mask definition for SC27XX_ADC_CTL register */ 32 #define SC27XX_ADC_EN BIT(0) 33 #define SC27XX_ADC_CHN_RUN BIT(1) 34 #define SC27XX_ADC_12BIT_MODE BIT(2) 35 #define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4) 36 #define SC27XX_ADC_RUN_NUM_SHIFT 4 37 38 /* Bits and mask definition for SC27XX_ADC_CH_CFG register */ 39 #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0) 40 #define SC27XX_ADC_SCALE_MASK GENMASK(10, 8) 41 #define SC27XX_ADC_SCALE_SHIFT 8 42 43 /* Bits definitions for SC27XX_ADC_INT_EN registers */ 44 #define SC27XX_ADC_IRQ_EN BIT(0) 45 46 /* Bits definitions for SC27XX_ADC_INT_CLR registers */ 47 #define SC27XX_ADC_IRQ_CLR BIT(0) 48 49 /* Mask definition for SC27XX_ADC_DATA register */ 50 #define SC27XX_ADC_DATA_MASK GENMASK(11, 0) 51 52 /* Timeout (ms) for the trylock of hardware spinlocks */ 53 #define SC27XX_ADC_HWLOCK_TIMEOUT 5000 54 55 /* Maximum ADC channel number */ 56 #define SC27XX_ADC_CHANNEL_MAX 32 57 58 /* ADC voltage ratio definition */ 59 #define SC27XX_VOLT_RATIO(n, d) \ 60 (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d)) 61 #define SC27XX_RATIO_NUMERATOR_OFFSET 16 62 #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0) 63 64 struct sc27xx_adc_data { 65 struct device *dev; 66 struct regmap *regmap; 67 /* 68 * One hardware spinlock to synchronize between the multiple 69 * subsystems which will access the unique ADC controller. 70 */ 71 struct hwspinlock *hwlock; 72 struct completion completion; 73 int channel_scale[SC27XX_ADC_CHANNEL_MAX]; 74 u32 base; 75 int value; 76 int irq; 77 }; 78 79 struct sc27xx_adc_linear_graph { 80 int volt0; 81 int adc0; 82 int volt1; 83 int adc1; 84 }; 85 86 /* 87 * According to the datasheet, we can convert one ADC value to one voltage value 88 * through 2 points in the linear graph. If the voltage is less than 1.2v, we 89 * should use the small-scale graph, and if more than 1.2v, we should use the 90 * big-scale graph. 91 */ 92 static struct sc27xx_adc_linear_graph big_scale_graph = { 93 4200, 3310, 94 3600, 2832, 95 }; 96 97 static struct sc27xx_adc_linear_graph small_scale_graph = { 98 1000, 3413, 99 100, 341, 100 }; 101 102 static const struct sc27xx_adc_linear_graph big_scale_graph_calib = { 103 4200, 856, 104 3600, 733, 105 }; 106 107 static const struct sc27xx_adc_linear_graph small_scale_graph_calib = { 108 1000, 833, 109 100, 80, 110 }; 111 112 static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc) 113 { 114 return ((calib_data & 0xff) + calib_adc - 128) * 4; 115 } 116 117 static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, 118 bool big_scale) 119 { 120 const struct sc27xx_adc_linear_graph *calib_graph; 121 struct sc27xx_adc_linear_graph *graph; 122 struct nvmem_cell *cell; 123 const char *cell_name; 124 u32 calib_data = 0; 125 void *buf; 126 size_t len; 127 128 if (big_scale) { 129 calib_graph = &big_scale_graph_calib; 130 graph = &big_scale_graph; 131 cell_name = "big_scale_calib"; 132 } else { 133 calib_graph = &small_scale_graph_calib; 134 graph = &small_scale_graph; 135 cell_name = "small_scale_calib"; 136 } 137 138 cell = nvmem_cell_get(data->dev, cell_name); 139 if (IS_ERR(cell)) 140 return PTR_ERR(cell); 141 142 buf = nvmem_cell_read(cell, &len); 143 nvmem_cell_put(cell); 144 145 if (IS_ERR(buf)) 146 return PTR_ERR(buf); 147 148 memcpy(&calib_data, buf, min(len, sizeof(u32))); 149 150 /* Only need to calibrate the adc values in the linear graph. */ 151 graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0); 152 graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8, 153 calib_graph->adc1); 154 155 kfree(buf); 156 return 0; 157 } 158 159 static int sc27xx_adc_get_ratio(int channel, int scale) 160 { 161 switch (channel) { 162 case 1: 163 case 2: 164 case 3: 165 case 4: 166 return scale ? SC27XX_VOLT_RATIO(400, 1025) : 167 SC27XX_VOLT_RATIO(1, 1); 168 case 5: 169 return SC27XX_VOLT_RATIO(7, 29); 170 case 6: 171 return SC27XX_VOLT_RATIO(375, 9000); 172 case 7: 173 case 8: 174 return scale ? SC27XX_VOLT_RATIO(100, 125) : 175 SC27XX_VOLT_RATIO(1, 1); 176 case 19: 177 return SC27XX_VOLT_RATIO(1, 3); 178 default: 179 return SC27XX_VOLT_RATIO(1, 1); 180 } 181 return SC27XX_VOLT_RATIO(1, 1); 182 } 183 184 static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, 185 int scale, int *val) 186 { 187 int ret; 188 u32 tmp; 189 190 reinit_completion(&data->completion); 191 192 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT); 193 if (ret) { 194 dev_err(data->dev, "timeout to get the hwspinlock\n"); 195 return ret; 196 } 197 198 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 199 SC27XX_ADC_EN, SC27XX_ADC_EN); 200 if (ret) 201 goto unlock_adc; 202 203 /* Configure the channel id and scale */ 204 tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK; 205 tmp |= channel & SC27XX_ADC_CHN_ID_MASK; 206 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG, 207 SC27XX_ADC_CHN_ID_MASK | SC27XX_ADC_SCALE_MASK, 208 tmp); 209 if (ret) 210 goto disable_adc; 211 212 /* Select 12bit conversion mode, and only sample 1 time */ 213 tmp = SC27XX_ADC_12BIT_MODE; 214 tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK; 215 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 216 SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE, 217 tmp); 218 if (ret) 219 goto disable_adc; 220 221 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 222 SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN); 223 if (ret) 224 goto disable_adc; 225 226 wait_for_completion(&data->completion); 227 228 disable_adc: 229 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 230 SC27XX_ADC_EN, 0); 231 unlock_adc: 232 hwspin_unlock_raw(data->hwlock); 233 234 if (!ret) 235 *val = data->value; 236 237 return ret; 238 } 239 240 static irqreturn_t sc27xx_adc_isr(int irq, void *dev_id) 241 { 242 struct sc27xx_adc_data *data = dev_id; 243 int ret; 244 245 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, 246 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR); 247 if (ret) 248 return IRQ_RETVAL(ret); 249 250 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, 251 &data->value); 252 if (ret) 253 return IRQ_RETVAL(ret); 254 255 data->value &= SC27XX_ADC_DATA_MASK; 256 complete(&data->completion); 257 258 return IRQ_HANDLED; 259 } 260 261 static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, 262 int channel, int scale, 263 u32 *div_numerator, u32 *div_denominator) 264 { 265 u32 ratio = sc27xx_adc_get_ratio(channel, scale); 266 267 *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; 268 *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; 269 } 270 271 static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, 272 int raw_adc) 273 { 274 int tmp; 275 276 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1); 277 tmp /= (graph->adc0 - graph->adc1); 278 tmp += graph->volt1; 279 280 return tmp < 0 ? 0 : tmp; 281 } 282 283 static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, 284 int scale, int raw_adc) 285 { 286 u32 numerator, denominator; 287 u32 volt; 288 289 /* 290 * Convert ADC values to voltage values according to the linear graph, 291 * and channel 5 and channel 1 has been calibrated, so we can just 292 * return the voltage values calculated by the linear graph. But other 293 * channels need be calculated to the real voltage values with the 294 * voltage ratio. 295 */ 296 switch (channel) { 297 case 5: 298 return sc27xx_adc_to_volt(&big_scale_graph, raw_adc); 299 300 case 1: 301 return sc27xx_adc_to_volt(&small_scale_graph, raw_adc); 302 303 default: 304 volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc); 305 break; 306 } 307 308 sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator); 309 310 return (volt * denominator + numerator / 2) / numerator; 311 } 312 313 static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data, 314 int channel, int scale, int *val) 315 { 316 int ret, raw_adc; 317 318 ret = sc27xx_adc_read(data, channel, scale, &raw_adc); 319 if (ret) 320 return ret; 321 322 *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc); 323 return 0; 324 } 325 326 static int sc27xx_adc_read_raw(struct iio_dev *indio_dev, 327 struct iio_chan_spec const *chan, 328 int *val, int *val2, long mask) 329 { 330 struct sc27xx_adc_data *data = iio_priv(indio_dev); 331 int scale = data->channel_scale[chan->channel]; 332 int ret, tmp; 333 334 switch (mask) { 335 case IIO_CHAN_INFO_RAW: 336 mutex_lock(&indio_dev->mlock); 337 ret = sc27xx_adc_read(data, chan->channel, scale, &tmp); 338 mutex_unlock(&indio_dev->mlock); 339 340 if (ret) 341 return ret; 342 343 *val = tmp; 344 return IIO_VAL_INT; 345 346 case IIO_CHAN_INFO_PROCESSED: 347 mutex_lock(&indio_dev->mlock); 348 ret = sc27xx_adc_read_processed(data, chan->channel, scale, 349 &tmp); 350 mutex_unlock(&indio_dev->mlock); 351 352 if (ret) 353 return ret; 354 355 *val = tmp; 356 return IIO_VAL_INT; 357 358 case IIO_CHAN_INFO_SCALE: 359 *val = scale; 360 return IIO_VAL_INT; 361 362 default: 363 return -EINVAL; 364 } 365 } 366 367 static int sc27xx_adc_write_raw(struct iio_dev *indio_dev, 368 struct iio_chan_spec const *chan, 369 int val, int val2, long mask) 370 { 371 struct sc27xx_adc_data *data = iio_priv(indio_dev); 372 373 switch (mask) { 374 case IIO_CHAN_INFO_SCALE: 375 data->channel_scale[chan->channel] = val; 376 return IIO_VAL_INT; 377 378 default: 379 return -EINVAL; 380 } 381 } 382 383 static const struct iio_info sc27xx_info = { 384 .read_raw = &sc27xx_adc_read_raw, 385 .write_raw = &sc27xx_adc_write_raw, 386 }; 387 388 #define SC27XX_ADC_CHANNEL(index, mask) { \ 389 .type = IIO_VOLTAGE, \ 390 .channel = index, \ 391 .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \ 392 .datasheet_name = "CH##index", \ 393 .indexed = 1, \ 394 } 395 396 static const struct iio_chan_spec sc27xx_channels[] = { 397 SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)), 398 SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)), 399 SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)), 400 SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)), 401 SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)), 402 SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)), 403 SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)), 404 SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)), 405 SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)), 406 SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)), 407 SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)), 408 SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)), 409 SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)), 410 SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)), 411 SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)), 412 SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)), 413 SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)), 414 SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)), 415 SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)), 416 SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)), 417 SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)), 418 SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)), 419 SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)), 420 SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)), 421 SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)), 422 SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)), 423 SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)), 424 SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)), 425 SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)), 426 SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)), 427 SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)), 428 SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)), 429 }; 430 431 static int sc27xx_adc_enable(struct sc27xx_adc_data *data) 432 { 433 int ret; 434 435 ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 436 SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN); 437 if (ret) 438 return ret; 439 440 /* Enable ADC work clock and controller clock */ 441 ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 442 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 443 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); 444 if (ret) 445 goto disable_adc; 446 447 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN, 448 SC27XX_ADC_IRQ_EN, SC27XX_ADC_IRQ_EN); 449 if (ret) 450 goto disable_clk; 451 452 /* ADC channel scales' calibration from nvmem device */ 453 ret = sc27xx_adc_scale_calibration(data, true); 454 if (ret) 455 goto disable_clk; 456 457 ret = sc27xx_adc_scale_calibration(data, false); 458 if (ret) 459 goto disable_clk; 460 461 return 0; 462 463 disable_clk: 464 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 465 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); 466 disable_adc: 467 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 468 SC27XX_MODULE_ADC_EN, 0); 469 470 return ret; 471 } 472 473 static void sc27xx_adc_disable(void *_data) 474 { 475 struct sc27xx_adc_data *data = _data; 476 477 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN, 478 SC27XX_ADC_IRQ_EN, 0); 479 480 /* Disable ADC work clock and controller clock */ 481 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 482 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); 483 484 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 485 SC27XX_MODULE_ADC_EN, 0); 486 } 487 488 static void sc27xx_adc_free_hwlock(void *_data) 489 { 490 struct hwspinlock *hwlock = _data; 491 492 hwspin_lock_free(hwlock); 493 } 494 495 static int sc27xx_adc_probe(struct platform_device *pdev) 496 { 497 struct device_node *np = pdev->dev.of_node; 498 struct sc27xx_adc_data *sc27xx_data; 499 struct iio_dev *indio_dev; 500 int ret; 501 502 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*sc27xx_data)); 503 if (!indio_dev) 504 return -ENOMEM; 505 506 sc27xx_data = iio_priv(indio_dev); 507 508 sc27xx_data->regmap = dev_get_regmap(pdev->dev.parent, NULL); 509 if (!sc27xx_data->regmap) { 510 dev_err(&pdev->dev, "failed to get ADC regmap\n"); 511 return -ENODEV; 512 } 513 514 ret = of_property_read_u32(np, "reg", &sc27xx_data->base); 515 if (ret) { 516 dev_err(&pdev->dev, "failed to get ADC base address\n"); 517 return ret; 518 } 519 520 sc27xx_data->irq = platform_get_irq(pdev, 0); 521 if (sc27xx_data->irq < 0) { 522 dev_err(&pdev->dev, "failed to get ADC irq number\n"); 523 return sc27xx_data->irq; 524 } 525 526 ret = of_hwspin_lock_get_id(np, 0); 527 if (ret < 0) { 528 dev_err(&pdev->dev, "failed to get hwspinlock id\n"); 529 return ret; 530 } 531 532 sc27xx_data->hwlock = hwspin_lock_request_specific(ret); 533 if (!sc27xx_data->hwlock) { 534 dev_err(&pdev->dev, "failed to request hwspinlock\n"); 535 return -ENXIO; 536 } 537 538 ret = devm_add_action(&pdev->dev, sc27xx_adc_free_hwlock, 539 sc27xx_data->hwlock); 540 if (ret) { 541 sc27xx_adc_free_hwlock(sc27xx_data->hwlock); 542 dev_err(&pdev->dev, "failed to add hwspinlock action\n"); 543 return ret; 544 } 545 546 init_completion(&sc27xx_data->completion); 547 sc27xx_data->dev = &pdev->dev; 548 549 ret = sc27xx_adc_enable(sc27xx_data); 550 if (ret) { 551 dev_err(&pdev->dev, "failed to enable ADC module\n"); 552 return ret; 553 } 554 555 ret = devm_add_action(&pdev->dev, sc27xx_adc_disable, sc27xx_data); 556 if (ret) { 557 sc27xx_adc_disable(sc27xx_data); 558 dev_err(&pdev->dev, "failed to add ADC disable action\n"); 559 return ret; 560 } 561 562 ret = devm_request_threaded_irq(&pdev->dev, sc27xx_data->irq, NULL, 563 sc27xx_adc_isr, IRQF_ONESHOT, 564 pdev->name, sc27xx_data); 565 if (ret) { 566 dev_err(&pdev->dev, "failed to request ADC irq\n"); 567 return ret; 568 } 569 570 indio_dev->dev.parent = &pdev->dev; 571 indio_dev->name = dev_name(&pdev->dev); 572 indio_dev->modes = INDIO_DIRECT_MODE; 573 indio_dev->info = &sc27xx_info; 574 indio_dev->channels = sc27xx_channels; 575 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels); 576 ret = devm_iio_device_register(&pdev->dev, indio_dev); 577 if (ret) 578 dev_err(&pdev->dev, "could not register iio (ADC)"); 579 580 return ret; 581 } 582 583 static const struct of_device_id sc27xx_adc_of_match[] = { 584 { .compatible = "sprd,sc2731-adc", }, 585 { } 586 }; 587 588 static struct platform_driver sc27xx_adc_driver = { 589 .probe = sc27xx_adc_probe, 590 .driver = { 591 .name = "sc27xx-adc", 592 .of_match_table = sc27xx_adc_of_match, 593 }, 594 }; 595 596 module_platform_driver(sc27xx_adc_driver); 597 598 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>"); 599 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver"); 600 MODULE_LICENSE("GPL v2"); 601