1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Spreadtrum Communications Inc. 3 4 #include <linux/hwspinlock.h> 5 #include <linux/iio/iio.h> 6 #include <linux/interrupt.h> 7 #include <linux/module.h> 8 #include <linux/nvmem-consumer.h> 9 #include <linux/of.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/slab.h> 14 15 /* PMIC global registers definition */ 16 #define SC27XX_MODULE_EN 0xc08 17 #define SC27XX_MODULE_ADC_EN BIT(5) 18 #define SC27XX_ARM_CLK_EN 0xc10 19 #define SC27XX_CLK_ADC_EN BIT(5) 20 #define SC27XX_CLK_ADC_CLK_EN BIT(6) 21 22 /* ADC controller registers definition */ 23 #define SC27XX_ADC_CTL 0x0 24 #define SC27XX_ADC_CH_CFG 0x4 25 #define SC27XX_ADC_DATA 0x4c 26 #define SC27XX_ADC_INT_EN 0x50 27 #define SC27XX_ADC_INT_CLR 0x54 28 #define SC27XX_ADC_INT_STS 0x58 29 #define SC27XX_ADC_INT_RAW 0x5c 30 31 /* Bits and mask definition for SC27XX_ADC_CTL register */ 32 #define SC27XX_ADC_EN BIT(0) 33 #define SC27XX_ADC_CHN_RUN BIT(1) 34 #define SC27XX_ADC_12BIT_MODE BIT(2) 35 #define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4) 36 #define SC27XX_ADC_RUN_NUM_SHIFT 4 37 38 /* Bits and mask definition for SC27XX_ADC_CH_CFG register */ 39 #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0) 40 #define SC27XX_ADC_SCALE_MASK GENMASK(10, 8) 41 #define SC27XX_ADC_SCALE_SHIFT 8 42 43 /* Bits definitions for SC27XX_ADC_INT_EN registers */ 44 #define SC27XX_ADC_IRQ_EN BIT(0) 45 46 /* Bits definitions for SC27XX_ADC_INT_CLR registers */ 47 #define SC27XX_ADC_IRQ_CLR BIT(0) 48 49 /* Mask definition for SC27XX_ADC_DATA register */ 50 #define SC27XX_ADC_DATA_MASK GENMASK(11, 0) 51 52 /* Timeout (ms) for the trylock of hardware spinlocks */ 53 #define SC27XX_ADC_HWLOCK_TIMEOUT 5000 54 55 /* Timeout (ms) for ADC data conversion according to ADC datasheet */ 56 #define SC27XX_ADC_RDY_TIMEOUT 100 57 58 /* Maximum ADC channel number */ 59 #define SC27XX_ADC_CHANNEL_MAX 32 60 61 /* ADC voltage ratio definition */ 62 #define SC27XX_VOLT_RATIO(n, d) \ 63 (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d)) 64 #define SC27XX_RATIO_NUMERATOR_OFFSET 16 65 #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0) 66 67 struct sc27xx_adc_data { 68 struct device *dev; 69 struct regmap *regmap; 70 /* 71 * One hardware spinlock to synchronize between the multiple 72 * subsystems which will access the unique ADC controller. 73 */ 74 struct hwspinlock *hwlock; 75 struct completion completion; 76 int channel_scale[SC27XX_ADC_CHANNEL_MAX]; 77 u32 base; 78 int value; 79 int irq; 80 }; 81 82 struct sc27xx_adc_linear_graph { 83 int volt0; 84 int adc0; 85 int volt1; 86 int adc1; 87 }; 88 89 /* 90 * According to the datasheet, we can convert one ADC value to one voltage value 91 * through 2 points in the linear graph. If the voltage is less than 1.2v, we 92 * should use the small-scale graph, and if more than 1.2v, we should use the 93 * big-scale graph. 94 */ 95 static struct sc27xx_adc_linear_graph big_scale_graph = { 96 4200, 3310, 97 3600, 2832, 98 }; 99 100 static struct sc27xx_adc_linear_graph small_scale_graph = { 101 1000, 3413, 102 100, 341, 103 }; 104 105 static const struct sc27xx_adc_linear_graph big_scale_graph_calib = { 106 4200, 856, 107 3600, 733, 108 }; 109 110 static const struct sc27xx_adc_linear_graph small_scale_graph_calib = { 111 1000, 833, 112 100, 80, 113 }; 114 115 static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc) 116 { 117 return ((calib_data & 0xff) + calib_adc - 128) * 4; 118 } 119 120 static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, 121 bool big_scale) 122 { 123 const struct sc27xx_adc_linear_graph *calib_graph; 124 struct sc27xx_adc_linear_graph *graph; 125 struct nvmem_cell *cell; 126 const char *cell_name; 127 u32 calib_data = 0; 128 void *buf; 129 size_t len; 130 131 if (big_scale) { 132 calib_graph = &big_scale_graph_calib; 133 graph = &big_scale_graph; 134 cell_name = "big_scale_calib"; 135 } else { 136 calib_graph = &small_scale_graph_calib; 137 graph = &small_scale_graph; 138 cell_name = "small_scale_calib"; 139 } 140 141 cell = nvmem_cell_get(data->dev, cell_name); 142 if (IS_ERR(cell)) 143 return PTR_ERR(cell); 144 145 buf = nvmem_cell_read(cell, &len); 146 nvmem_cell_put(cell); 147 148 if (IS_ERR(buf)) 149 return PTR_ERR(buf); 150 151 memcpy(&calib_data, buf, min(len, sizeof(u32))); 152 153 /* Only need to calibrate the adc values in the linear graph. */ 154 graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0); 155 graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8, 156 calib_graph->adc1); 157 158 kfree(buf); 159 return 0; 160 } 161 162 static int sc27xx_adc_get_ratio(int channel, int scale) 163 { 164 switch (channel) { 165 case 1: 166 case 2: 167 case 3: 168 case 4: 169 return scale ? SC27XX_VOLT_RATIO(400, 1025) : 170 SC27XX_VOLT_RATIO(1, 1); 171 case 5: 172 return SC27XX_VOLT_RATIO(7, 29); 173 case 6: 174 return SC27XX_VOLT_RATIO(375, 9000); 175 case 7: 176 case 8: 177 return scale ? SC27XX_VOLT_RATIO(100, 125) : 178 SC27XX_VOLT_RATIO(1, 1); 179 case 19: 180 return SC27XX_VOLT_RATIO(1, 3); 181 default: 182 return SC27XX_VOLT_RATIO(1, 1); 183 } 184 return SC27XX_VOLT_RATIO(1, 1); 185 } 186 187 static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, 188 int scale, int *val) 189 { 190 int ret; 191 u32 tmp; 192 193 reinit_completion(&data->completion); 194 195 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT); 196 if (ret) { 197 dev_err(data->dev, "timeout to get the hwspinlock\n"); 198 return ret; 199 } 200 201 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 202 SC27XX_ADC_EN, SC27XX_ADC_EN); 203 if (ret) 204 goto unlock_adc; 205 206 /* Configure the channel id and scale */ 207 tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK; 208 tmp |= channel & SC27XX_ADC_CHN_ID_MASK; 209 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG, 210 SC27XX_ADC_CHN_ID_MASK | SC27XX_ADC_SCALE_MASK, 211 tmp); 212 if (ret) 213 goto disable_adc; 214 215 /* Select 12bit conversion mode, and only sample 1 time */ 216 tmp = SC27XX_ADC_12BIT_MODE; 217 tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK; 218 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 219 SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE, 220 tmp); 221 if (ret) 222 goto disable_adc; 223 224 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 225 SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN); 226 if (ret) 227 goto disable_adc; 228 229 ret = wait_for_completion_timeout(&data->completion, 230 msecs_to_jiffies(SC27XX_ADC_RDY_TIMEOUT)); 231 if (!ret) { 232 dev_err(data->dev, "read ADC data timeout\n"); 233 ret = -ETIMEDOUT; 234 } else { 235 ret = 0; 236 } 237 238 disable_adc: 239 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 240 SC27XX_ADC_EN, 0); 241 unlock_adc: 242 hwspin_unlock_raw(data->hwlock); 243 244 if (!ret) 245 *val = data->value; 246 247 return ret; 248 } 249 250 static irqreturn_t sc27xx_adc_isr(int irq, void *dev_id) 251 { 252 struct sc27xx_adc_data *data = dev_id; 253 int ret; 254 255 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, 256 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR); 257 if (ret) 258 return IRQ_RETVAL(ret); 259 260 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, 261 &data->value); 262 if (ret) 263 return IRQ_RETVAL(ret); 264 265 data->value &= SC27XX_ADC_DATA_MASK; 266 complete(&data->completion); 267 268 return IRQ_HANDLED; 269 } 270 271 static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, 272 int channel, int scale, 273 u32 *div_numerator, u32 *div_denominator) 274 { 275 u32 ratio = sc27xx_adc_get_ratio(channel, scale); 276 277 *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; 278 *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; 279 } 280 281 static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, 282 int raw_adc) 283 { 284 int tmp; 285 286 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1); 287 tmp /= (graph->adc0 - graph->adc1); 288 tmp += graph->volt1; 289 290 return tmp < 0 ? 0 : tmp; 291 } 292 293 static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, 294 int scale, int raw_adc) 295 { 296 u32 numerator, denominator; 297 u32 volt; 298 299 /* 300 * Convert ADC values to voltage values according to the linear graph, 301 * and channel 5 and channel 1 has been calibrated, so we can just 302 * return the voltage values calculated by the linear graph. But other 303 * channels need be calculated to the real voltage values with the 304 * voltage ratio. 305 */ 306 switch (channel) { 307 case 5: 308 return sc27xx_adc_to_volt(&big_scale_graph, raw_adc); 309 310 case 1: 311 return sc27xx_adc_to_volt(&small_scale_graph, raw_adc); 312 313 default: 314 volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc); 315 break; 316 } 317 318 sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator); 319 320 return (volt * denominator + numerator / 2) / numerator; 321 } 322 323 static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data, 324 int channel, int scale, int *val) 325 { 326 int ret, raw_adc; 327 328 ret = sc27xx_adc_read(data, channel, scale, &raw_adc); 329 if (ret) 330 return ret; 331 332 *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc); 333 return 0; 334 } 335 336 static int sc27xx_adc_read_raw(struct iio_dev *indio_dev, 337 struct iio_chan_spec const *chan, 338 int *val, int *val2, long mask) 339 { 340 struct sc27xx_adc_data *data = iio_priv(indio_dev); 341 int scale = data->channel_scale[chan->channel]; 342 int ret, tmp; 343 344 switch (mask) { 345 case IIO_CHAN_INFO_RAW: 346 mutex_lock(&indio_dev->mlock); 347 ret = sc27xx_adc_read(data, chan->channel, scale, &tmp); 348 mutex_unlock(&indio_dev->mlock); 349 350 if (ret) 351 return ret; 352 353 *val = tmp; 354 return IIO_VAL_INT; 355 356 case IIO_CHAN_INFO_PROCESSED: 357 mutex_lock(&indio_dev->mlock); 358 ret = sc27xx_adc_read_processed(data, chan->channel, scale, 359 &tmp); 360 mutex_unlock(&indio_dev->mlock); 361 362 if (ret) 363 return ret; 364 365 *val = tmp; 366 return IIO_VAL_INT; 367 368 case IIO_CHAN_INFO_SCALE: 369 *val = scale; 370 return IIO_VAL_INT; 371 372 default: 373 return -EINVAL; 374 } 375 } 376 377 static int sc27xx_adc_write_raw(struct iio_dev *indio_dev, 378 struct iio_chan_spec const *chan, 379 int val, int val2, long mask) 380 { 381 struct sc27xx_adc_data *data = iio_priv(indio_dev); 382 383 switch (mask) { 384 case IIO_CHAN_INFO_SCALE: 385 data->channel_scale[chan->channel] = val; 386 return IIO_VAL_INT; 387 388 default: 389 return -EINVAL; 390 } 391 } 392 393 static const struct iio_info sc27xx_info = { 394 .read_raw = &sc27xx_adc_read_raw, 395 .write_raw = &sc27xx_adc_write_raw, 396 }; 397 398 #define SC27XX_ADC_CHANNEL(index, mask) { \ 399 .type = IIO_VOLTAGE, \ 400 .channel = index, \ 401 .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \ 402 .datasheet_name = "CH##index", \ 403 .indexed = 1, \ 404 } 405 406 static const struct iio_chan_spec sc27xx_channels[] = { 407 SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)), 408 SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)), 409 SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)), 410 SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)), 411 SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)), 412 SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)), 413 SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)), 414 SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)), 415 SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)), 416 SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)), 417 SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)), 418 SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)), 419 SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)), 420 SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)), 421 SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)), 422 SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)), 423 SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)), 424 SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)), 425 SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)), 426 SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)), 427 SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)), 428 SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)), 429 SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)), 430 SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)), 431 SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)), 432 SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)), 433 SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)), 434 SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)), 435 SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)), 436 SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)), 437 SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)), 438 SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)), 439 }; 440 441 static int sc27xx_adc_enable(struct sc27xx_adc_data *data) 442 { 443 int ret; 444 445 ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 446 SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN); 447 if (ret) 448 return ret; 449 450 /* Enable ADC work clock and controller clock */ 451 ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 452 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 453 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); 454 if (ret) 455 goto disable_adc; 456 457 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN, 458 SC27XX_ADC_IRQ_EN, SC27XX_ADC_IRQ_EN); 459 if (ret) 460 goto disable_clk; 461 462 /* ADC channel scales' calibration from nvmem device */ 463 ret = sc27xx_adc_scale_calibration(data, true); 464 if (ret) 465 goto disable_clk; 466 467 ret = sc27xx_adc_scale_calibration(data, false); 468 if (ret) 469 goto disable_clk; 470 471 return 0; 472 473 disable_clk: 474 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 475 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); 476 disable_adc: 477 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 478 SC27XX_MODULE_ADC_EN, 0); 479 480 return ret; 481 } 482 483 static void sc27xx_adc_disable(void *_data) 484 { 485 struct sc27xx_adc_data *data = _data; 486 487 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN, 488 SC27XX_ADC_IRQ_EN, 0); 489 490 /* Disable ADC work clock and controller clock */ 491 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, 492 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); 493 494 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, 495 SC27XX_MODULE_ADC_EN, 0); 496 } 497 498 static void sc27xx_adc_free_hwlock(void *_data) 499 { 500 struct hwspinlock *hwlock = _data; 501 502 hwspin_lock_free(hwlock); 503 } 504 505 static int sc27xx_adc_probe(struct platform_device *pdev) 506 { 507 struct device_node *np = pdev->dev.of_node; 508 struct sc27xx_adc_data *sc27xx_data; 509 struct iio_dev *indio_dev; 510 int ret; 511 512 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*sc27xx_data)); 513 if (!indio_dev) 514 return -ENOMEM; 515 516 sc27xx_data = iio_priv(indio_dev); 517 518 sc27xx_data->regmap = dev_get_regmap(pdev->dev.parent, NULL); 519 if (!sc27xx_data->regmap) { 520 dev_err(&pdev->dev, "failed to get ADC regmap\n"); 521 return -ENODEV; 522 } 523 524 ret = of_property_read_u32(np, "reg", &sc27xx_data->base); 525 if (ret) { 526 dev_err(&pdev->dev, "failed to get ADC base address\n"); 527 return ret; 528 } 529 530 sc27xx_data->irq = platform_get_irq(pdev, 0); 531 if (sc27xx_data->irq < 0) { 532 dev_err(&pdev->dev, "failed to get ADC irq number\n"); 533 return sc27xx_data->irq; 534 } 535 536 ret = of_hwspin_lock_get_id(np, 0); 537 if (ret < 0) { 538 dev_err(&pdev->dev, "failed to get hwspinlock id\n"); 539 return ret; 540 } 541 542 sc27xx_data->hwlock = hwspin_lock_request_specific(ret); 543 if (!sc27xx_data->hwlock) { 544 dev_err(&pdev->dev, "failed to request hwspinlock\n"); 545 return -ENXIO; 546 } 547 548 ret = devm_add_action(&pdev->dev, sc27xx_adc_free_hwlock, 549 sc27xx_data->hwlock); 550 if (ret) { 551 sc27xx_adc_free_hwlock(sc27xx_data->hwlock); 552 dev_err(&pdev->dev, "failed to add hwspinlock action\n"); 553 return ret; 554 } 555 556 init_completion(&sc27xx_data->completion); 557 sc27xx_data->dev = &pdev->dev; 558 559 ret = sc27xx_adc_enable(sc27xx_data); 560 if (ret) { 561 dev_err(&pdev->dev, "failed to enable ADC module\n"); 562 return ret; 563 } 564 565 ret = devm_add_action(&pdev->dev, sc27xx_adc_disable, sc27xx_data); 566 if (ret) { 567 sc27xx_adc_disable(sc27xx_data); 568 dev_err(&pdev->dev, "failed to add ADC disable action\n"); 569 return ret; 570 } 571 572 ret = devm_request_threaded_irq(&pdev->dev, sc27xx_data->irq, NULL, 573 sc27xx_adc_isr, IRQF_ONESHOT, 574 pdev->name, sc27xx_data); 575 if (ret) { 576 dev_err(&pdev->dev, "failed to request ADC irq\n"); 577 return ret; 578 } 579 580 indio_dev->dev.parent = &pdev->dev; 581 indio_dev->name = dev_name(&pdev->dev); 582 indio_dev->modes = INDIO_DIRECT_MODE; 583 indio_dev->info = &sc27xx_info; 584 indio_dev->channels = sc27xx_channels; 585 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels); 586 ret = devm_iio_device_register(&pdev->dev, indio_dev); 587 if (ret) 588 dev_err(&pdev->dev, "could not register iio (ADC)"); 589 590 return ret; 591 } 592 593 static const struct of_device_id sc27xx_adc_of_match[] = { 594 { .compatible = "sprd,sc2731-adc", }, 595 { } 596 }; 597 598 static struct platform_driver sc27xx_adc_driver = { 599 .probe = sc27xx_adc_probe, 600 .driver = { 601 .name = "sc27xx-adc", 602 .of_match_table = sc27xx_adc_of_match, 603 }, 604 }; 605 606 module_platform_driver(sc27xx_adc_driver); 607 608 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>"); 609 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver"); 610 MODULE_LICENSE("GPL v2"); 611