1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Spreadtrum Communications Inc. 3 4 #include <linux/hwspinlock.h> 5 #include <linux/iio/iio.h> 6 #include <linux/module.h> 7 #include <linux/nvmem-consumer.h> 8 #include <linux/of.h> 9 #include <linux/of_device.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/slab.h> 14 15 /* PMIC global registers definition */ 16 #define SC2730_MODULE_EN 0x1808 17 #define SC2731_MODULE_EN 0xc08 18 #define SC27XX_MODULE_ADC_EN BIT(5) 19 #define SC2721_ARM_CLK_EN 0xc0c 20 #define SC2730_ARM_CLK_EN 0x180c 21 #define SC2731_ARM_CLK_EN 0xc10 22 #define SC27XX_CLK_ADC_EN BIT(5) 23 #define SC27XX_CLK_ADC_CLK_EN BIT(6) 24 25 /* ADC controller registers definition */ 26 #define SC27XX_ADC_CTL 0x0 27 #define SC27XX_ADC_CH_CFG 0x4 28 #define SC27XX_ADC_DATA 0x4c 29 #define SC27XX_ADC_INT_EN 0x50 30 #define SC27XX_ADC_INT_CLR 0x54 31 #define SC27XX_ADC_INT_STS 0x58 32 #define SC27XX_ADC_INT_RAW 0x5c 33 34 /* Bits and mask definition for SC27XX_ADC_CTL register */ 35 #define SC27XX_ADC_EN BIT(0) 36 #define SC27XX_ADC_CHN_RUN BIT(1) 37 #define SC27XX_ADC_12BIT_MODE BIT(2) 38 #define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4) 39 #define SC27XX_ADC_RUN_NUM_SHIFT 4 40 41 /* Bits and mask definition for SC27XX_ADC_CH_CFG register */ 42 #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0) 43 #define SC27XX_ADC_SCALE_MASK GENMASK(10, 9) 44 #define SC2721_ADC_SCALE_MASK BIT(5) 45 #define SC27XX_ADC_SCALE_SHIFT 9 46 #define SC2721_ADC_SCALE_SHIFT 5 47 48 /* Bits definitions for SC27XX_ADC_INT_EN registers */ 49 #define SC27XX_ADC_IRQ_EN BIT(0) 50 51 /* Bits definitions for SC27XX_ADC_INT_CLR registers */ 52 #define SC27XX_ADC_IRQ_CLR BIT(0) 53 54 /* Bits definitions for SC27XX_ADC_INT_RAW registers */ 55 #define SC27XX_ADC_IRQ_RAW BIT(0) 56 57 /* Mask definition for SC27XX_ADC_DATA register */ 58 #define SC27XX_ADC_DATA_MASK GENMASK(11, 0) 59 60 /* Timeout (ms) for the trylock of hardware spinlocks */ 61 #define SC27XX_ADC_HWLOCK_TIMEOUT 5000 62 63 /* Timeout (us) for ADC data conversion according to ADC datasheet */ 64 #define SC27XX_ADC_RDY_TIMEOUT 1000000 65 #define SC27XX_ADC_POLL_RAW_STATUS 500 66 67 /* Maximum ADC channel number */ 68 #define SC27XX_ADC_CHANNEL_MAX 32 69 70 /* ADC voltage ratio definition */ 71 #define SC27XX_VOLT_RATIO(n, d) \ 72 (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d)) 73 #define SC27XX_RATIO_NUMERATOR_OFFSET 16 74 #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0) 75 76 /* ADC specific channel reference voltage 3.5V */ 77 #define SC27XX_ADC_REFVOL_VDD35 3500000 78 79 /* ADC default channel reference voltage is 2.8V */ 80 #define SC27XX_ADC_REFVOL_VDD28 2800000 81 82 struct sc27xx_adc_data { 83 struct device *dev; 84 struct regulator *volref; 85 struct regmap *regmap; 86 /* 87 * One hardware spinlock to synchronize between the multiple 88 * subsystems which will access the unique ADC controller. 89 */ 90 struct hwspinlock *hwlock; 91 int channel_scale[SC27XX_ADC_CHANNEL_MAX]; 92 u32 base; 93 int irq; 94 const struct sc27xx_adc_variant_data *var_data; 95 }; 96 97 /* 98 * Since different PMICs of SC27xx series can have different 99 * address and ratio, we should save ratio config and base 100 * in the device data structure. 101 */ 102 struct sc27xx_adc_variant_data { 103 u32 module_en; 104 u32 clk_en; 105 u32 scale_shift; 106 u32 scale_mask; 107 const struct sc27xx_adc_linear_graph *bscale_cal; 108 const struct sc27xx_adc_linear_graph *sscale_cal; 109 void (*init_scale)(struct sc27xx_adc_data *data); 110 int (*get_ratio)(int channel, int scale); 111 bool set_volref; 112 }; 113 114 struct sc27xx_adc_linear_graph { 115 int volt0; 116 int adc0; 117 int volt1; 118 int adc1; 119 }; 120 121 /* 122 * According to the datasheet, we can convert one ADC value to one voltage value 123 * through 2 points in the linear graph. If the voltage is less than 1.2v, we 124 * should use the small-scale graph, and if more than 1.2v, we should use the 125 * big-scale graph. 126 */ 127 static struct sc27xx_adc_linear_graph big_scale_graph = { 128 4200, 3310, 129 3600, 2832, 130 }; 131 132 static struct sc27xx_adc_linear_graph small_scale_graph = { 133 1000, 3413, 134 100, 341, 135 }; 136 137 static const struct sc27xx_adc_linear_graph sc2731_big_scale_graph_calib = { 138 4200, 850, 139 3600, 728, 140 }; 141 142 static const struct sc27xx_adc_linear_graph sc2731_small_scale_graph_calib = { 143 1000, 838, 144 100, 84, 145 }; 146 147 static const struct sc27xx_adc_linear_graph big_scale_graph_calib = { 148 4200, 856, 149 3600, 733, 150 }; 151 152 static const struct sc27xx_adc_linear_graph small_scale_graph_calib = { 153 1000, 833, 154 100, 80, 155 }; 156 157 static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc) 158 { 159 return ((calib_data & 0xff) + calib_adc - 128) * 4; 160 } 161 162 /* get the adc nvmem cell calibration data */ 163 static int adc_nvmem_cell_calib_data(struct sc27xx_adc_data *data, const char *cell_name) 164 { 165 struct nvmem_cell *cell; 166 void *buf; 167 u32 origin_calib_data = 0; 168 size_t len; 169 170 if (!data) 171 return -EINVAL; 172 173 cell = nvmem_cell_get(data->dev, cell_name); 174 if (IS_ERR(cell)) 175 return PTR_ERR(cell); 176 177 buf = nvmem_cell_read(cell, &len); 178 if (IS_ERR(buf)) { 179 nvmem_cell_put(cell); 180 return PTR_ERR(buf); 181 } 182 183 memcpy(&origin_calib_data, buf, min(len, sizeof(u32))); 184 185 kfree(buf); 186 nvmem_cell_put(cell); 187 return origin_calib_data; 188 } 189 190 static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, 191 bool big_scale) 192 { 193 const struct sc27xx_adc_linear_graph *calib_graph; 194 struct sc27xx_adc_linear_graph *graph; 195 const char *cell_name; 196 u32 calib_data = 0; 197 198 if (big_scale) { 199 calib_graph = data->var_data->bscale_cal; 200 graph = &big_scale_graph; 201 cell_name = "big_scale_calib"; 202 } else { 203 calib_graph = data->var_data->sscale_cal; 204 graph = &small_scale_graph; 205 cell_name = "small_scale_calib"; 206 } 207 208 calib_data = adc_nvmem_cell_calib_data(data, cell_name); 209 210 /* Only need to calibrate the adc values in the linear graph. */ 211 graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0); 212 graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8, 213 calib_graph->adc1); 214 215 return 0; 216 } 217 218 static int sc2720_adc_get_ratio(int channel, int scale) 219 { 220 switch (channel) { 221 case 14: 222 switch (scale) { 223 case 0: 224 return SC27XX_VOLT_RATIO(68, 900); 225 case 1: 226 return SC27XX_VOLT_RATIO(68, 1760); 227 case 2: 228 return SC27XX_VOLT_RATIO(68, 2327); 229 case 3: 230 return SC27XX_VOLT_RATIO(68, 3654); 231 default: 232 return SC27XX_VOLT_RATIO(1, 1); 233 } 234 case 16: 235 switch (scale) { 236 case 0: 237 return SC27XX_VOLT_RATIO(48, 100); 238 case 1: 239 return SC27XX_VOLT_RATIO(480, 1955); 240 case 2: 241 return SC27XX_VOLT_RATIO(480, 2586); 242 case 3: 243 return SC27XX_VOLT_RATIO(48, 406); 244 default: 245 return SC27XX_VOLT_RATIO(1, 1); 246 } 247 case 21: 248 case 22: 249 case 23: 250 switch (scale) { 251 case 0: 252 return SC27XX_VOLT_RATIO(3, 8); 253 case 1: 254 return SC27XX_VOLT_RATIO(375, 1955); 255 case 2: 256 return SC27XX_VOLT_RATIO(375, 2586); 257 case 3: 258 return SC27XX_VOLT_RATIO(300, 3248); 259 default: 260 return SC27XX_VOLT_RATIO(1, 1); 261 } 262 default: 263 switch (scale) { 264 case 0: 265 return SC27XX_VOLT_RATIO(1, 1); 266 case 1: 267 return SC27XX_VOLT_RATIO(1000, 1955); 268 case 2: 269 return SC27XX_VOLT_RATIO(1000, 2586); 270 case 3: 271 return SC27XX_VOLT_RATIO(100, 406); 272 default: 273 return SC27XX_VOLT_RATIO(1, 1); 274 } 275 } 276 return SC27XX_VOLT_RATIO(1, 1); 277 } 278 279 static int sc2721_adc_get_ratio(int channel, int scale) 280 { 281 switch (channel) { 282 case 1: 283 case 2: 284 case 3: 285 case 4: 286 return scale ? SC27XX_VOLT_RATIO(400, 1025) : 287 SC27XX_VOLT_RATIO(1, 1); 288 case 5: 289 return SC27XX_VOLT_RATIO(7, 29); 290 case 7: 291 case 9: 292 return scale ? SC27XX_VOLT_RATIO(100, 125) : 293 SC27XX_VOLT_RATIO(1, 1); 294 case 14: 295 return SC27XX_VOLT_RATIO(68, 900); 296 case 16: 297 return SC27XX_VOLT_RATIO(48, 100); 298 case 19: 299 return SC27XX_VOLT_RATIO(1, 3); 300 default: 301 return SC27XX_VOLT_RATIO(1, 1); 302 } 303 return SC27XX_VOLT_RATIO(1, 1); 304 } 305 306 static int sc2730_adc_get_ratio(int channel, int scale) 307 { 308 switch (channel) { 309 case 14: 310 switch (scale) { 311 case 0: 312 return SC27XX_VOLT_RATIO(68, 900); 313 case 1: 314 return SC27XX_VOLT_RATIO(68, 1760); 315 case 2: 316 return SC27XX_VOLT_RATIO(68, 2327); 317 case 3: 318 return SC27XX_VOLT_RATIO(68, 3654); 319 default: 320 return SC27XX_VOLT_RATIO(1, 1); 321 } 322 case 15: 323 switch (scale) { 324 case 0: 325 return SC27XX_VOLT_RATIO(1, 3); 326 case 1: 327 return SC27XX_VOLT_RATIO(1000, 5865); 328 case 2: 329 return SC27XX_VOLT_RATIO(500, 3879); 330 case 3: 331 return SC27XX_VOLT_RATIO(500, 6090); 332 default: 333 return SC27XX_VOLT_RATIO(1, 1); 334 } 335 case 16: 336 switch (scale) { 337 case 0: 338 return SC27XX_VOLT_RATIO(48, 100); 339 case 1: 340 return SC27XX_VOLT_RATIO(480, 1955); 341 case 2: 342 return SC27XX_VOLT_RATIO(480, 2586); 343 case 3: 344 return SC27XX_VOLT_RATIO(48, 406); 345 default: 346 return SC27XX_VOLT_RATIO(1, 1); 347 } 348 case 21: 349 case 22: 350 case 23: 351 switch (scale) { 352 case 0: 353 return SC27XX_VOLT_RATIO(3, 8); 354 case 1: 355 return SC27XX_VOLT_RATIO(375, 1955); 356 case 2: 357 return SC27XX_VOLT_RATIO(375, 2586); 358 case 3: 359 return SC27XX_VOLT_RATIO(300, 3248); 360 default: 361 return SC27XX_VOLT_RATIO(1, 1); 362 } 363 default: 364 switch (scale) { 365 case 0: 366 return SC27XX_VOLT_RATIO(1, 1); 367 case 1: 368 return SC27XX_VOLT_RATIO(1000, 1955); 369 case 2: 370 return SC27XX_VOLT_RATIO(1000, 2586); 371 case 3: 372 return SC27XX_VOLT_RATIO(1000, 4060); 373 default: 374 return SC27XX_VOLT_RATIO(1, 1); 375 } 376 } 377 return SC27XX_VOLT_RATIO(1, 1); 378 } 379 380 static int sc2731_adc_get_ratio(int channel, int scale) 381 { 382 switch (channel) { 383 case 1: 384 case 2: 385 case 3: 386 case 4: 387 return scale ? SC27XX_VOLT_RATIO(400, 1025) : 388 SC27XX_VOLT_RATIO(1, 1); 389 case 5: 390 return SC27XX_VOLT_RATIO(7, 29); 391 case 6: 392 return SC27XX_VOLT_RATIO(375, 9000); 393 case 7: 394 case 8: 395 return scale ? SC27XX_VOLT_RATIO(100, 125) : 396 SC27XX_VOLT_RATIO(1, 1); 397 case 19: 398 return SC27XX_VOLT_RATIO(1, 3); 399 default: 400 return SC27XX_VOLT_RATIO(1, 1); 401 } 402 return SC27XX_VOLT_RATIO(1, 1); 403 } 404 405 /* 406 * According to the datasheet set specific value on some channel. 407 */ 408 static void sc2720_adc_scale_init(struct sc27xx_adc_data *data) 409 { 410 int i; 411 412 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) { 413 switch (i) { 414 case 5: 415 data->channel_scale[i] = 3; 416 break; 417 case 7: 418 case 9: 419 data->channel_scale[i] = 2; 420 break; 421 case 13: 422 data->channel_scale[i] = 1; 423 break; 424 case 19: 425 case 30: 426 case 31: 427 data->channel_scale[i] = 3; 428 break; 429 default: 430 data->channel_scale[i] = 0; 431 break; 432 } 433 } 434 } 435 436 static void sc2730_adc_scale_init(struct sc27xx_adc_data *data) 437 { 438 int i; 439 440 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) { 441 switch (i) { 442 case 5: 443 case 10: 444 case 19: 445 case 30: 446 case 31: 447 data->channel_scale[i] = 3; 448 break; 449 case 7: 450 case 9: 451 data->channel_scale[i] = 2; 452 break; 453 case 13: 454 data->channel_scale[i] = 1; 455 break; 456 default: 457 data->channel_scale[i] = 0; 458 break; 459 } 460 } 461 } 462 463 static void sc2731_adc_scale_init(struct sc27xx_adc_data *data) 464 { 465 int i; 466 /* 467 * In the current software design, SC2731 support 2 scales, 468 * channels 5 uses big scale, others use smale. 469 */ 470 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) { 471 switch (i) { 472 case 5: 473 data->channel_scale[i] = 1; 474 break; 475 default: 476 data->channel_scale[i] = 0; 477 break; 478 } 479 } 480 } 481 482 static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, 483 int scale, int *val) 484 { 485 int ret, ret_volref; 486 u32 tmp, value, status; 487 488 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT); 489 if (ret) { 490 dev_err(data->dev, "timeout to get the hwspinlock\n"); 491 return ret; 492 } 493 494 /* 495 * According to the sc2721 chip data sheet, the reference voltage of 496 * specific channel 30 and channel 31 in ADC module needs to be set from 497 * the default 2.8v to 3.5v. 498 */ 499 if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) { 500 ret = regulator_set_voltage(data->volref, 501 SC27XX_ADC_REFVOL_VDD35, 502 SC27XX_ADC_REFVOL_VDD35); 503 if (ret) { 504 dev_err(data->dev, "failed to set the volref 3.5v\n"); 505 goto unlock_adc; 506 } 507 } 508 509 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 510 SC27XX_ADC_EN, SC27XX_ADC_EN); 511 if (ret) 512 goto regulator_restore; 513 514 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, 515 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR); 516 if (ret) 517 goto disable_adc; 518 519 /* Configure the channel id and scale */ 520 tmp = (scale << data->var_data->scale_shift) & data->var_data->scale_mask; 521 tmp |= channel & SC27XX_ADC_CHN_ID_MASK; 522 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG, 523 SC27XX_ADC_CHN_ID_MASK | 524 data->var_data->scale_mask, 525 tmp); 526 if (ret) 527 goto disable_adc; 528 529 /* Select 12bit conversion mode, and only sample 1 time */ 530 tmp = SC27XX_ADC_12BIT_MODE; 531 tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK; 532 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 533 SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE, 534 tmp); 535 if (ret) 536 goto disable_adc; 537 538 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 539 SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN); 540 if (ret) 541 goto disable_adc; 542 543 ret = regmap_read_poll_timeout(data->regmap, 544 data->base + SC27XX_ADC_INT_RAW, 545 status, (status & SC27XX_ADC_IRQ_RAW), 546 SC27XX_ADC_POLL_RAW_STATUS, 547 SC27XX_ADC_RDY_TIMEOUT); 548 if (ret) { 549 dev_err(data->dev, "read adc timeout, status = 0x%x\n", status); 550 goto disable_adc; 551 } 552 553 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value); 554 if (ret) 555 goto disable_adc; 556 557 value &= SC27XX_ADC_DATA_MASK; 558 559 disable_adc: 560 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, 561 SC27XX_ADC_EN, 0); 562 regulator_restore: 563 if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) { 564 ret_volref = regulator_set_voltage(data->volref, 565 SC27XX_ADC_REFVOL_VDD28, 566 SC27XX_ADC_REFVOL_VDD28); 567 if (ret_volref) { 568 dev_err(data->dev, "failed to set the volref 2.8v,ret_volref = 0x%x\n", 569 ret_volref); 570 ret = ret || ret_volref; 571 } 572 } 573 unlock_adc: 574 hwspin_unlock_raw(data->hwlock); 575 576 if (!ret) 577 *val = value; 578 579 return ret; 580 } 581 582 static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, int channel, int scale, 583 struct u32_fract *fract) 584 { 585 u32 ratio; 586 587 ratio = data->var_data->get_ratio(channel, scale); 588 fract->numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; 589 fract->denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; 590 } 591 592 static int adc_to_volt(struct sc27xx_adc_linear_graph *graph, 593 int raw_adc) 594 { 595 int tmp; 596 597 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1); 598 tmp /= (graph->adc0 - graph->adc1); 599 tmp += graph->volt1; 600 601 return tmp; 602 } 603 604 static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, 605 int raw_adc) 606 { 607 int tmp; 608 609 tmp = adc_to_volt(graph, raw_adc); 610 611 return tmp < 0 ? 0 : tmp; 612 } 613 614 static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, 615 int scale, int raw_adc) 616 { 617 struct u32_fract fract; 618 u32 volt; 619 620 /* 621 * Convert ADC values to voltage values according to the linear graph, 622 * and channel 5 and channel 1 has been calibrated, so we can just 623 * return the voltage values calculated by the linear graph. But other 624 * channels need be calculated to the real voltage values with the 625 * voltage ratio. 626 */ 627 switch (channel) { 628 case 5: 629 return sc27xx_adc_to_volt(&big_scale_graph, raw_adc); 630 631 case 1: 632 return sc27xx_adc_to_volt(&small_scale_graph, raw_adc); 633 634 default: 635 volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc); 636 break; 637 } 638 639 sc27xx_adc_volt_ratio(data, channel, scale, &fract); 640 641 return DIV_ROUND_CLOSEST(volt * fract.denominator, fract.numerator); 642 } 643 644 static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data, 645 int channel, int scale, int *val) 646 { 647 int ret, raw_adc; 648 649 ret = sc27xx_adc_read(data, channel, scale, &raw_adc); 650 if (ret) 651 return ret; 652 653 *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc); 654 return 0; 655 } 656 657 static int sc27xx_adc_read_raw(struct iio_dev *indio_dev, 658 struct iio_chan_spec const *chan, 659 int *val, int *val2, long mask) 660 { 661 struct sc27xx_adc_data *data = iio_priv(indio_dev); 662 int scale = data->channel_scale[chan->channel]; 663 int ret, tmp; 664 665 switch (mask) { 666 case IIO_CHAN_INFO_RAW: 667 mutex_lock(&indio_dev->mlock); 668 ret = sc27xx_adc_read(data, chan->channel, scale, &tmp); 669 mutex_unlock(&indio_dev->mlock); 670 671 if (ret) 672 return ret; 673 674 *val = tmp; 675 return IIO_VAL_INT; 676 677 case IIO_CHAN_INFO_PROCESSED: 678 mutex_lock(&indio_dev->mlock); 679 ret = sc27xx_adc_read_processed(data, chan->channel, scale, 680 &tmp); 681 mutex_unlock(&indio_dev->mlock); 682 683 if (ret) 684 return ret; 685 686 *val = tmp; 687 return IIO_VAL_INT; 688 689 case IIO_CHAN_INFO_SCALE: 690 *val = scale; 691 return IIO_VAL_INT; 692 693 default: 694 return -EINVAL; 695 } 696 } 697 698 static int sc27xx_adc_write_raw(struct iio_dev *indio_dev, 699 struct iio_chan_spec const *chan, 700 int val, int val2, long mask) 701 { 702 struct sc27xx_adc_data *data = iio_priv(indio_dev); 703 704 switch (mask) { 705 case IIO_CHAN_INFO_SCALE: 706 data->channel_scale[chan->channel] = val; 707 return IIO_VAL_INT; 708 709 default: 710 return -EINVAL; 711 } 712 } 713 714 static const struct iio_info sc27xx_info = { 715 .read_raw = &sc27xx_adc_read_raw, 716 .write_raw = &sc27xx_adc_write_raw, 717 }; 718 719 #define SC27XX_ADC_CHANNEL(index, mask) { \ 720 .type = IIO_VOLTAGE, \ 721 .channel = index, \ 722 .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \ 723 .datasheet_name = "CH##index", \ 724 .indexed = 1, \ 725 } 726 727 static const struct iio_chan_spec sc27xx_channels[] = { 728 SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)), 729 SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)), 730 SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)), 731 SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)), 732 SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)), 733 SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)), 734 SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)), 735 SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)), 736 SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)), 737 SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)), 738 SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)), 739 SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)), 740 SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)), 741 SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)), 742 SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)), 743 SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)), 744 SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)), 745 SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)), 746 SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)), 747 SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)), 748 SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)), 749 SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)), 750 SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)), 751 SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)), 752 SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)), 753 SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)), 754 SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)), 755 SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)), 756 SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)), 757 SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)), 758 SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)), 759 SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)), 760 }; 761 762 static int sc27xx_adc_enable(struct sc27xx_adc_data *data) 763 { 764 int ret; 765 766 ret = regmap_update_bits(data->regmap, data->var_data->module_en, 767 SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN); 768 if (ret) 769 return ret; 770 771 /* Enable ADC work clock and controller clock */ 772 ret = regmap_update_bits(data->regmap, data->var_data->clk_en, 773 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 774 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); 775 if (ret) 776 goto disable_adc; 777 778 /* ADC channel scales' calibration from nvmem device */ 779 ret = sc27xx_adc_scale_calibration(data, true); 780 if (ret) 781 goto disable_clk; 782 783 ret = sc27xx_adc_scale_calibration(data, false); 784 if (ret) 785 goto disable_clk; 786 787 return 0; 788 789 disable_clk: 790 regmap_update_bits(data->regmap, data->var_data->clk_en, 791 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); 792 disable_adc: 793 regmap_update_bits(data->regmap, data->var_data->module_en, 794 SC27XX_MODULE_ADC_EN, 0); 795 796 return ret; 797 } 798 799 static void sc27xx_adc_disable(void *_data) 800 { 801 struct sc27xx_adc_data *data = _data; 802 803 /* Disable ADC work clock and controller clock */ 804 regmap_update_bits(data->regmap, data->var_data->clk_en, 805 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); 806 807 regmap_update_bits(data->regmap, data->var_data->module_en, 808 SC27XX_MODULE_ADC_EN, 0); 809 } 810 811 static const struct sc27xx_adc_variant_data sc2731_data = { 812 .module_en = SC2731_MODULE_EN, 813 .clk_en = SC2731_ARM_CLK_EN, 814 .scale_shift = SC27XX_ADC_SCALE_SHIFT, 815 .scale_mask = SC27XX_ADC_SCALE_MASK, 816 .bscale_cal = &sc2731_big_scale_graph_calib, 817 .sscale_cal = &sc2731_small_scale_graph_calib, 818 .init_scale = sc2731_adc_scale_init, 819 .get_ratio = sc2731_adc_get_ratio, 820 .set_volref = false, 821 }; 822 823 static const struct sc27xx_adc_variant_data sc2730_data = { 824 .module_en = SC2730_MODULE_EN, 825 .clk_en = SC2730_ARM_CLK_EN, 826 .scale_shift = SC27XX_ADC_SCALE_SHIFT, 827 .scale_mask = SC27XX_ADC_SCALE_MASK, 828 .bscale_cal = &big_scale_graph_calib, 829 .sscale_cal = &small_scale_graph_calib, 830 .init_scale = sc2730_adc_scale_init, 831 .get_ratio = sc2730_adc_get_ratio, 832 .set_volref = false, 833 }; 834 835 static const struct sc27xx_adc_variant_data sc2721_data = { 836 .module_en = SC2731_MODULE_EN, 837 .clk_en = SC2721_ARM_CLK_EN, 838 .scale_shift = SC2721_ADC_SCALE_SHIFT, 839 .scale_mask = SC2721_ADC_SCALE_MASK, 840 .bscale_cal = &sc2731_big_scale_graph_calib, 841 .sscale_cal = &sc2731_small_scale_graph_calib, 842 .init_scale = sc2731_adc_scale_init, 843 .get_ratio = sc2721_adc_get_ratio, 844 .set_volref = true, 845 }; 846 847 static const struct sc27xx_adc_variant_data sc2720_data = { 848 .module_en = SC2731_MODULE_EN, 849 .clk_en = SC2721_ARM_CLK_EN, 850 .scale_shift = SC27XX_ADC_SCALE_SHIFT, 851 .scale_mask = SC27XX_ADC_SCALE_MASK, 852 .bscale_cal = &big_scale_graph_calib, 853 .sscale_cal = &small_scale_graph_calib, 854 .init_scale = sc2720_adc_scale_init, 855 .get_ratio = sc2720_adc_get_ratio, 856 .set_volref = false, 857 }; 858 859 static int sc27xx_adc_probe(struct platform_device *pdev) 860 { 861 struct device *dev = &pdev->dev; 862 struct device_node *np = dev->of_node; 863 struct sc27xx_adc_data *sc27xx_data; 864 const struct sc27xx_adc_variant_data *pdata; 865 struct iio_dev *indio_dev; 866 int ret; 867 868 pdata = of_device_get_match_data(dev); 869 if (!pdata) { 870 dev_err(dev, "No matching driver data found\n"); 871 return -EINVAL; 872 } 873 874 indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data)); 875 if (!indio_dev) 876 return -ENOMEM; 877 878 sc27xx_data = iio_priv(indio_dev); 879 880 sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL); 881 if (!sc27xx_data->regmap) { 882 dev_err(dev, "failed to get ADC regmap\n"); 883 return -ENODEV; 884 } 885 886 ret = of_property_read_u32(np, "reg", &sc27xx_data->base); 887 if (ret) { 888 dev_err(dev, "failed to get ADC base address\n"); 889 return ret; 890 } 891 892 sc27xx_data->irq = platform_get_irq(pdev, 0); 893 if (sc27xx_data->irq < 0) 894 return sc27xx_data->irq; 895 896 ret = of_hwspin_lock_get_id(np, 0); 897 if (ret < 0) { 898 dev_err(dev, "failed to get hwspinlock id\n"); 899 return ret; 900 } 901 902 sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 903 if (!sc27xx_data->hwlock) { 904 dev_err(dev, "failed to request hwspinlock\n"); 905 return -ENXIO; 906 } 907 908 sc27xx_data->dev = dev; 909 if (pdata->set_volref) { 910 sc27xx_data->volref = devm_regulator_get(dev, "vref"); 911 if (IS_ERR(sc27xx_data->volref)) { 912 ret = PTR_ERR(sc27xx_data->volref); 913 return dev_err_probe(dev, ret, "failed to get ADC volref\n"); 914 } 915 } 916 917 sc27xx_data->var_data = pdata; 918 sc27xx_data->var_data->init_scale(sc27xx_data); 919 920 ret = sc27xx_adc_enable(sc27xx_data); 921 if (ret) { 922 dev_err(dev, "failed to enable ADC module\n"); 923 return ret; 924 } 925 926 ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data); 927 if (ret) { 928 dev_err(dev, "failed to add ADC disable action\n"); 929 return ret; 930 } 931 932 indio_dev->name = dev_name(dev); 933 indio_dev->modes = INDIO_DIRECT_MODE; 934 indio_dev->info = &sc27xx_info; 935 indio_dev->channels = sc27xx_channels; 936 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels); 937 ret = devm_iio_device_register(dev, indio_dev); 938 if (ret) 939 dev_err(dev, "could not register iio (ADC)"); 940 941 return ret; 942 } 943 944 static const struct of_device_id sc27xx_adc_of_match[] = { 945 { .compatible = "sprd,sc2731-adc", .data = &sc2731_data}, 946 { .compatible = "sprd,sc2730-adc", .data = &sc2730_data}, 947 { .compatible = "sprd,sc2721-adc", .data = &sc2721_data}, 948 { .compatible = "sprd,sc2720-adc", .data = &sc2720_data}, 949 { } 950 }; 951 MODULE_DEVICE_TABLE(of, sc27xx_adc_of_match); 952 953 static struct platform_driver sc27xx_adc_driver = { 954 .probe = sc27xx_adc_probe, 955 .driver = { 956 .name = "sc27xx-adc", 957 .of_match_table = sc27xx_adc_of_match, 958 }, 959 }; 960 961 module_platform_driver(sc27xx_adc_driver); 962 963 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>"); 964 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver"); 965 MODULE_LICENSE("GPL v2"); 966