1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G2L A/D Converter driver 4 * 5 * Copyright (c) 2021 Renesas Electronics Europe GmbH 6 * 7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/delay.h> 14 #include <linux/iio/iio.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 #include <linux/reset.h> 23 24 #define DRIVER_NAME "rzg2l-adc" 25 26 #define RZG2L_ADM(n) ((n) * 0x4) 27 #define RZG2L_ADM0_ADCE BIT(0) 28 #define RZG2L_ADM0_ADBSY BIT(1) 29 #define RZG2L_ADM0_PWDWNB BIT(2) 30 #define RZG2L_ADM0_SRESB BIT(15) 31 #define RZG2L_ADM1_TRG BIT(0) 32 #define RZG2L_ADM1_MS BIT(2) 33 #define RZG2L_ADM1_BS BIT(4) 34 #define RZG2L_ADM1_EGA_MASK GENMASK(13, 12) 35 #define RZG2L_ADM2_CHSEL_MASK GENMASK(7, 0) 36 #define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24) 37 #define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16) 38 #define RZG2L_ADM3_ADCMP_E FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, 0xe) 39 #define RZG2L_ADM3_ADSMP_MASK GENMASK(15, 0) 40 41 #define RZG2L_ADINT 0x20 42 #define RZG2L_ADINT_INTEN_MASK GENMASK(7, 0) 43 #define RZG2L_ADINT_CSEEN BIT(16) 44 #define RZG2L_ADINT_INTS BIT(31) 45 46 #define RZG2L_ADSTS 0x24 47 #define RZG2L_ADSTS_CSEST BIT(16) 48 #define RZG2L_ADSTS_INTST_MASK GENMASK(7, 0) 49 50 #define RZG2L_ADIVC 0x28 51 #define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0) 52 #define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4) 53 54 #define RZG2L_ADFIL 0x2c 55 56 #define RZG2L_ADCR(n) (0x30 + ((n) * 0x4)) 57 #define RZG2L_ADCR_AD_MASK GENMASK(11, 0) 58 59 #define RZG2L_ADSMP_DEFAULT_SAMPLING 0x578 60 61 #define RZG2L_ADC_MAX_CHANNELS 8 62 #define RZG2L_ADC_CHN_MASK 0x7 63 #define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4) 64 65 struct rzg2l_adc_data { 66 const struct iio_chan_spec *channels; 67 u8 num_channels; 68 }; 69 70 struct rzg2l_adc { 71 void __iomem *base; 72 struct clk *pclk; 73 struct clk *adclk; 74 struct reset_control *presetn; 75 struct reset_control *adrstn; 76 struct completion completion; 77 const struct rzg2l_adc_data *data; 78 struct mutex lock; 79 u16 last_val[RZG2L_ADC_MAX_CHANNELS]; 80 }; 81 82 static const char * const rzg2l_adc_channel_name[] = { 83 "adc0", 84 "adc1", 85 "adc2", 86 "adc3", 87 "adc4", 88 "adc5", 89 "adc6", 90 "adc7", 91 }; 92 93 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg) 94 { 95 return readl(adc->base + reg); 96 } 97 98 static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val) 99 { 100 writel(val, adc->base + reg); 101 } 102 103 static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on) 104 { 105 u32 reg; 106 107 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); 108 if (on) 109 reg |= RZG2L_ADM0_PWDWNB; 110 else 111 reg &= ~RZG2L_ADM0_PWDWNB; 112 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); 113 udelay(2); 114 } 115 116 static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start) 117 { 118 int timeout = 5; 119 u32 reg; 120 121 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); 122 if (start) 123 reg |= RZG2L_ADM0_ADCE; 124 else 125 reg &= ~RZG2L_ADM0_ADCE; 126 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); 127 128 if (start) 129 return; 130 131 do { 132 usleep_range(100, 200); 133 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); 134 timeout--; 135 if (!timeout) { 136 pr_err("%s stopping ADC timed out\n", __func__); 137 break; 138 } 139 } while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE))); 140 } 141 142 static void rzg2l_set_trigger(struct rzg2l_adc *adc) 143 { 144 u32 reg; 145 146 /* 147 * Setup ADM1 for SW trigger 148 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid 149 * BS[4] - Enable 1-buffer mode 150 * MS[1] - Enable Select mode 151 * TRG[0] - Enable software trigger mode 152 */ 153 reg = rzg2l_adc_readl(adc, RZG2L_ADM(1)); 154 reg &= ~RZG2L_ADM1_EGA_MASK; 155 reg &= ~RZG2L_ADM1_BS; 156 reg &= ~RZG2L_ADM1_TRG; 157 reg |= RZG2L_ADM1_MS; 158 rzg2l_adc_writel(adc, RZG2L_ADM(1), reg); 159 } 160 161 static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch) 162 { 163 u32 reg; 164 165 if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY) 166 return -EBUSY; 167 168 rzg2l_set_trigger(adc); 169 170 /* Select analog input channel subjected to conversion. */ 171 reg = rzg2l_adc_readl(adc, RZG2L_ADM(2)); 172 reg &= ~RZG2L_ADM2_CHSEL_MASK; 173 reg |= BIT(ch); 174 rzg2l_adc_writel(adc, RZG2L_ADM(2), reg); 175 176 /* 177 * Setup ADINT 178 * INTS[31] - Select pulse signal 179 * CSEEN[16] - Enable channel select error interrupt 180 * INTEN[7:0] - Select channel interrupt 181 */ 182 reg = rzg2l_adc_readl(adc, RZG2L_ADINT); 183 reg &= ~RZG2L_ADINT_INTS; 184 reg &= ~RZG2L_ADINT_INTEN_MASK; 185 reg |= (RZG2L_ADINT_CSEEN | BIT(ch)); 186 rzg2l_adc_writel(adc, RZG2L_ADINT, reg); 187 188 return 0; 189 } 190 191 static int rzg2l_adc_set_power(struct iio_dev *indio_dev, bool on) 192 { 193 struct device *dev = indio_dev->dev.parent; 194 195 if (on) 196 return pm_runtime_resume_and_get(dev); 197 198 return pm_runtime_put_sync(dev); 199 } 200 201 static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch) 202 { 203 int ret; 204 205 ret = rzg2l_adc_set_power(indio_dev, true); 206 if (ret) 207 return ret; 208 209 ret = rzg2l_adc_conversion_setup(adc, ch); 210 if (ret) { 211 rzg2l_adc_set_power(indio_dev, false); 212 return ret; 213 } 214 215 reinit_completion(&adc->completion); 216 217 rzg2l_adc_start_stop(adc, true); 218 219 if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) { 220 rzg2l_adc_writel(adc, RZG2L_ADINT, 221 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK); 222 rzg2l_adc_start_stop(adc, false); 223 rzg2l_adc_set_power(indio_dev, false); 224 return -ETIMEDOUT; 225 } 226 227 return rzg2l_adc_set_power(indio_dev, false); 228 } 229 230 static int rzg2l_adc_read_raw(struct iio_dev *indio_dev, 231 struct iio_chan_spec const *chan, 232 int *val, int *val2, long mask) 233 { 234 struct rzg2l_adc *adc = iio_priv(indio_dev); 235 int ret; 236 u8 ch; 237 238 switch (mask) { 239 case IIO_CHAN_INFO_RAW: 240 if (chan->type != IIO_VOLTAGE) 241 return -EINVAL; 242 243 mutex_lock(&adc->lock); 244 ch = chan->channel & RZG2L_ADC_CHN_MASK; 245 ret = rzg2l_adc_conversion(indio_dev, adc, ch); 246 if (ret) { 247 mutex_unlock(&adc->lock); 248 return ret; 249 } 250 *val = adc->last_val[ch]; 251 mutex_unlock(&adc->lock); 252 253 return IIO_VAL_INT; 254 255 default: 256 return -EINVAL; 257 } 258 } 259 260 static int rzg2l_adc_read_label(struct iio_dev *iio_dev, 261 const struct iio_chan_spec *chan, 262 char *label) 263 { 264 return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]); 265 } 266 267 static const struct iio_info rzg2l_adc_iio_info = { 268 .read_raw = rzg2l_adc_read_raw, 269 .read_label = rzg2l_adc_read_label, 270 }; 271 272 static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id) 273 { 274 struct rzg2l_adc *adc = dev_id; 275 unsigned long intst; 276 u32 reg; 277 int ch; 278 279 reg = rzg2l_adc_readl(adc, RZG2L_ADSTS); 280 281 /* A/D conversion channel select error interrupt */ 282 if (reg & RZG2L_ADSTS_CSEST) { 283 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg); 284 return IRQ_HANDLED; 285 } 286 287 intst = reg & RZG2L_ADSTS_INTST_MASK; 288 if (!intst) 289 return IRQ_NONE; 290 291 for_each_set_bit(ch, &intst, RZG2L_ADC_MAX_CHANNELS) 292 adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK; 293 294 /* clear the channel interrupt */ 295 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg); 296 297 complete(&adc->completion); 298 299 return IRQ_HANDLED; 300 } 301 302 static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc) 303 { 304 struct iio_chan_spec *chan_array; 305 struct fwnode_handle *fwnode; 306 struct rzg2l_adc_data *data; 307 unsigned int channel; 308 int num_channels; 309 int ret; 310 u8 i; 311 312 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 313 if (!data) 314 return -ENOMEM; 315 316 num_channels = device_get_child_node_count(&pdev->dev); 317 if (!num_channels) { 318 dev_err(&pdev->dev, "no channel children\n"); 319 return -ENODEV; 320 } 321 322 if (num_channels > RZG2L_ADC_MAX_CHANNELS) { 323 dev_err(&pdev->dev, "num of channel children out of range\n"); 324 return -EINVAL; 325 } 326 327 chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array), 328 GFP_KERNEL); 329 if (!chan_array) 330 return -ENOMEM; 331 332 i = 0; 333 device_for_each_child_node(&pdev->dev, fwnode) { 334 ret = fwnode_property_read_u32(fwnode, "reg", &channel); 335 if (ret) { 336 fwnode_handle_put(fwnode); 337 return ret; 338 } 339 340 if (channel >= RZG2L_ADC_MAX_CHANNELS) { 341 fwnode_handle_put(fwnode); 342 return -EINVAL; 343 } 344 345 chan_array[i].type = IIO_VOLTAGE; 346 chan_array[i].indexed = 1; 347 chan_array[i].channel = channel; 348 chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 349 chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel]; 350 i++; 351 } 352 353 data->num_channels = num_channels; 354 data->channels = chan_array; 355 adc->data = data; 356 357 return 0; 358 } 359 360 static int rzg2l_adc_hw_init(struct rzg2l_adc *adc) 361 { 362 int timeout = 5; 363 u32 reg; 364 int ret; 365 366 ret = clk_prepare_enable(adc->pclk); 367 if (ret) 368 return ret; 369 370 /* SW reset */ 371 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); 372 reg |= RZG2L_ADM0_SRESB; 373 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); 374 375 while (!(rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_SRESB)) { 376 if (!timeout) { 377 ret = -EBUSY; 378 goto exit_hw_init; 379 } 380 timeout--; 381 usleep_range(100, 200); 382 } 383 384 /* Only division by 4 can be set */ 385 reg = rzg2l_adc_readl(adc, RZG2L_ADIVC); 386 reg &= ~RZG2L_ADIVC_DIVADC_MASK; 387 reg |= RZG2L_ADIVC_DIVADC_4; 388 rzg2l_adc_writel(adc, RZG2L_ADIVC, reg); 389 390 /* 391 * Setup AMD3 392 * ADIL[31:24] - Should be always set to 0 393 * ADCMP[23:16] - Should be always set to 0xe 394 * ADSMP[15:0] - Set default (0x578) sampling period 395 */ 396 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3)); 397 reg &= ~RZG2L_ADM3_ADIL_MASK; 398 reg &= ~RZG2L_ADM3_ADCMP_MASK; 399 reg &= ~RZG2L_ADM3_ADSMP_MASK; 400 reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFAULT_SAMPLING); 401 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg); 402 403 exit_hw_init: 404 clk_disable_unprepare(adc->pclk); 405 406 return ret; 407 } 408 409 static void rzg2l_adc_pm_runtime_disable(void *data) 410 { 411 struct device *dev = data; 412 413 pm_runtime_disable(dev->parent); 414 } 415 416 static void rzg2l_adc_pm_runtime_set_suspended(void *data) 417 { 418 struct device *dev = data; 419 420 pm_runtime_set_suspended(dev->parent); 421 } 422 423 static void rzg2l_adc_reset_assert(void *data) 424 { 425 reset_control_assert(data); 426 } 427 428 static int rzg2l_adc_probe(struct platform_device *pdev) 429 { 430 struct device *dev = &pdev->dev; 431 struct iio_dev *indio_dev; 432 struct rzg2l_adc *adc; 433 int ret; 434 int irq; 435 436 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 437 if (!indio_dev) 438 return -ENOMEM; 439 440 adc = iio_priv(indio_dev); 441 442 ret = rzg2l_adc_parse_properties(pdev, adc); 443 if (ret) 444 return ret; 445 446 mutex_init(&adc->lock); 447 448 adc->base = devm_platform_ioremap_resource(pdev, 0); 449 if (IS_ERR(adc->base)) 450 return PTR_ERR(adc->base); 451 452 adc->pclk = devm_clk_get(dev, "pclk"); 453 if (IS_ERR(adc->pclk)) { 454 dev_err(dev, "Failed to get pclk"); 455 return PTR_ERR(adc->pclk); 456 } 457 458 adc->adclk = devm_clk_get(dev, "adclk"); 459 if (IS_ERR(adc->adclk)) { 460 dev_err(dev, "Failed to get adclk"); 461 return PTR_ERR(adc->adclk); 462 } 463 464 adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n"); 465 if (IS_ERR(adc->adrstn)) { 466 dev_err(dev, "failed to get adrstn\n"); 467 return PTR_ERR(adc->adrstn); 468 } 469 470 adc->presetn = devm_reset_control_get_exclusive(dev, "presetn"); 471 if (IS_ERR(adc->presetn)) { 472 dev_err(dev, "failed to get presetn\n"); 473 return PTR_ERR(adc->presetn); 474 } 475 476 ret = reset_control_deassert(adc->adrstn); 477 if (ret) { 478 dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret); 479 return ret; 480 } 481 482 ret = devm_add_action_or_reset(&pdev->dev, 483 rzg2l_adc_reset_assert, adc->adrstn); 484 if (ret) { 485 dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n", 486 ret); 487 return ret; 488 } 489 490 ret = reset_control_deassert(adc->presetn); 491 if (ret) { 492 dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret); 493 return ret; 494 } 495 496 ret = devm_add_action_or_reset(&pdev->dev, 497 rzg2l_adc_reset_assert, adc->presetn); 498 if (ret) { 499 dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n", 500 ret); 501 return ret; 502 } 503 504 ret = rzg2l_adc_hw_init(adc); 505 if (ret) { 506 dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret); 507 return ret; 508 } 509 510 irq = platform_get_irq(pdev, 0); 511 if (irq < 0) 512 return irq; 513 514 ret = devm_request_irq(dev, irq, rzg2l_adc_isr, 515 0, dev_name(dev), adc); 516 if (ret < 0) 517 return ret; 518 519 init_completion(&adc->completion); 520 521 platform_set_drvdata(pdev, indio_dev); 522 523 indio_dev->name = DRIVER_NAME; 524 indio_dev->info = &rzg2l_adc_iio_info; 525 indio_dev->modes = INDIO_DIRECT_MODE; 526 indio_dev->channels = adc->data->channels; 527 indio_dev->num_channels = adc->data->num_channels; 528 529 pm_runtime_set_suspended(dev); 530 ret = devm_add_action_or_reset(&pdev->dev, 531 rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev); 532 if (ret) 533 return ret; 534 535 pm_runtime_enable(dev); 536 ret = devm_add_action_or_reset(&pdev->dev, 537 rzg2l_adc_pm_runtime_disable, &indio_dev->dev); 538 if (ret) 539 return ret; 540 541 return devm_iio_device_register(dev, indio_dev); 542 } 543 544 static const struct of_device_id rzg2l_adc_match[] = { 545 { .compatible = "renesas,rzg2l-adc",}, 546 { /* sentinel */ } 547 }; 548 MODULE_DEVICE_TABLE(of, rzg2l_adc_match); 549 550 static int __maybe_unused rzg2l_adc_pm_runtime_suspend(struct device *dev) 551 { 552 struct iio_dev *indio_dev = dev_get_drvdata(dev); 553 struct rzg2l_adc *adc = iio_priv(indio_dev); 554 555 rzg2l_adc_pwr(adc, false); 556 clk_disable_unprepare(adc->adclk); 557 clk_disable_unprepare(adc->pclk); 558 559 return 0; 560 } 561 562 static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev) 563 { 564 struct iio_dev *indio_dev = dev_get_drvdata(dev); 565 struct rzg2l_adc *adc = iio_priv(indio_dev); 566 int ret; 567 568 ret = clk_prepare_enable(adc->pclk); 569 if (ret) 570 return ret; 571 572 ret = clk_prepare_enable(adc->adclk); 573 if (ret) { 574 clk_disable_unprepare(adc->pclk); 575 return ret; 576 } 577 578 rzg2l_adc_pwr(adc, true); 579 580 return 0; 581 } 582 583 static const struct dev_pm_ops rzg2l_adc_pm_ops = { 584 SET_RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend, 585 rzg2l_adc_pm_runtime_resume, 586 NULL) 587 }; 588 589 static struct platform_driver rzg2l_adc_driver = { 590 .probe = rzg2l_adc_probe, 591 .driver = { 592 .name = DRIVER_NAME, 593 .of_match_table = rzg2l_adc_match, 594 .pm = &rzg2l_adc_pm_ops, 595 }, 596 }; 597 598 module_platform_driver(rzg2l_adc_driver); 599 600 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 601 MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver"); 602 MODULE_LICENSE("GPL v2"); 603