1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip Successive Approximation Register (SAR) A/D Converter 4 * Copyright (C) 2014 ROCKCHIP, Inc. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/module.h> 9 #include <linux/mutex.h> 10 #include <linux/platform_device.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/clk.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/reset.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/trigger_consumer.h> 23 #include <linux/iio/triggered_buffer.h> 24 25 #define SARADC_DATA 0x00 26 27 #define SARADC_STAS 0x04 28 #define SARADC_STAS_BUSY BIT(0) 29 30 #define SARADC_CTRL 0x08 31 #define SARADC_CTRL_IRQ_STATUS BIT(6) 32 #define SARADC_CTRL_IRQ_ENABLE BIT(5) 33 #define SARADC_CTRL_POWER_CTRL BIT(3) 34 #define SARADC_CTRL_CHN_MASK 0x7 35 36 #define SARADC_DLY_PU_SOC 0x0c 37 #define SARADC_DLY_PU_SOC_MASK 0x3f 38 39 #define SARADC_TIMEOUT msecs_to_jiffies(100) 40 #define SARADC_MAX_CHANNELS 8 41 42 /* v2 registers */ 43 #define SARADC2_CONV_CON 0x000 44 #define SARADC_T_PD_SOC 0x004 45 #define SARADC_T_DAS_SOC 0x00c 46 #define SARADC2_END_INT_EN 0x104 47 #define SARADC2_ST_CON 0x108 48 #define SARADC2_STATUS 0x10c 49 #define SARADC2_END_INT_ST 0x110 50 #define SARADC2_DATA_BASE 0x120 51 52 #define SARADC2_EN_END_INT BIT(0) 53 #define SARADC2_START BIT(4) 54 #define SARADC2_SINGLE_MODE BIT(5) 55 56 #define SARADC2_CONV_CHANNELS GENMASK(15, 0) 57 58 struct rockchip_saradc; 59 60 struct rockchip_saradc_data { 61 const struct iio_chan_spec *channels; 62 int num_channels; 63 unsigned long clk_rate; 64 void (*start)(struct rockchip_saradc *info, int chn); 65 int (*read)(struct rockchip_saradc *info); 66 void (*power_down)(struct rockchip_saradc *info); 67 }; 68 69 struct rockchip_saradc { 70 void __iomem *regs; 71 struct clk *pclk; 72 struct clk *clk; 73 struct completion completion; 74 struct regulator *vref; 75 /* lock to protect against multiple access to the device */ 76 struct mutex lock; 77 int uv_vref; 78 struct reset_control *reset; 79 const struct rockchip_saradc_data *data; 80 u16 last_val; 81 const struct iio_chan_spec *last_chan; 82 struct notifier_block nb; 83 }; 84 85 static void rockchip_saradc_reset_controller(struct reset_control *reset); 86 87 static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn) 88 { 89 /* 8 clock periods as delay between power up and start cmd */ 90 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); 91 /* Select the channel to be used and trigger conversion */ 92 writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) | 93 SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL); 94 } 95 96 static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn) 97 { 98 int val; 99 100 if (info->reset) 101 rockchip_saradc_reset_controller(info->reset); 102 103 writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC); 104 writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC); 105 val = FIELD_PREP(SARADC2_EN_END_INT, 1); 106 val |= val << 16; 107 writel_relaxed(val, info->regs + SARADC2_END_INT_EN); 108 val = FIELD_PREP(SARADC2_START, 1) | 109 FIELD_PREP(SARADC2_SINGLE_MODE, 1) | 110 FIELD_PREP(SARADC2_CONV_CHANNELS, chn); 111 val |= val << 16; 112 writel(val, info->regs + SARADC2_CONV_CON); 113 } 114 115 static void rockchip_saradc_start(struct rockchip_saradc *info, int chn) 116 { 117 info->data->start(info, chn); 118 } 119 120 static int rockchip_saradc_read_v1(struct rockchip_saradc *info) 121 { 122 return readl_relaxed(info->regs + SARADC_DATA); 123 } 124 125 static int rockchip_saradc_read_v2(struct rockchip_saradc *info) 126 { 127 int offset; 128 129 /* Clear irq */ 130 writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST); 131 132 offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4; 133 134 return readl_relaxed(info->regs + offset); 135 } 136 137 static int rockchip_saradc_read(struct rockchip_saradc *info) 138 { 139 return info->data->read(info); 140 } 141 142 static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info) 143 { 144 writel_relaxed(0, info->regs + SARADC_CTRL); 145 } 146 147 static void rockchip_saradc_power_down(struct rockchip_saradc *info) 148 { 149 if (info->data->power_down) 150 info->data->power_down(info); 151 } 152 153 static int rockchip_saradc_conversion(struct rockchip_saradc *info, 154 struct iio_chan_spec const *chan) 155 { 156 reinit_completion(&info->completion); 157 158 info->last_chan = chan; 159 rockchip_saradc_start(info, chan->channel); 160 161 if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT)) 162 return -ETIMEDOUT; 163 164 return 0; 165 } 166 167 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev, 168 struct iio_chan_spec const *chan, 169 int *val, int *val2, long mask) 170 { 171 struct rockchip_saradc *info = iio_priv(indio_dev); 172 int ret; 173 174 switch (mask) { 175 case IIO_CHAN_INFO_RAW: 176 mutex_lock(&info->lock); 177 178 ret = rockchip_saradc_conversion(info, chan); 179 if (ret) { 180 rockchip_saradc_power_down(info); 181 mutex_unlock(&info->lock); 182 return ret; 183 } 184 185 *val = info->last_val; 186 mutex_unlock(&info->lock); 187 return IIO_VAL_INT; 188 case IIO_CHAN_INFO_SCALE: 189 *val = info->uv_vref / 1000; 190 *val2 = chan->scan_type.realbits; 191 return IIO_VAL_FRACTIONAL_LOG2; 192 default: 193 return -EINVAL; 194 } 195 } 196 197 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id) 198 { 199 struct rockchip_saradc *info = dev_id; 200 201 /* Read value */ 202 info->last_val = rockchip_saradc_read(info); 203 info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0); 204 205 rockchip_saradc_power_down(info); 206 207 complete(&info->completion); 208 209 return IRQ_HANDLED; 210 } 211 212 static const struct iio_info rockchip_saradc_iio_info = { 213 .read_raw = rockchip_saradc_read_raw, 214 }; 215 216 #define SARADC_CHANNEL(_index, _id, _res) { \ 217 .type = IIO_VOLTAGE, \ 218 .indexed = 1, \ 219 .channel = _index, \ 220 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 221 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 222 .datasheet_name = _id, \ 223 .scan_index = _index, \ 224 .scan_type = { \ 225 .sign = 'u', \ 226 .realbits = _res, \ 227 .storagebits = 16, \ 228 .endianness = IIO_CPU, \ 229 }, \ 230 } 231 232 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = { 233 SARADC_CHANNEL(0, "adc0", 10), 234 SARADC_CHANNEL(1, "adc1", 10), 235 SARADC_CHANNEL(2, "adc2", 10), 236 }; 237 238 static const struct rockchip_saradc_data saradc_data = { 239 .channels = rockchip_saradc_iio_channels, 240 .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels), 241 .clk_rate = 1000000, 242 .start = rockchip_saradc_start_v1, 243 .read = rockchip_saradc_read_v1, 244 .power_down = rockchip_saradc_power_down_v1, 245 }; 246 247 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = { 248 SARADC_CHANNEL(0, "adc0", 12), 249 SARADC_CHANNEL(1, "adc1", 12), 250 }; 251 252 static const struct rockchip_saradc_data rk3066_tsadc_data = { 253 .channels = rockchip_rk3066_tsadc_iio_channels, 254 .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels), 255 .clk_rate = 50000, 256 .start = rockchip_saradc_start_v1, 257 .read = rockchip_saradc_read_v1, 258 .power_down = rockchip_saradc_power_down_v1, 259 }; 260 261 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = { 262 SARADC_CHANNEL(0, "adc0", 10), 263 SARADC_CHANNEL(1, "adc1", 10), 264 SARADC_CHANNEL(2, "adc2", 10), 265 SARADC_CHANNEL(3, "adc3", 10), 266 SARADC_CHANNEL(4, "adc4", 10), 267 SARADC_CHANNEL(5, "adc5", 10), 268 }; 269 270 static const struct rockchip_saradc_data rk3399_saradc_data = { 271 .channels = rockchip_rk3399_saradc_iio_channels, 272 .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels), 273 .clk_rate = 1000000, 274 .start = rockchip_saradc_start_v1, 275 .read = rockchip_saradc_read_v1, 276 .power_down = rockchip_saradc_power_down_v1, 277 }; 278 279 static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = { 280 SARADC_CHANNEL(0, "adc0", 10), 281 SARADC_CHANNEL(1, "adc1", 10), 282 SARADC_CHANNEL(2, "adc2", 10), 283 SARADC_CHANNEL(3, "adc3", 10), 284 SARADC_CHANNEL(4, "adc4", 10), 285 SARADC_CHANNEL(5, "adc5", 10), 286 SARADC_CHANNEL(6, "adc6", 10), 287 SARADC_CHANNEL(7, "adc7", 10), 288 }; 289 290 static const struct rockchip_saradc_data rk3568_saradc_data = { 291 .channels = rockchip_rk3568_saradc_iio_channels, 292 .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels), 293 .clk_rate = 1000000, 294 .start = rockchip_saradc_start_v1, 295 .read = rockchip_saradc_read_v1, 296 .power_down = rockchip_saradc_power_down_v1, 297 }; 298 299 static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = { 300 SARADC_CHANNEL(0, "adc0", 12), 301 SARADC_CHANNEL(1, "adc1", 12), 302 SARADC_CHANNEL(2, "adc2", 12), 303 SARADC_CHANNEL(3, "adc3", 12), 304 SARADC_CHANNEL(4, "adc4", 12), 305 SARADC_CHANNEL(5, "adc5", 12), 306 SARADC_CHANNEL(6, "adc6", 12), 307 SARADC_CHANNEL(7, "adc7", 12), 308 }; 309 310 static const struct rockchip_saradc_data rk3588_saradc_data = { 311 .channels = rockchip_rk3588_saradc_iio_channels, 312 .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels), 313 .clk_rate = 1000000, 314 .start = rockchip_saradc_start_v2, 315 .read = rockchip_saradc_read_v2, 316 }; 317 318 static const struct of_device_id rockchip_saradc_match[] = { 319 { 320 .compatible = "rockchip,saradc", 321 .data = &saradc_data, 322 }, { 323 .compatible = "rockchip,rk3066-tsadc", 324 .data = &rk3066_tsadc_data, 325 }, { 326 .compatible = "rockchip,rk3399-saradc", 327 .data = &rk3399_saradc_data, 328 }, { 329 .compatible = "rockchip,rk3568-saradc", 330 .data = &rk3568_saradc_data, 331 }, { 332 .compatible = "rockchip,rk3588-saradc", 333 .data = &rk3588_saradc_data, 334 }, 335 {}, 336 }; 337 MODULE_DEVICE_TABLE(of, rockchip_saradc_match); 338 339 /* 340 * Reset SARADC Controller. 341 */ 342 static void rockchip_saradc_reset_controller(struct reset_control *reset) 343 { 344 reset_control_assert(reset); 345 usleep_range(10, 20); 346 reset_control_deassert(reset); 347 } 348 349 static void rockchip_saradc_regulator_disable(void *data) 350 { 351 struct rockchip_saradc *info = data; 352 353 regulator_disable(info->vref); 354 } 355 356 static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p) 357 { 358 struct iio_poll_func *pf = p; 359 struct iio_dev *i_dev = pf->indio_dev; 360 struct rockchip_saradc *info = iio_priv(i_dev); 361 /* 362 * @values: each channel takes an u16 value 363 * @timestamp: will be 8-byte aligned automatically 364 */ 365 struct { 366 u16 values[SARADC_MAX_CHANNELS]; 367 int64_t timestamp; 368 } data; 369 int ret; 370 int i, j = 0; 371 372 mutex_lock(&info->lock); 373 374 for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) { 375 const struct iio_chan_spec *chan = &i_dev->channels[i]; 376 377 ret = rockchip_saradc_conversion(info, chan); 378 if (ret) { 379 rockchip_saradc_power_down(info); 380 goto out; 381 } 382 383 data.values[j] = info->last_val; 384 j++; 385 } 386 387 iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev)); 388 out: 389 mutex_unlock(&info->lock); 390 391 iio_trigger_notify_done(i_dev->trig); 392 393 return IRQ_HANDLED; 394 } 395 396 static int rockchip_saradc_volt_notify(struct notifier_block *nb, 397 unsigned long event, void *data) 398 { 399 struct rockchip_saradc *info = 400 container_of(nb, struct rockchip_saradc, nb); 401 402 if (event & REGULATOR_EVENT_VOLTAGE_CHANGE) 403 info->uv_vref = (unsigned long)data; 404 405 return NOTIFY_OK; 406 } 407 408 static void rockchip_saradc_regulator_unreg_notifier(void *data) 409 { 410 struct rockchip_saradc *info = data; 411 412 regulator_unregister_notifier(info->vref, &info->nb); 413 } 414 415 static int rockchip_saradc_probe(struct platform_device *pdev) 416 { 417 const struct rockchip_saradc_data *match_data; 418 struct rockchip_saradc *info = NULL; 419 struct device_node *np = pdev->dev.of_node; 420 struct iio_dev *indio_dev = NULL; 421 int ret; 422 int irq; 423 424 if (!np) 425 return -ENODEV; 426 427 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); 428 if (!indio_dev) 429 return dev_err_probe(&pdev->dev, -ENOMEM, 430 "failed allocating iio device\n"); 431 432 info = iio_priv(indio_dev); 433 434 match_data = of_device_get_match_data(&pdev->dev); 435 if (!match_data) 436 return dev_err_probe(&pdev->dev, -ENODEV, 437 "failed to match device\n"); 438 439 info->data = match_data; 440 441 /* Sanity check for possible later IP variants with more channels */ 442 if (info->data->num_channels > SARADC_MAX_CHANNELS) 443 return dev_err_probe(&pdev->dev, -EINVAL, 444 "max channels exceeded"); 445 446 info->regs = devm_platform_ioremap_resource(pdev, 0); 447 if (IS_ERR(info->regs)) 448 return PTR_ERR(info->regs); 449 450 /* 451 * The reset should be an optional property, as it should work 452 * with old devicetrees as well 453 */ 454 info->reset = devm_reset_control_get_exclusive(&pdev->dev, 455 "saradc-apb"); 456 if (IS_ERR(info->reset)) { 457 ret = PTR_ERR(info->reset); 458 if (ret != -ENOENT) 459 return dev_err_probe(&pdev->dev, ret, 460 "failed to get saradc-apb\n"); 461 462 dev_dbg(&pdev->dev, "no reset control found\n"); 463 info->reset = NULL; 464 } 465 466 init_completion(&info->completion); 467 468 irq = platform_get_irq(pdev, 0); 469 if (irq < 0) 470 return dev_err_probe(&pdev->dev, irq, "failed to get irq\n"); 471 472 ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr, 473 0, dev_name(&pdev->dev), info); 474 if (ret < 0) { 475 dev_err(&pdev->dev, "failed requesting irq %d\n", irq); 476 return ret; 477 } 478 479 info->vref = devm_regulator_get(&pdev->dev, "vref"); 480 if (IS_ERR(info->vref)) 481 return dev_err_probe(&pdev->dev, PTR_ERR(info->vref), 482 "failed to get regulator\n"); 483 484 if (info->reset) 485 rockchip_saradc_reset_controller(info->reset); 486 487 /* 488 * Use a default value for the converter clock. 489 * This may become user-configurable in the future. 490 */ 491 ret = clk_set_rate(info->clk, info->data->clk_rate); 492 if (ret < 0) 493 return dev_err_probe(&pdev->dev, ret, 494 "failed to set adc clk rate\n"); 495 496 ret = regulator_enable(info->vref); 497 if (ret < 0) 498 return dev_err_probe(&pdev->dev, ret, 499 "failed to enable vref regulator\n"); 500 501 ret = devm_add_action_or_reset(&pdev->dev, 502 rockchip_saradc_regulator_disable, info); 503 if (ret) 504 return dev_err_probe(&pdev->dev, ret, 505 "failed to register devm action\n"); 506 507 ret = regulator_get_voltage(info->vref); 508 if (ret < 0) 509 return ret; 510 511 info->uv_vref = ret; 512 513 info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); 514 if (IS_ERR(info->pclk)) 515 return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), 516 "failed to get pclk\n"); 517 518 info->clk = devm_clk_get_enabled(&pdev->dev, "saradc"); 519 if (IS_ERR(info->clk)) 520 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), 521 "failed to get adc clock\n"); 522 523 platform_set_drvdata(pdev, indio_dev); 524 525 indio_dev->name = dev_name(&pdev->dev); 526 indio_dev->info = &rockchip_saradc_iio_info; 527 indio_dev->modes = INDIO_DIRECT_MODE; 528 529 indio_dev->channels = info->data->channels; 530 indio_dev->num_channels = info->data->num_channels; 531 ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL, 532 rockchip_saradc_trigger_handler, 533 NULL); 534 if (ret) 535 return ret; 536 537 info->nb.notifier_call = rockchip_saradc_volt_notify; 538 ret = regulator_register_notifier(info->vref, &info->nb); 539 if (ret) 540 return ret; 541 542 ret = devm_add_action_or_reset(&pdev->dev, 543 rockchip_saradc_regulator_unreg_notifier, 544 info); 545 if (ret) 546 return ret; 547 548 mutex_init(&info->lock); 549 550 return devm_iio_device_register(&pdev->dev, indio_dev); 551 } 552 553 static int rockchip_saradc_suspend(struct device *dev) 554 { 555 struct iio_dev *indio_dev = dev_get_drvdata(dev); 556 struct rockchip_saradc *info = iio_priv(indio_dev); 557 558 clk_disable_unprepare(info->clk); 559 clk_disable_unprepare(info->pclk); 560 regulator_disable(info->vref); 561 562 return 0; 563 } 564 565 static int rockchip_saradc_resume(struct device *dev) 566 { 567 struct iio_dev *indio_dev = dev_get_drvdata(dev); 568 struct rockchip_saradc *info = iio_priv(indio_dev); 569 int ret; 570 571 ret = regulator_enable(info->vref); 572 if (ret) 573 return ret; 574 575 ret = clk_prepare_enable(info->pclk); 576 if (ret) 577 return ret; 578 579 ret = clk_prepare_enable(info->clk); 580 if (ret) 581 clk_disable_unprepare(info->pclk); 582 583 return ret; 584 } 585 586 static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops, 587 rockchip_saradc_suspend, 588 rockchip_saradc_resume); 589 590 static struct platform_driver rockchip_saradc_driver = { 591 .probe = rockchip_saradc_probe, 592 .driver = { 593 .name = "rockchip-saradc", 594 .of_match_table = rockchip_saradc_match, 595 .pm = pm_sleep_ptr(&rockchip_saradc_pm_ops), 596 }, 597 }; 598 599 module_platform_driver(rockchip_saradc_driver); 600 601 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 602 MODULE_DESCRIPTION("Rockchip SARADC driver"); 603 MODULE_LICENSE("GPL v2"); 604