1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Qualcomm PM8xxx PMIC XOADC driver
4  *
5  * These ADCs are known as HK/XO (house keeping / chrystal oscillator)
6  * "XO" in "XOADC" means Chrystal Oscillator. It's a bunch of
7  * specific-purpose and general purpose ADC converters and channels.
8  *
9  * Copyright (C) 2017 Linaro Ltd.
10  * Author: Linus Walleij <linus.walleij@linaro.org>
11  */
12 
13 #include <linux/iio/adc/qcom-vadc-common.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/regulator/consumer.h>
24 
25 /*
26  * Definitions for the "user processor" registers lifted from the v3.4
27  * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC:
28  * drivers/misc/pmic8058-xoadc.c
29  * drivers/hwmon/pm8xxx-adc.c
30  * None of them contain any complete register specification, so this is
31  * a best effort of combining the information.
32  */
33 
34 /* These appear to be "battery monitor" registers */
35 #define ADC_ARB_BTM_CNTRL1			0x17e
36 #define ADC_ARB_BTM_CNTRL1_EN_BTM		BIT(0)
37 #define ADC_ARB_BTM_CNTRL1_SEL_OP_MODE		BIT(1)
38 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1	BIT(2)
39 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2	BIT(3)
40 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3	BIT(4)
41 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4	BIT(5)
42 #define ADC_ARB_BTM_CNTRL1_EOC			BIT(6)
43 #define ADC_ARB_BTM_CNTRL1_REQ			BIT(7)
44 
45 #define ADC_ARB_BTM_AMUX_CNTRL			0x17f
46 #define ADC_ARB_BTM_ANA_PARAM			0x180
47 #define ADC_ARB_BTM_DIG_PARAM			0x181
48 #define ADC_ARB_BTM_RSV				0x182
49 #define ADC_ARB_BTM_DATA1			0x183
50 #define ADC_ARB_BTM_DATA0			0x184
51 #define ADC_ARB_BTM_BAT_COOL_THR1		0x185
52 #define ADC_ARB_BTM_BAT_COOL_THR0		0x186
53 #define ADC_ARB_BTM_BAT_WARM_THR1		0x187
54 #define ADC_ARB_BTM_BAT_WARM_THR0		0x188
55 #define ADC_ARB_BTM_CNTRL2			0x18c
56 
57 /* Proper ADC registers */
58 
59 #define ADC_ARB_USRP_CNTRL			0x197
60 #define ADC_ARB_USRP_CNTRL_EN_ARB		BIT(0)
61 #define ADC_ARB_USRP_CNTRL_RSV1			BIT(1)
62 #define ADC_ARB_USRP_CNTRL_RSV2			BIT(2)
63 #define ADC_ARB_USRP_CNTRL_RSV3			BIT(3)
64 #define ADC_ARB_USRP_CNTRL_RSV4			BIT(4)
65 #define ADC_ARB_USRP_CNTRL_RSV5			BIT(5)
66 #define ADC_ARB_USRP_CNTRL_EOC			BIT(6)
67 #define ADC_ARB_USRP_CNTRL_REQ			BIT(7)
68 
69 #define ADC_ARB_USRP_AMUX_CNTRL			0x198
70 /*
71  * The channel mask includes the bits selecting channel mux and prescaler
72  * on PM8058, or channel mux and premux on PM8921.
73  */
74 #define ADC_ARB_USRP_AMUX_CNTRL_CHAN_MASK	0xfc
75 #define ADC_ARB_USRP_AMUX_CNTRL_RSV0		BIT(0)
76 #define ADC_ARB_USRP_AMUX_CNTRL_RSV1		BIT(1)
77 /* On PM8058 this is prescaling, on PM8921 this is premux */
78 #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX0	BIT(2)
79 #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX1	BIT(3)
80 #define ADC_ARB_USRP_AMUX_CNTRL_SEL0		BIT(4)
81 #define ADC_ARB_USRP_AMUX_CNTRL_SEL1		BIT(5)
82 #define ADC_ARB_USRP_AMUX_CNTRL_SEL2		BIT(6)
83 #define ADC_ARB_USRP_AMUX_CNTRL_SEL3		BIT(7)
84 #define ADC_AMUX_PREMUX_SHIFT			2
85 #define ADC_AMUX_SEL_SHIFT			4
86 
87 /* We know very little about the bits in this register */
88 #define ADC_ARB_USRP_ANA_PARAM			0x199
89 #define ADC_ARB_USRP_ANA_PARAM_DIS		0xFE
90 #define ADC_ARB_USRP_ANA_PARAM_EN		0xFF
91 
92 #define ADC_ARB_USRP_DIG_PARAM			0x19A
93 #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0	BIT(0)
94 #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1	BIT(1)
95 #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE0	BIT(2)
96 #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE1	BIT(3)
97 #define ADC_ARB_USRP_DIG_PARAM_EOC		BIT(4)
98 /*
99  * On a later ADC the decimation factors are defined as
100  * 00 = 512, 01 = 1024, 10 = 2048, 11 = 4096 so assume this
101  * holds also for this older XOADC.
102  */
103 #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE0	BIT(5)
104 #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE1	BIT(6)
105 #define ADC_ARB_USRP_DIG_PARAM_EN		BIT(7)
106 #define ADC_DIG_PARAM_DEC_SHIFT			5
107 
108 #define ADC_ARB_USRP_RSV			0x19B
109 #define ADC_ARB_USRP_RSV_RST			BIT(0)
110 #define ADC_ARB_USRP_RSV_DTEST0			BIT(1)
111 #define ADC_ARB_USRP_RSV_DTEST1			BIT(2)
112 #define ADC_ARB_USRP_RSV_OP			BIT(3)
113 #define ADC_ARB_USRP_RSV_IP_SEL0		BIT(4)
114 #define ADC_ARB_USRP_RSV_IP_SEL1		BIT(5)
115 #define ADC_ARB_USRP_RSV_IP_SEL2		BIT(6)
116 #define ADC_ARB_USRP_RSV_TRM			BIT(7)
117 #define ADC_RSV_IP_SEL_SHIFT			4
118 
119 #define ADC_ARB_USRP_DATA0			0x19D
120 #define ADC_ARB_USRP_DATA1			0x19C
121 
122 /*
123  * Physical channels which MUST exist on all PM variants in order to provide
124  * proper reference points for calibration.
125  *
126  * @PM8XXX_CHANNEL_INTERNAL: 625mV reference channel
127  * @PM8XXX_CHANNEL_125V: 1250mV reference channel
128  * @PM8XXX_CHANNEL_INTERNAL_2: 325mV reference channel
129  * @PM8XXX_CHANNEL_MUXOFF: channel to reduce input load on mux, apparently also
130  * measures XO temperature
131  */
132 #define PM8XXX_CHANNEL_INTERNAL		0x0c
133 #define PM8XXX_CHANNEL_125V		0x0d
134 #define PM8XXX_CHANNEL_INTERNAL_2	0x0e
135 #define PM8XXX_CHANNEL_MUXOFF		0x0f
136 
137 /*
138  * PM8058 AMUX premux scaling, two bits. This is done of the channel before
139  * reaching the AMUX.
140  */
141 #define PM8058_AMUX_PRESCALE_0 0x0 /* No scaling on the signal */
142 #define PM8058_AMUX_PRESCALE_1 0x1 /* Unity scaling selected by the user */
143 #define PM8058_AMUX_PRESCALE_1_DIV3 0x2 /* 1/3 prescaler on the input */
144 
145 /* Defines reference voltage for the XOADC */
146 #define AMUX_RSV0 0x0 /* XO_IN/XOADC_GND, special selection to read XO temp */
147 #define AMUX_RSV1 0x1 /* PMIC_IN/XOADC_GND */
148 #define AMUX_RSV2 0x2 /* PMIC_IN/BMS_CSP */
149 #define AMUX_RSV3 0x3 /* not used */
150 #define AMUX_RSV4 0x4 /* XOADC_GND/XOADC_GND */
151 #define AMUX_RSV5 0x5 /* XOADC_VREF/XOADC_GND */
152 #define XOADC_RSV_MAX 5 /* 3 bits 0..7, 3 and 6,7 are invalid */
153 
154 /**
155  * struct xoadc_channel - encodes channel properties and defaults
156  * @datasheet_name: the hardwarename of this channel
157  * @pre_scale_mux: prescale (PM8058) or premux (PM8921) for selecting
158  * this channel. Both this and the amux channel is needed to uniquely
159  * identify a channel. Values 0..3.
160  * @amux_channel: value of the ADC_ARB_USRP_AMUX_CNTRL register for this
161  * channel, bits 4..7, selects the amux, values 0..f
162  * @prescale: the channels have hard-coded prescale ratios defined
163  * by the hardware, this tells us what it is
164  * @type: corresponding IIO channel type, usually IIO_VOLTAGE or
165  * IIO_TEMP
166  * @scale_fn_type: the liner interpolation etc to convert the
167  * ADC code to the value that IIO expects, in uV or millicelsius
168  * etc. This scale function can be pretty elaborate if different
169  * thermistors are connected or other hardware characteristics are
170  * deployed.
171  * @amux_ip_rsv: ratiometric scale value used by the analog muxer: this
172  * selects the reference voltage for ratiometric scaling
173  */
174 struct xoadc_channel {
175 	const char *datasheet_name;
176 	u8 pre_scale_mux:2;
177 	u8 amux_channel:4;
178 	const struct u32_fract prescale;
179 	enum iio_chan_type type;
180 	enum vadc_scale_fn_type scale_fn_type;
181 	u8 amux_ip_rsv:3;
182 };
183 
184 /**
185  * struct xoadc_variant - encodes the XOADC variant characteristics
186  * @name: name of this PMIC variant
187  * @channels: the hardware channels and respective settings and defaults
188  * @broken_ratiometric: if the PMIC has broken ratiometric scaling (this
189  * is a known problem on PM8058)
190  * @prescaling: this variant uses AMUX bits 2 & 3 for prescaling (PM8058)
191  * @second_level_mux: this variant uses AMUX bits 2 & 3 for a second level
192  * mux
193  */
194 struct xoadc_variant {
195 	const char name[16];
196 	const struct xoadc_channel *channels;
197 	bool broken_ratiometric;
198 	bool prescaling;
199 	bool second_level_mux;
200 };
201 
202 /*
203  * XOADC_CHAN macro parameters:
204  * _dname: the name of the channel
205  * _presmux: prescaler (PM8058) or premux (PM8921) setting for this channel
206  * _amux: the value in bits 2..7 of the ADC_ARB_USRP_AMUX_CNTRL register
207  * for this channel. On some PMICs some of the bits select a prescaler, and
208  * on some PMICs some of the bits select various complex multiplex settings.
209  * _type: IIO channel type
210  * _prenum: prescaler numerator (dividend)
211  * _preden: prescaler denominator (divisor)
212  * _scale: scaling function type, this selects how the raw valued is mangled
213  * to output the actual processed measurement
214  * _amip: analog mux input parent when using ratiometric measurements
215  */
216 #define XOADC_CHAN(_dname, _presmux, _amux, _type, _prenum, _preden, _scale, _amip) \
217 	{								\
218 		.datasheet_name = __stringify(_dname),			\
219 		.pre_scale_mux = _presmux,				\
220 		.amux_channel = _amux,					\
221 		.prescale = {						\
222 			.numerator = _prenum, .denominator = _preden,	\
223 		},							\
224 		.type = _type,						\
225 		.scale_fn_type = _scale,				\
226 		.amux_ip_rsv = _amip,					\
227 	}
228 
229 /*
230  * Taken from arch/arm/mach-msm/board-9615.c in the vendor tree:
231  * TODO: incomplete, needs testing.
232  */
233 static const struct xoadc_channel pm8018_xoadc_channels[] = {
234 	XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
235 	XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
236 	XOADC_CHAN(VPH_PWR, 0x00, 0x02, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
237 	XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
238 	/* Used for battery ID or battery temperature */
239 	XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV2),
240 	XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
241 	XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
242 	XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
243 	{ }, /* Sentinel */
244 };
245 
246 /*
247  * Taken from arch/arm/mach-msm/board-8930-pmic.c in the vendor tree:
248  * TODO: needs testing.
249  */
250 static const struct xoadc_channel pm8038_xoadc_channels[] = {
251 	XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
252 	XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
253 	XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
254 	XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
255 	XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
256 	XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
257 	XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
258 	XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
259 	/* AMUX8 used for battery temperature in most cases */
260 	XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV2),
261 	XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
262 	XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
263 	XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
264 	XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
265 	XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
266 	XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
267 	XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
268 	{ }, /* Sentinel */
269 };
270 
271 /*
272  * This was created by cross-referencing the vendor tree
273  * arch/arm/mach-msm/board-msm8x60.c msm_adc_channels_data[]
274  * with the "channel types" (first field) to find the right
275  * configuration for these channels on an MSM8x60 i.e. PM8058
276  * setup.
277  */
278 static const struct xoadc_channel pm8058_xoadc_channels[] = {
279 	XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
280 	XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
281 	XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 10, SCALE_DEFAULT, AMUX_RSV1),
282 	XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
283 	XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
284 	/*
285 	 * AMUX channels 5 thru 9 are referred to as MPP5 thru MPP9 in
286 	 * some code and documentation. But they are really just 5
287 	 * channels just like any other. They are connected to a switching
288 	 * matrix where they can be routed to any of the MPPs, not just
289 	 * 1-to-1 onto MPP5 thru 9, so naming them MPP5 thru MPP9 is
290 	 * very confusing.
291 	 */
292 	XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
293 	XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
294 	XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
295 	XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
296 	XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
297 	XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
298 	XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
299 	XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
300 	XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
301 	XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
302 	XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
303 	/* There are also "unity" and divided by 3 channels (prescaler) but noone is using them */
304 	{ }, /* Sentinel */
305 };
306 
307 /*
308  * The PM8921 has some pre-muxing on its channels, this comes from the vendor tree
309  * include/linux/mfd/pm8xxx/pm8xxx-adc.h
310  * board-flo-pmic.c (Nexus 7) and board-8064-pmic.c
311  */
312 static const struct xoadc_channel pm8921_xoadc_channels[] = {
313 	XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
314 	XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
315 	XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
316 	/* channel "ICHG" is reserved and not used on PM8921 */
317 	XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
318 	XOADC_CHAN(IBAT, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
319 	/* CHAN 6 & 7 (MPP1 & MPP2) are reserved for MPP channels on PM8921 */
320 	XOADC_CHAN(BATT_THERM, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV1),
321 	XOADC_CHAN(BATT_ID, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
322 	XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
323 	XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
324 	XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
325 	XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
326 	/* FIXME: look into the scaling of this temperature */
327 	XOADC_CHAN(CHG_TEMP, 0x00, 0x0e, IIO_TEMP, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
328 	XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
329 	/* The following channels have premux bit 0 set to 1 (all end in 4) */
330 	XOADC_CHAN(ATEST_8, 0x01, 0x00, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
331 	/* Set scaling to 1/2 based on the name for these two */
332 	XOADC_CHAN(USB_SNS_DIV20, 0x01, 0x01, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
333 	XOADC_CHAN(DCIN_SNS_DIV20, 0x01, 0x02, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
334 	XOADC_CHAN(AMUX3, 0x01, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
335 	XOADC_CHAN(AMUX4, 0x01, 0x04, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
336 	XOADC_CHAN(AMUX5, 0x01, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
337 	XOADC_CHAN(AMUX6, 0x01, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
338 	XOADC_CHAN(AMUX7, 0x01, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
339 	XOADC_CHAN(AMUX8, 0x01, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
340 	/* Internal test signals, I think */
341 	XOADC_CHAN(ATEST_1, 0x01, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
342 	XOADC_CHAN(ATEST_2, 0x01, 0x0a, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
343 	XOADC_CHAN(ATEST_3, 0x01, 0x0b, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
344 	XOADC_CHAN(ATEST_4, 0x01, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
345 	XOADC_CHAN(ATEST_5, 0x01, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
346 	XOADC_CHAN(ATEST_6, 0x01, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
347 	XOADC_CHAN(ATEST_7, 0x01, 0x0f, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
348 	/* The following channels have premux bit 1 set to 1 (all end in 8) */
349 	/* I guess even ATEST8 will be divided by 3 here */
350 	XOADC_CHAN(ATEST_8, 0x02, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
351 	/* I guess div 2 div 3 becomes div 6 */
352 	XOADC_CHAN(USB_SNS_DIV20_DIV3, 0x02, 0x01, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
353 	XOADC_CHAN(DCIN_SNS_DIV20_DIV3, 0x02, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
354 	XOADC_CHAN(AMUX3_DIV3, 0x02, 0x03, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
355 	XOADC_CHAN(AMUX4_DIV3, 0x02, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
356 	XOADC_CHAN(AMUX5_DIV3, 0x02, 0x05, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
357 	XOADC_CHAN(AMUX6_DIV3, 0x02, 0x06, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
358 	XOADC_CHAN(AMUX7_DIV3, 0x02, 0x07, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
359 	XOADC_CHAN(AMUX8_DIV3, 0x02, 0x08, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
360 	XOADC_CHAN(ATEST_1_DIV3, 0x02, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
361 	XOADC_CHAN(ATEST_2_DIV3, 0x02, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
362 	XOADC_CHAN(ATEST_3_DIV3, 0x02, 0x0b, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
363 	XOADC_CHAN(ATEST_4_DIV3, 0x02, 0x0c, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
364 	XOADC_CHAN(ATEST_5_DIV3, 0x02, 0x0d, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
365 	XOADC_CHAN(ATEST_6_DIV3, 0x02, 0x0e, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
366 	XOADC_CHAN(ATEST_7_DIV3, 0x02, 0x0f, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
367 	{ }, /* Sentinel */
368 };
369 
370 /**
371  * struct pm8xxx_chan_info - ADC channel information
372  * @name: name of this channel
373  * @hwchan: pointer to hardware channel information (muxing & scaling settings)
374  * @calibration: whether to use absolute or ratiometric calibration
375  * @scale_fn_type: scaling function type
376  * @decimation: 0,1,2,3
377  * @amux_ip_rsv: ratiometric scale value if using ratiometric
378  * calibration: 0, 1, 2, 4, 5.
379  */
380 struct pm8xxx_chan_info {
381 	const char *name;
382 	const struct xoadc_channel *hwchan;
383 	enum vadc_calibration calibration;
384 	u8 decimation:2;
385 	u8 amux_ip_rsv:3;
386 };
387 
388 /**
389  * struct pm8xxx_xoadc - state container for the XOADC
390  * @dev: pointer to device
391  * @map: regmap to access registers
392  * @variant: XOADC variant characteristics
393  * @vref: reference voltage regulator
394  * characteristics of the channels, and sensible default settings
395  * @nchans: number of channels, configured by the device tree
396  * @chans: the channel information per-channel, configured by the device tree
397  * @iio_chans: IIO channel specifiers
398  * @graph: linear calibration parameters for absolute and
399  * ratiometric measurements
400  * @complete: completion to indicate end of conversion
401  * @lock: lock to restrict access to the hardware to one client at the time
402  */
403 struct pm8xxx_xoadc {
404 	struct device *dev;
405 	struct regmap *map;
406 	const struct xoadc_variant *variant;
407 	struct regulator *vref;
408 	unsigned int nchans;
409 	struct pm8xxx_chan_info *chans;
410 	struct iio_chan_spec *iio_chans;
411 	struct vadc_linear_graph graph[2];
412 	struct completion complete;
413 	struct mutex lock;
414 };
415 
416 static irqreturn_t pm8xxx_eoc_irq(int irq, void *d)
417 {
418 	struct iio_dev *indio_dev = d;
419 	struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
420 
421 	complete(&adc->complete);
422 
423 	return IRQ_HANDLED;
424 }
425 
426 static struct pm8xxx_chan_info *
427 pm8xxx_get_channel(struct pm8xxx_xoadc *adc, u8 chan)
428 {
429 	int i;
430 
431 	for (i = 0; i < adc->nchans; i++) {
432 		struct pm8xxx_chan_info *ch = &adc->chans[i];
433 		if (ch->hwchan->amux_channel == chan)
434 			return ch;
435 	}
436 	return NULL;
437 }
438 
439 static int pm8xxx_read_channel_rsv(struct pm8xxx_xoadc *adc,
440 				   const struct pm8xxx_chan_info *ch,
441 				   u8 rsv, u16 *adc_code,
442 				   bool force_ratiometric)
443 {
444 	int ret;
445 	unsigned int val;
446 	u8 rsvmask, rsvval;
447 	u8 lsb, msb;
448 
449 	dev_dbg(adc->dev, "read channel \"%s\", amux %d, prescale/mux: %d, rsv %d\n",
450 		ch->name, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv);
451 
452 	mutex_lock(&adc->lock);
453 
454 	/* Mux in this channel */
455 	val = ch->hwchan->amux_channel << ADC_AMUX_SEL_SHIFT;
456 	val |= ch->hwchan->pre_scale_mux << ADC_AMUX_PREMUX_SHIFT;
457 	ret = regmap_write(adc->map, ADC_ARB_USRP_AMUX_CNTRL, val);
458 	if (ret)
459 		goto unlock;
460 
461 	/* Set up ratiometric scale value, mask off all bits except these */
462 	rsvmask = (ADC_ARB_USRP_RSV_RST | ADC_ARB_USRP_RSV_DTEST0 |
463 		   ADC_ARB_USRP_RSV_DTEST1 | ADC_ARB_USRP_RSV_OP);
464 	if (adc->variant->broken_ratiometric && !force_ratiometric) {
465 		/*
466 		 * Apparently the PM8058 has some kind of bug which is
467 		 * reflected in the vendor tree drivers/misc/pmix8058-xoadc.c
468 		 * which just hardcodes the RSV selector to SEL1 (0x20) for
469 		 * most cases and SEL0 (0x10) for the MUXOFF channel only.
470 		 * If we force ratiometric (currently only done when attempting
471 		 * to do ratiometric calibration) this doesn't seem to work
472 		 * very well and I suspect ratiometric conversion is simply
473 		 * broken or not supported on the PM8058.
474 		 *
475 		 * Maybe IO_SEL2 doesn't exist on PM8058 and bits 4 & 5 select
476 		 * the mode alone.
477 		 *
478 		 * Some PM8058 register documentation would be nice to get
479 		 * this right.
480 		 */
481 		if (ch->hwchan->amux_channel == PM8XXX_CHANNEL_MUXOFF)
482 			rsvval = ADC_ARB_USRP_RSV_IP_SEL0;
483 		else
484 			rsvval = ADC_ARB_USRP_RSV_IP_SEL1;
485 	} else {
486 		if (rsv == 0xff)
487 			rsvval = (ch->amux_ip_rsv << ADC_RSV_IP_SEL_SHIFT) |
488 				ADC_ARB_USRP_RSV_TRM;
489 		else
490 			rsvval = (rsv << ADC_RSV_IP_SEL_SHIFT) |
491 				ADC_ARB_USRP_RSV_TRM;
492 	}
493 
494 	ret = regmap_update_bits(adc->map,
495 				 ADC_ARB_USRP_RSV,
496 				 ~rsvmask,
497 				 rsvval);
498 	if (ret)
499 		goto unlock;
500 
501 	ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
502 			   ADC_ARB_USRP_ANA_PARAM_DIS);
503 	if (ret)
504 		goto unlock;
505 
506 	/* Decimation factor */
507 	ret = regmap_write(adc->map, ADC_ARB_USRP_DIG_PARAM,
508 			   ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 |
509 			   ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 |
510 			   ch->decimation << ADC_DIG_PARAM_DEC_SHIFT);
511 	if (ret)
512 		goto unlock;
513 
514 	ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
515 			   ADC_ARB_USRP_ANA_PARAM_EN);
516 	if (ret)
517 		goto unlock;
518 
519 	/* Enable the arbiter, the Qualcomm code does it twice like this */
520 	ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
521 			   ADC_ARB_USRP_CNTRL_EN_ARB);
522 	if (ret)
523 		goto unlock;
524 	ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
525 			   ADC_ARB_USRP_CNTRL_EN_ARB);
526 	if (ret)
527 		goto unlock;
528 
529 
530 	/* Fire a request! */
531 	reinit_completion(&adc->complete);
532 	ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
533 			   ADC_ARB_USRP_CNTRL_EN_ARB |
534 			   ADC_ARB_USRP_CNTRL_REQ);
535 	if (ret)
536 		goto unlock;
537 
538 	/* Next the interrupt occurs */
539 	ret = wait_for_completion_timeout(&adc->complete,
540 					  VADC_CONV_TIME_MAX_US);
541 	if (!ret) {
542 		dev_err(adc->dev, "conversion timed out\n");
543 		ret = -ETIMEDOUT;
544 		goto unlock;
545 	}
546 
547 	ret = regmap_read(adc->map, ADC_ARB_USRP_DATA0, &val);
548 	if (ret)
549 		goto unlock;
550 	lsb = val;
551 	ret = regmap_read(adc->map, ADC_ARB_USRP_DATA1, &val);
552 	if (ret)
553 		goto unlock;
554 	msb = val;
555 	*adc_code = (msb << 8) | lsb;
556 
557 	/* Turn off the ADC by setting the arbiter to 0 twice */
558 	ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
559 	if (ret)
560 		goto unlock;
561 	ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
562 	if (ret)
563 		goto unlock;
564 
565 unlock:
566 	mutex_unlock(&adc->lock);
567 	return ret;
568 }
569 
570 static int pm8xxx_read_channel(struct pm8xxx_xoadc *adc,
571 			       const struct pm8xxx_chan_info *ch,
572 			       u16 *adc_code)
573 {
574 	/*
575 	 * Normally we just use the ratiometric scale value (RSV) predefined
576 	 * for the channel, but during calibration we need to modify this
577 	 * so this wrapper is a helper hiding the more complex version.
578 	 */
579 	return pm8xxx_read_channel_rsv(adc, ch, 0xff, adc_code, false);
580 }
581 
582 static int pm8xxx_calibrate_device(struct pm8xxx_xoadc *adc)
583 {
584 	const struct pm8xxx_chan_info *ch;
585 	u16 read_1250v;
586 	u16 read_0625v;
587 	u16 read_nomux_rsv5;
588 	u16 read_nomux_rsv4;
589 	int ret;
590 
591 	adc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;
592 	adc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;
593 
594 	/* Common reference channel calibration */
595 	ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
596 	if (!ch)
597 		return -ENODEV;
598 	ret = pm8xxx_read_channel(adc, ch, &read_1250v);
599 	if (ret) {
600 		dev_err(adc->dev, "could not read 1.25V reference channel\n");
601 		return -ENODEV;
602 	}
603 	ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
604 	if (!ch)
605 		return -ENODEV;
606 	ret = pm8xxx_read_channel(adc, ch, &read_0625v);
607 	if (ret) {
608 		dev_err(adc->dev, "could not read 0.625V reference channel\n");
609 		return -ENODEV;
610 	}
611 	if (read_1250v == read_0625v) {
612 		dev_err(adc->dev, "read same ADC code for 1.25V and 0.625V\n");
613 		return -ENODEV;
614 	}
615 
616 	adc->graph[VADC_CALIB_ABSOLUTE].dy = read_1250v - read_0625v;
617 	adc->graph[VADC_CALIB_ABSOLUTE].gnd = read_0625v;
618 
619 	dev_info(adc->dev, "absolute calibration dx = %d uV, dy = %d units\n",
620 		 VADC_ABSOLUTE_RANGE_UV, adc->graph[VADC_CALIB_ABSOLUTE].dy);
621 
622 	/* Ratiometric calibration */
623 	ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
624 	if (!ch)
625 		return -ENODEV;
626 	ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV5,
627 				      &read_nomux_rsv5, true);
628 	if (ret) {
629 		dev_err(adc->dev, "could not read MUXOFF reference channel\n");
630 		return -ENODEV;
631 	}
632 	ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV4,
633 				      &read_nomux_rsv4, true);
634 	if (ret) {
635 		dev_err(adc->dev, "could not read MUXOFF reference channel\n");
636 		return -ENODEV;
637 	}
638 	adc->graph[VADC_CALIB_RATIOMETRIC].dy =
639 		read_nomux_rsv5 - read_nomux_rsv4;
640 	adc->graph[VADC_CALIB_RATIOMETRIC].gnd = read_nomux_rsv4;
641 
642 	dev_info(adc->dev, "ratiometric calibration dx = %d, dy = %d units\n",
643 		 VADC_RATIOMETRIC_RANGE,
644 		 adc->graph[VADC_CALIB_RATIOMETRIC].dy);
645 
646 	return 0;
647 }
648 
649 static int pm8xxx_read_raw(struct iio_dev *indio_dev,
650 			   struct iio_chan_spec const *chan,
651 			   int *val, int *val2, long mask)
652 {
653 	struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
654 	const struct pm8xxx_chan_info *ch;
655 	u16 adc_code;
656 	int ret;
657 
658 	switch (mask) {
659 	case IIO_CHAN_INFO_PROCESSED:
660 		ch = pm8xxx_get_channel(adc, chan->address);
661 		if (!ch) {
662 			dev_err(adc->dev, "no such channel %lu\n",
663 				chan->address);
664 			return -EINVAL;
665 		}
666 		ret = pm8xxx_read_channel(adc, ch, &adc_code);
667 		if (ret)
668 			return ret;
669 
670 		ret = qcom_vadc_scale(ch->hwchan->scale_fn_type,
671 				      &adc->graph[ch->calibration],
672 				      &ch->hwchan->prescale,
673 				      (ch->calibration == VADC_CALIB_ABSOLUTE),
674 				      adc_code, val);
675 		if (ret)
676 			return ret;
677 
678 		return IIO_VAL_INT;
679 	case IIO_CHAN_INFO_RAW:
680 		ch = pm8xxx_get_channel(adc, chan->address);
681 		if (!ch) {
682 			dev_err(adc->dev, "no such channel %lu\n",
683 				chan->address);
684 			return -EINVAL;
685 		}
686 		ret = pm8xxx_read_channel(adc, ch, &adc_code);
687 		if (ret)
688 			return ret;
689 
690 		*val = (int)adc_code;
691 		return IIO_VAL_INT;
692 	default:
693 		return -EINVAL;
694 	}
695 }
696 
697 static int pm8xxx_of_xlate(struct iio_dev *indio_dev,
698 			   const struct of_phandle_args *iiospec)
699 {
700 	struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
701 	u8 pre_scale_mux;
702 	u8 amux_channel;
703 	unsigned int i;
704 
705 	/*
706 	 * First cell is prescaler or premux, second cell is analog
707 	 * mux.
708 	 */
709 	if (iiospec->args_count != 2) {
710 		dev_err(&indio_dev->dev, "wrong number of arguments for %pOFn need 2 got %d\n",
711 			iiospec->np,
712 			iiospec->args_count);
713 		return -EINVAL;
714 	}
715 	pre_scale_mux = (u8)iiospec->args[0];
716 	amux_channel = (u8)iiospec->args[1];
717 	dev_dbg(&indio_dev->dev, "pre scale/mux: %02x, amux: %02x\n",
718 		pre_scale_mux, amux_channel);
719 
720 	/* We need to match exactly on the prescale/premux and channel */
721 	for (i = 0; i < adc->nchans; i++)
722 		if (adc->chans[i].hwchan->pre_scale_mux == pre_scale_mux &&
723 		    adc->chans[i].hwchan->amux_channel == amux_channel)
724 			return i;
725 
726 	return -EINVAL;
727 }
728 
729 static const struct iio_info pm8xxx_xoadc_info = {
730 	.of_xlate = pm8xxx_of_xlate,
731 	.read_raw = pm8xxx_read_raw,
732 };
733 
734 static int pm8xxx_xoadc_parse_channel(struct device *dev,
735 				      struct device_node *np,
736 				      const struct xoadc_channel *hw_channels,
737 				      struct iio_chan_spec *iio_chan,
738 				      struct pm8xxx_chan_info *ch)
739 {
740 	const char *name = np->name;
741 	const struct xoadc_channel *hwchan;
742 	u32 pre_scale_mux, amux_channel;
743 	u32 rsv, dec;
744 	int ret;
745 	int chid;
746 
747 	ret = of_property_read_u32_index(np, "reg", 0, &pre_scale_mux);
748 	if (ret) {
749 		dev_err(dev, "invalid pre scale/mux number %s\n", name);
750 		return ret;
751 	}
752 	ret = of_property_read_u32_index(np, "reg", 1, &amux_channel);
753 	if (ret) {
754 		dev_err(dev, "invalid amux channel number %s\n", name);
755 		return ret;
756 	}
757 
758 	/* Find the right channel setting */
759 	chid = 0;
760 	hwchan = &hw_channels[0];
761 	while (hwchan && hwchan->datasheet_name) {
762 		if (hwchan->pre_scale_mux == pre_scale_mux &&
763 		    hwchan->amux_channel == amux_channel)
764 			break;
765 		hwchan++;
766 		chid++;
767 	}
768 	/* The sentinel does not have a name assigned */
769 	if (!hwchan->datasheet_name) {
770 		dev_err(dev, "could not locate channel %02x/%02x\n",
771 			pre_scale_mux, amux_channel);
772 		return -EINVAL;
773 	}
774 	ch->name = name;
775 	ch->hwchan = hwchan;
776 	/* Everyone seems to use absolute calibration except in special cases */
777 	ch->calibration = VADC_CALIB_ABSOLUTE;
778 	/* Everyone seems to use default ("type 2") decimation */
779 	ch->decimation = VADC_DEF_DECIMATION;
780 
781 	if (!of_property_read_u32(np, "qcom,ratiometric", &rsv)) {
782 		ch->calibration = VADC_CALIB_RATIOMETRIC;
783 		if (rsv > XOADC_RSV_MAX) {
784 			dev_err(dev, "%s too large RSV value %d\n", name, rsv);
785 			return -EINVAL;
786 		}
787 		if (rsv == AMUX_RSV3) {
788 			dev_err(dev, "%s invalid RSV value %d\n", name, rsv);
789 			return -EINVAL;
790 		}
791 	}
792 
793 	/* Optional decimation, if omitted we use the default */
794 	ret = of_property_read_u32(np, "qcom,decimation", &dec);
795 	if (!ret) {
796 		ret = qcom_vadc_decimation_from_dt(dec);
797 		if (ret < 0) {
798 			dev_err(dev, "%s invalid decimation %d\n",
799 				name, dec);
800 			return ret;
801 		}
802 		ch->decimation = ret;
803 	}
804 
805 	iio_chan->channel = chid;
806 	iio_chan->address = hwchan->amux_channel;
807 	iio_chan->datasheet_name = hwchan->datasheet_name;
808 	iio_chan->type = hwchan->type;
809 	/* All channels are raw or processed */
810 	iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
811 		BIT(IIO_CHAN_INFO_PROCESSED);
812 	iio_chan->indexed = 1;
813 
814 	dev_dbg(dev,
815 		"channel [PRESCALE/MUX: %02x AMUX: %02x] \"%s\" ref voltage: %d, decimation %d prescale %d/%d, scale function %d\n",
816 		hwchan->pre_scale_mux, hwchan->amux_channel, ch->name,
817 		ch->amux_ip_rsv, ch->decimation, hwchan->prescale.numerator,
818 		hwchan->prescale.denominator, hwchan->scale_fn_type);
819 
820 	return 0;
821 }
822 
823 static int pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc *adc,
824 				       struct device_node *np)
825 {
826 	struct device_node *child;
827 	struct pm8xxx_chan_info *ch;
828 	int ret;
829 	int i;
830 
831 	adc->nchans = of_get_available_child_count(np);
832 	if (!adc->nchans) {
833 		dev_err(adc->dev, "no channel children\n");
834 		return -ENODEV;
835 	}
836 	dev_dbg(adc->dev, "found %d ADC channels\n", adc->nchans);
837 
838 	adc->iio_chans = devm_kcalloc(adc->dev, adc->nchans,
839 				      sizeof(*adc->iio_chans), GFP_KERNEL);
840 	if (!adc->iio_chans)
841 		return -ENOMEM;
842 
843 	adc->chans = devm_kcalloc(adc->dev, adc->nchans,
844 				  sizeof(*adc->chans), GFP_KERNEL);
845 	if (!adc->chans)
846 		return -ENOMEM;
847 
848 	i = 0;
849 	for_each_available_child_of_node(np, child) {
850 		ch = &adc->chans[i];
851 		ret = pm8xxx_xoadc_parse_channel(adc->dev, child,
852 						 adc->variant->channels,
853 						 &adc->iio_chans[i],
854 						 ch);
855 		if (ret) {
856 			of_node_put(child);
857 			return ret;
858 		}
859 		i++;
860 	}
861 
862 	/* Check for required channels */
863 	ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
864 	if (!ch) {
865 		dev_err(adc->dev, "missing 1.25V reference channel\n");
866 		return -ENODEV;
867 	}
868 	ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
869 	if (!ch) {
870 		dev_err(adc->dev, "missing 0.625V reference channel\n");
871 		return -ENODEV;
872 	}
873 	ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
874 	if (!ch) {
875 		dev_err(adc->dev, "missing MUXOFF reference channel\n");
876 		return -ENODEV;
877 	}
878 
879 	return 0;
880 }
881 
882 static int pm8xxx_xoadc_probe(struct platform_device *pdev)
883 {
884 	const struct xoadc_variant *variant;
885 	struct pm8xxx_xoadc *adc;
886 	struct iio_dev *indio_dev;
887 	struct device_node *np = pdev->dev.of_node;
888 	struct regmap *map;
889 	struct device *dev = &pdev->dev;
890 	int ret;
891 
892 	variant = of_device_get_match_data(dev);
893 	if (!variant)
894 		return -ENODEV;
895 
896 	indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
897 	if (!indio_dev)
898 		return -ENOMEM;
899 	platform_set_drvdata(pdev, indio_dev);
900 
901 	adc = iio_priv(indio_dev);
902 	adc->dev = dev;
903 	adc->variant = variant;
904 	init_completion(&adc->complete);
905 	mutex_init(&adc->lock);
906 
907 	ret = pm8xxx_xoadc_parse_channels(adc, np);
908 	if (ret)
909 		return ret;
910 
911 	map = dev_get_regmap(dev->parent, NULL);
912 	if (!map) {
913 		dev_err(dev, "parent regmap unavailable.\n");
914 		return -ENODEV;
915 	}
916 	adc->map = map;
917 
918 	/* Bring up regulator */
919 	adc->vref = devm_regulator_get(dev, "xoadc-ref");
920 	if (IS_ERR(adc->vref))
921 		return dev_err_probe(dev, PTR_ERR(adc->vref),
922 				     "failed to get XOADC VREF regulator\n");
923 	ret = regulator_enable(adc->vref);
924 	if (ret) {
925 		dev_err(dev, "failed to enable XOADC VREF regulator\n");
926 		return ret;
927 	}
928 
929 	ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
930 			pm8xxx_eoc_irq, NULL, 0, variant->name, indio_dev);
931 	if (ret) {
932 		dev_err(dev, "unable to request IRQ\n");
933 		goto out_disable_vref;
934 	}
935 
936 	indio_dev->name = variant->name;
937 	indio_dev->modes = INDIO_DIRECT_MODE;
938 	indio_dev->info = &pm8xxx_xoadc_info;
939 	indio_dev->channels = adc->iio_chans;
940 	indio_dev->num_channels = adc->nchans;
941 
942 	ret = iio_device_register(indio_dev);
943 	if (ret)
944 		goto out_disable_vref;
945 
946 	ret = pm8xxx_calibrate_device(adc);
947 	if (ret)
948 		goto out_unreg_device;
949 
950 	dev_info(dev, "%s XOADC driver enabled\n", variant->name);
951 
952 	return 0;
953 
954 out_unreg_device:
955 	iio_device_unregister(indio_dev);
956 out_disable_vref:
957 	regulator_disable(adc->vref);
958 
959 	return ret;
960 }
961 
962 static int pm8xxx_xoadc_remove(struct platform_device *pdev)
963 {
964 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
965 	struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
966 
967 	iio_device_unregister(indio_dev);
968 
969 	regulator_disable(adc->vref);
970 
971 	return 0;
972 }
973 
974 static const struct xoadc_variant pm8018_variant = {
975 	.name = "PM8018-XOADC",
976 	.channels = pm8018_xoadc_channels,
977 };
978 
979 static const struct xoadc_variant pm8038_variant = {
980 	.name = "PM8038-XOADC",
981 	.channels = pm8038_xoadc_channels,
982 };
983 
984 static const struct xoadc_variant pm8058_variant = {
985 	.name = "PM8058-XOADC",
986 	.channels = pm8058_xoadc_channels,
987 	.broken_ratiometric = true,
988 	.prescaling = true,
989 };
990 
991 static const struct xoadc_variant pm8921_variant = {
992 	.name = "PM8921-XOADC",
993 	.channels = pm8921_xoadc_channels,
994 	.second_level_mux = true,
995 };
996 
997 static const struct of_device_id pm8xxx_xoadc_id_table[] = {
998 	{
999 		.compatible = "qcom,pm8018-adc",
1000 		.data = &pm8018_variant,
1001 	},
1002 	{
1003 		.compatible = "qcom,pm8038-adc",
1004 		.data = &pm8038_variant,
1005 	},
1006 	{
1007 		.compatible = "qcom,pm8058-adc",
1008 		.data = &pm8058_variant,
1009 	},
1010 	{
1011 		.compatible = "qcom,pm8921-adc",
1012 		.data = &pm8921_variant,
1013 	},
1014 	{ },
1015 };
1016 MODULE_DEVICE_TABLE(of, pm8xxx_xoadc_id_table);
1017 
1018 static struct platform_driver pm8xxx_xoadc_driver = {
1019 	.driver		= {
1020 		.name	= "pm8xxx-adc",
1021 		.of_match_table = pm8xxx_xoadc_id_table,
1022 	},
1023 	.probe		= pm8xxx_xoadc_probe,
1024 	.remove		= pm8xxx_xoadc_remove,
1025 };
1026 module_platform_driver(pm8xxx_xoadc_driver);
1027 
1028 MODULE_DESCRIPTION("PM8xxx XOADC driver");
1029 MODULE_LICENSE("GPL v2");
1030 MODULE_ALIAS("platform:pm8xxx-xoadc");
1031