1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * palmas-adc.c -- TI PALMAS GPADC. 4 * 5 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. 6 * 7 * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/err.h> 12 #include <linux/irq.h> 13 #include <linux/interrupt.h> 14 #include <linux/platform_device.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/i2c.h> 18 #include <linux/pm.h> 19 #include <linux/mfd/palmas.h> 20 #include <linux/completion.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/iio/events.h> 24 #include <linux/iio/iio.h> 25 #include <linux/iio/machine.h> 26 #include <linux/iio/driver.h> 27 28 #define MOD_NAME "palmas-gpadc" 29 #define PALMAS_ADC_CONVERSION_TIMEOUT (msecs_to_jiffies(5000)) 30 #define PALMAS_TO_BE_CALCULATED 0 31 #define PALMAS_GPADC_TRIMINVALID -1 32 33 struct palmas_gpadc_info { 34 /* calibration codes and regs */ 35 int x1; /* lower ideal code */ 36 int x2; /* higher ideal code */ 37 int v1; /* expected lower volt reading */ 38 int v2; /* expected higher volt reading */ 39 u8 trim1_reg; /* register number for lower trim */ 40 u8 trim2_reg; /* register number for upper trim */ 41 int gain; /* calculated from above (after reading trim regs) */ 42 int offset; /* calculated from above (after reading trim regs) */ 43 int gain_error; /* calculated from above (after reading trim regs) */ 44 bool is_uncalibrated; /* if channel has calibration data */ 45 }; 46 47 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \ 48 [PALMAS_ADC_CH_##_chan] = { \ 49 .x1 = _x1, \ 50 .x2 = _x2, \ 51 .v1 = _v1, \ 52 .v2 = _v2, \ 53 .gain = PALMAS_TO_BE_CALCULATED, \ 54 .offset = PALMAS_TO_BE_CALCULATED, \ 55 .gain_error = PALMAS_TO_BE_CALCULATED, \ 56 .trim1_reg = PALMAS_GPADC_TRIM##_t1, \ 57 .trim2_reg = PALMAS_GPADC_TRIM##_t2, \ 58 .is_uncalibrated = _is_uncalibrated \ 59 } 60 61 static struct palmas_gpadc_info palmas_gpadc_info[] = { 62 PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false), 63 PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false), 64 PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false), 65 PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false), 66 PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false), 67 PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false), 68 PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false), 69 PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false), 70 PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false), 71 PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false), 72 PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false), 73 PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true), 74 PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true), 75 PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true), 76 PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false), 77 PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true), 78 }; 79 80 struct palmas_adc_event { 81 bool enabled; 82 int channel; 83 enum iio_event_direction direction; 84 }; 85 86 struct palmas_gpadc_thresholds { 87 int high; 88 int low; 89 }; 90 91 /* 92 * struct palmas_gpadc - the palmas_gpadc structure 93 * @ch0_current: channel 0 current source setting 94 * 0: 0 uA 95 * 1: 5 uA 96 * 2: 15 uA 97 * 3: 20 uA 98 * @ch3_current: channel 0 current source setting 99 * 0: 0 uA 100 * 1: 10 uA 101 * 2: 400 uA 102 * 3: 800 uA 103 * @extended_delay: enable the gpadc extended delay mode 104 * @auto_conversion_period: define the auto_conversion_period 105 * @lock: Lock to protect the device state during a potential concurrent 106 * read access from userspace. Reading a raw value requires a sequence 107 * of register writes, then a wait for a completion callback, 108 * and finally a register read, during which userspace could issue 109 * another read request. This lock protects a read access from 110 * ocurring before another one has finished. 111 * 112 * This is the palmas_gpadc structure to store run-time information 113 * and pointers for this driver instance. 114 */ 115 struct palmas_gpadc { 116 struct device *dev; 117 struct palmas *palmas; 118 u8 ch0_current; 119 u8 ch3_current; 120 bool extended_delay; 121 int irq; 122 int irq_auto_0; 123 int irq_auto_1; 124 struct palmas_gpadc_info *adc_info; 125 struct completion conv_completion; 126 struct palmas_adc_event event0; 127 struct palmas_adc_event event1; 128 struct palmas_gpadc_thresholds thresholds[PALMAS_ADC_CH_MAX]; 129 int auto_conversion_period; 130 struct mutex lock; 131 }; 132 133 static struct palmas_adc_event *palmas_gpadc_get_event(struct palmas_gpadc *adc, 134 int adc_chan, 135 enum iio_event_direction dir) 136 { 137 if (adc_chan == adc->event0.channel && dir == adc->event0.direction) 138 return &adc->event0; 139 140 if (adc_chan == adc->event1.channel && dir == adc->event1.direction) 141 return &adc->event1; 142 143 return NULL; 144 } 145 146 static bool palmas_gpadc_channel_is_freerunning(struct palmas_gpadc *adc, 147 int adc_chan) 148 { 149 return palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_RISING) || 150 palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_FALLING); 151 } 152 153 /* 154 * GPADC lock issue in AUTO mode. 155 * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO 156 * mode feature. 157 * Details: 158 * When the AUTO mode is the only conversion mode enabled, if the AUTO 159 * mode feature is disabled with bit GPADC_AUTO_CTRL. AUTO_CONV1_EN = 0 160 * or bit GPADC_AUTO_CTRL. AUTO_CONV0_EN = 0 during a conversion, the 161 * conversion mechanism can be seen as locked meaning that all following 162 * conversion will give 0 as a result. Bit GPADC_STATUS.GPADC_AVAILABLE 163 * will stay at 0 meaning that GPADC is busy. An RT conversion can unlock 164 * the GPADC. 165 * 166 * Workaround(s): 167 * To avoid the lock mechanism, the workaround to follow before any stop 168 * conversion request is: 169 * Force the GPADC state machine to be ON by using the GPADC_CTRL1. 170 * GPADC_FORCE bit = 1 171 * Shutdown the GPADC AUTO conversion using 172 * GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0. 173 * After 100us, force the GPADC state machine to be OFF by using the 174 * GPADC_CTRL1. GPADC_FORCE bit = 0 175 */ 176 177 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc) 178 { 179 int ret; 180 181 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 182 PALMAS_GPADC_CTRL1, 183 PALMAS_GPADC_CTRL1_GPADC_FORCE, 184 PALMAS_GPADC_CTRL1_GPADC_FORCE); 185 if (ret < 0) { 186 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret); 187 return ret; 188 } 189 190 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 191 PALMAS_GPADC_AUTO_CTRL, 192 PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 | 193 PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0, 194 0); 195 if (ret < 0) { 196 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret); 197 return ret; 198 } 199 200 udelay(100); 201 202 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 203 PALMAS_GPADC_CTRL1, 204 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0); 205 if (ret < 0) 206 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret); 207 208 return ret; 209 } 210 211 static irqreturn_t palmas_gpadc_irq(int irq, void *data) 212 { 213 struct palmas_gpadc *adc = data; 214 215 complete(&adc->conv_completion); 216 217 return IRQ_HANDLED; 218 } 219 220 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data) 221 { 222 struct iio_dev *indio_dev = data; 223 struct palmas_gpadc *adc = iio_priv(indio_dev); 224 struct palmas_adc_event *ev; 225 226 dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq); 227 palmas_disable_auto_conversion(adc); 228 229 ev = (irq == adc->irq_auto_0) ? &adc->event0 : &adc->event1; 230 if (ev->channel != -1) { 231 enum iio_event_direction dir; 232 u64 code; 233 234 dir = ev->direction; 235 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, ev->channel, 236 IIO_EV_TYPE_THRESH, dir); 237 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev)); 238 } 239 240 return IRQ_HANDLED; 241 } 242 243 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc, 244 bool mask) 245 { 246 int ret; 247 248 if (!mask) 249 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE, 250 PALMAS_INT3_MASK, 251 PALMAS_INT3_MASK_GPADC_EOC_SW, 0); 252 else 253 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE, 254 PALMAS_INT3_MASK, 255 PALMAS_INT3_MASK_GPADC_EOC_SW, 256 PALMAS_INT3_MASK_GPADC_EOC_SW); 257 if (ret < 0) 258 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret); 259 260 return ret; 261 } 262 263 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan, 264 int enable) 265 { 266 unsigned int mask, val; 267 int ret; 268 269 if (enable) { 270 val = (adc->extended_delay 271 << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT); 272 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 273 PALMAS_GPADC_RT_CTRL, 274 PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val); 275 if (ret < 0) { 276 dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret); 277 return ret; 278 } 279 280 mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK | 281 PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK | 282 PALMAS_GPADC_CTRL1_GPADC_FORCE); 283 val = (adc->ch0_current 284 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT); 285 val |= (adc->ch3_current 286 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT); 287 val |= PALMAS_GPADC_CTRL1_GPADC_FORCE; 288 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 289 PALMAS_GPADC_CTRL1, mask, val); 290 if (ret < 0) { 291 dev_err(adc->dev, 292 "Failed to update current setting: %d\n", ret); 293 return ret; 294 } 295 296 mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK | 297 PALMAS_GPADC_SW_SELECT_SW_CONV_EN); 298 val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN); 299 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 300 PALMAS_GPADC_SW_SELECT, mask, val); 301 if (ret < 0) { 302 dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret); 303 return ret; 304 } 305 } else { 306 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 307 PALMAS_GPADC_SW_SELECT, 0); 308 if (ret < 0) 309 dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret); 310 311 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 312 PALMAS_GPADC_CTRL1, 313 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0); 314 if (ret < 0) { 315 dev_err(adc->dev, "CTRL1 update failed: %d\n", ret); 316 return ret; 317 } 318 } 319 320 return ret; 321 } 322 323 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan) 324 { 325 int ret; 326 327 if (palmas_gpadc_channel_is_freerunning(adc, adc_chan)) 328 return 0; /* ADC already running */ 329 330 ret = palmas_gpadc_enable(adc, adc_chan, true); 331 if (ret < 0) 332 return ret; 333 334 return palmas_gpadc_start_mask_interrupt(adc, 0); 335 } 336 337 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan) 338 { 339 palmas_gpadc_start_mask_interrupt(adc, 1); 340 palmas_gpadc_enable(adc, adc_chan, false); 341 } 342 343 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan) 344 { 345 int k; 346 int d1; 347 int d2; 348 int ret; 349 int gain; 350 int x1 = adc->adc_info[adc_chan].x1; 351 int x2 = adc->adc_info[adc_chan].x2; 352 int v1 = adc->adc_info[adc_chan].v1; 353 int v2 = adc->adc_info[adc_chan].v2; 354 355 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE, 356 adc->adc_info[adc_chan].trim1_reg, &d1); 357 if (ret < 0) { 358 dev_err(adc->dev, "TRIM read failed: %d\n", ret); 359 goto scrub; 360 } 361 362 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE, 363 adc->adc_info[adc_chan].trim2_reg, &d2); 364 if (ret < 0) { 365 dev_err(adc->dev, "TRIM read failed: %d\n", ret); 366 goto scrub; 367 } 368 369 /* gain error calculation */ 370 k = (1000 + (1000 * (d2 - d1)) / (x2 - x1)); 371 372 /* gain calculation */ 373 gain = ((v2 - v1) * 1000) / (x2 - x1); 374 375 adc->adc_info[adc_chan].gain_error = k; 376 adc->adc_info[adc_chan].gain = gain; 377 /* offset Calculation */ 378 adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1); 379 380 scrub: 381 return ret; 382 } 383 384 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan) 385 { 386 unsigned int val; 387 int ret; 388 389 if (palmas_gpadc_channel_is_freerunning(adc, adc_chan)) { 390 int event = (adc_chan == adc->event0.channel) ? 0 : 1; 391 unsigned int reg = (event == 0) ? 392 PALMAS_GPADC_AUTO_CONV0_LSB : 393 PALMAS_GPADC_AUTO_CONV1_LSB; 394 395 ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE, 396 reg, &val, 2); 397 if (ret < 0) { 398 dev_err(adc->dev, "AUTO_CONV%x_LSB read failed: %d\n", 399 event, ret); 400 return ret; 401 } 402 } else { 403 init_completion(&adc->conv_completion); 404 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 405 PALMAS_GPADC_SW_SELECT, 406 PALMAS_GPADC_SW_SELECT_SW_START_CONV0, 407 PALMAS_GPADC_SW_SELECT_SW_START_CONV0); 408 if (ret < 0) { 409 dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret); 410 return ret; 411 } 412 413 ret = wait_for_completion_timeout(&adc->conv_completion, 414 PALMAS_ADC_CONVERSION_TIMEOUT); 415 if (ret == 0) { 416 dev_err(adc->dev, "conversion not completed\n"); 417 return -ETIMEDOUT; 418 } 419 420 ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE, 421 PALMAS_GPADC_SW_CONV0_LSB, &val, 2); 422 if (ret < 0) { 423 dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret); 424 return ret; 425 } 426 } 427 428 ret = val & 0xFFF; 429 430 return ret; 431 } 432 433 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc, 434 int adc_chan, int val) 435 { 436 if (!adc->adc_info[adc_chan].is_uncalibrated) 437 val = (val*1000 - adc->adc_info[adc_chan].offset) / 438 adc->adc_info[adc_chan].gain_error; 439 440 if (val < 0) { 441 if (val < -10) 442 dev_err(adc->dev, "Mismatch with calibration var = %d\n", val); 443 return 0; 444 } 445 446 val = (val * adc->adc_info[adc_chan].gain) / 1000; 447 448 return val; 449 } 450 451 /* 452 * The high and low threshold values are calculated based on the advice given 453 * in TI Application Report SLIA087A, "Guide to Using the GPADC in PS65903x, 454 * TPS65917-Q1, TPS65919-Q1, and TPS65916 Devices". This document recommend 455 * taking ADC tolerances into account and is based on the device integral non- 456 * linearity (INL), offset error and gain error: 457 * 458 * raw high threshold = (ideal threshold + INL) * gain error + offset error 459 * 460 * The gain error include both gain error, as specified in the datasheet, and 461 * the gain error drift. These paramenters vary depending on device and whether 462 * the the channel is calibrated (trimmed) or not. 463 */ 464 static int palmas_gpadc_threshold_with_tolerance(int val, const int INL, 465 const int gain_error, 466 const int offset_error) 467 { 468 val = ((val + INL) * (1000 + gain_error)) / 1000 + offset_error; 469 470 return clamp(val, 0, 0xFFF); 471 } 472 473 /* 474 * The values below are taken from the datasheet of TWL6035, TWL6037. 475 * todo: get max INL, gain error, and offset error from OF. 476 */ 477 static int palmas_gpadc_get_high_threshold_raw(struct palmas_gpadc *adc, 478 struct palmas_adc_event *ev) 479 { 480 const int adc_chan = ev->channel; 481 int val = adc->thresholds[adc_chan].high; 482 /* integral nonlinearity, measured in LSB */ 483 const int max_INL = 2; 484 /* measured in LSB */ 485 int max_offset_error; 486 /* 0.2% when calibrated */ 487 int max_gain_error = 2; 488 489 val = (val * 1000) / adc->adc_info[adc_chan].gain; 490 491 if (adc->adc_info[adc_chan].is_uncalibrated) { 492 /* 2% worse */ 493 max_gain_error += 20; 494 max_offset_error = 36; 495 } else { 496 val = (val * adc->adc_info[adc_chan].gain_error + 497 adc->adc_info[adc_chan].offset) / 498 1000; 499 max_offset_error = 2; 500 } 501 502 return palmas_gpadc_threshold_with_tolerance(val, 503 max_INL, 504 max_gain_error, 505 max_offset_error); 506 } 507 508 /* 509 * The values below are taken from the datasheet of TWL6035, TWL6037. 510 * todo: get min INL, gain error, and offset error from OF. 511 */ 512 static int palmas_gpadc_get_low_threshold_raw(struct palmas_gpadc *adc, 513 struct palmas_adc_event *ev) 514 { 515 const int adc_chan = ev->channel; 516 int val = adc->thresholds[adc_chan].low; 517 /* integral nonlinearity, measured in LSB */ 518 const int min_INL = -2; 519 /* measured in LSB */ 520 int min_offset_error; 521 /* -0.6% when calibrated */ 522 int min_gain_error = -6; 523 524 val = (val * 1000) / adc->adc_info[adc_chan].gain; 525 526 if (adc->adc_info[adc_chan].is_uncalibrated) { 527 /* 2% worse */ 528 min_gain_error -= 20; 529 min_offset_error = -36; 530 } else { 531 val = (val * adc->adc_info[adc_chan].gain_error - 532 adc->adc_info[adc_chan].offset) / 533 1000; 534 min_offset_error = -2; 535 } 536 537 return palmas_gpadc_threshold_with_tolerance(val, 538 min_INL, 539 min_gain_error, 540 min_offset_error); 541 } 542 543 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev, 544 struct iio_chan_spec const *chan, int *val, int *val2, long mask) 545 { 546 struct palmas_gpadc *adc = iio_priv(indio_dev); 547 int adc_chan = chan->channel; 548 int ret = 0; 549 550 if (adc_chan > PALMAS_ADC_CH_MAX) 551 return -EINVAL; 552 553 mutex_lock(&adc->lock); 554 555 switch (mask) { 556 case IIO_CHAN_INFO_RAW: 557 case IIO_CHAN_INFO_PROCESSED: 558 ret = palmas_gpadc_read_prepare(adc, adc_chan); 559 if (ret < 0) 560 goto out; 561 562 ret = palmas_gpadc_start_conversion(adc, adc_chan); 563 if (ret < 0) { 564 dev_err(adc->dev, 565 "ADC start conversion failed\n"); 566 goto out; 567 } 568 569 if (mask == IIO_CHAN_INFO_PROCESSED) 570 ret = palmas_gpadc_get_calibrated_code( 571 adc, adc_chan, ret); 572 573 *val = ret; 574 575 ret = IIO_VAL_INT; 576 goto out; 577 } 578 579 mutex_unlock(&adc->lock); 580 return ret; 581 582 out: 583 palmas_gpadc_read_done(adc, adc_chan); 584 mutex_unlock(&adc->lock); 585 586 return ret; 587 } 588 589 static int palmas_gpadc_read_event_config(struct iio_dev *indio_dev, 590 const struct iio_chan_spec *chan, 591 enum iio_event_type type, 592 enum iio_event_direction dir) 593 { 594 struct palmas_gpadc *adc = iio_priv(indio_dev); 595 int adc_chan = chan->channel; 596 int ret = 0; 597 598 if (adc_chan > PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH) 599 return -EINVAL; 600 601 mutex_lock(&adc->lock); 602 603 if (palmas_gpadc_get_event(adc, adc_chan, dir)) 604 ret = 1; 605 606 mutex_unlock(&adc->lock); 607 608 return ret; 609 } 610 611 static int palmas_adc_configure_events(struct palmas_gpadc *adc); 612 static int palmas_adc_reset_events(struct palmas_gpadc *adc); 613 614 static int palmas_gpadc_reconfigure_event_channels(struct palmas_gpadc *adc) 615 { 616 return (adc->event0.enabled || adc->event1.enabled) ? 617 palmas_adc_configure_events(adc) : 618 palmas_adc_reset_events(adc); 619 } 620 621 static int palmas_gpadc_enable_event_config(struct palmas_gpadc *adc, 622 const struct iio_chan_spec *chan, 623 enum iio_event_direction dir) 624 { 625 struct palmas_adc_event *ev; 626 int adc_chan = chan->channel; 627 628 if (palmas_gpadc_get_event(adc, adc_chan, dir)) 629 /* already enabled */ 630 return 0; 631 632 if (adc->event0.channel == -1) { 633 ev = &adc->event0; 634 } else if (adc->event1.channel == -1) { 635 /* event0 has to be the lowest channel */ 636 if (adc_chan < adc->event0.channel) { 637 adc->event1 = adc->event0; 638 ev = &adc->event0; 639 } else { 640 ev = &adc->event1; 641 } 642 } else { /* both AUTO channels already in use */ 643 dev_warn(adc->dev, "event0 - %d, event1 - %d\n", 644 adc->event0.channel, adc->event1.channel); 645 return -EBUSY; 646 } 647 648 ev->enabled = true; 649 ev->channel = adc_chan; 650 ev->direction = dir; 651 652 return palmas_gpadc_reconfigure_event_channels(adc); 653 } 654 655 static int palmas_gpadc_disable_event_config(struct palmas_gpadc *adc, 656 const struct iio_chan_spec *chan, 657 enum iio_event_direction dir) 658 { 659 int adc_chan = chan->channel; 660 struct palmas_adc_event *ev = palmas_gpadc_get_event(adc, adc_chan, dir); 661 662 if (!ev) 663 return 0; 664 665 if (ev == &adc->event0) { 666 adc->event0 = adc->event1; 667 ev = &adc->event1; 668 } 669 670 ev->enabled = false; 671 ev->channel = -1; 672 ev->direction = IIO_EV_DIR_NONE; 673 674 return palmas_gpadc_reconfigure_event_channels(adc); 675 } 676 677 static int palmas_gpadc_write_event_config(struct iio_dev *indio_dev, 678 const struct iio_chan_spec *chan, 679 enum iio_event_type type, 680 enum iio_event_direction dir, 681 int state) 682 { 683 struct palmas_gpadc *adc = iio_priv(indio_dev); 684 int adc_chan = chan->channel; 685 int ret; 686 687 if (adc_chan > PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH) 688 return -EINVAL; 689 690 mutex_lock(&adc->lock); 691 692 if (state) 693 ret = palmas_gpadc_enable_event_config(adc, chan, dir); 694 else 695 ret = palmas_gpadc_disable_event_config(adc, chan, dir); 696 697 mutex_unlock(&adc->lock); 698 699 return ret; 700 } 701 702 static int palmas_gpadc_read_event_value(struct iio_dev *indio_dev, 703 const struct iio_chan_spec *chan, 704 enum iio_event_type type, 705 enum iio_event_direction dir, 706 enum iio_event_info info, 707 int *val, int *val2) 708 { 709 struct palmas_gpadc *adc = iio_priv(indio_dev); 710 int adc_chan = chan->channel; 711 int ret; 712 713 if (adc_chan > PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH) 714 return -EINVAL; 715 716 mutex_lock(&adc->lock); 717 718 switch (info) { 719 case IIO_EV_INFO_VALUE: 720 *val = (dir == IIO_EV_DIR_RISING) ? 721 adc->thresholds[adc_chan].high : 722 adc->thresholds[adc_chan].low; 723 ret = IIO_VAL_INT; 724 break; 725 default: 726 ret = -EINVAL; 727 break; 728 } 729 730 mutex_unlock(&adc->lock); 731 732 return ret; 733 } 734 735 static int palmas_gpadc_write_event_value(struct iio_dev *indio_dev, 736 const struct iio_chan_spec *chan, 737 enum iio_event_type type, 738 enum iio_event_direction dir, 739 enum iio_event_info info, 740 int val, int val2) 741 { 742 struct palmas_gpadc *adc = iio_priv(indio_dev); 743 int adc_chan = chan->channel; 744 int old; 745 int ret; 746 747 if (adc_chan > PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH) 748 return -EINVAL; 749 750 mutex_lock(&adc->lock); 751 switch (info) { 752 case IIO_EV_INFO_VALUE: 753 if (val < 0 || val > 0xFFF) { 754 ret = -EINVAL; 755 goto out_unlock; 756 } 757 if (dir == IIO_EV_DIR_RISING) { 758 old = adc->thresholds[adc_chan].high; 759 adc->thresholds[adc_chan].high = val; 760 } else { 761 old = adc->thresholds[adc_chan].low; 762 adc->thresholds[adc_chan].low = val; 763 } 764 ret = 0; 765 break; 766 default: 767 ret = -EINVAL; 768 goto out_unlock; 769 } 770 771 if (val != old && palmas_gpadc_get_event(adc, adc_chan, dir)) 772 ret = palmas_gpadc_reconfigure_event_channels(adc); 773 774 out_unlock: 775 mutex_unlock(&adc->lock); 776 777 return ret; 778 } 779 780 static const struct iio_info palmas_gpadc_iio_info = { 781 .read_raw = palmas_gpadc_read_raw, 782 .read_event_config = palmas_gpadc_read_event_config, 783 .write_event_config = palmas_gpadc_write_event_config, 784 .read_event_value = palmas_gpadc_read_event_value, 785 .write_event_value = palmas_gpadc_write_event_value, 786 }; 787 788 static const struct iio_event_spec palmas_gpadc_events[] = { 789 { 790 .type = IIO_EV_TYPE_THRESH, 791 .dir = IIO_EV_DIR_RISING, 792 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 793 BIT(IIO_EV_INFO_ENABLE), 794 }, { 795 .type = IIO_EV_TYPE_THRESH, 796 .dir = IIO_EV_DIR_FALLING, 797 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 798 BIT(IIO_EV_INFO_ENABLE), 799 }, 800 }; 801 802 #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \ 803 { \ 804 .datasheet_name = PALMAS_DATASHEET_NAME(chan), \ 805 .type = _type, \ 806 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 807 BIT(chan_info), \ 808 .indexed = 1, \ 809 .channel = PALMAS_ADC_CH_##chan, \ 810 .event_spec = palmas_gpadc_events, \ 811 .num_event_specs = ARRAY_SIZE(palmas_gpadc_events) \ 812 } 813 814 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = { 815 PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 816 PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW), 817 PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 818 PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW), 819 PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 820 PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 821 PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 822 PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 823 PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 824 PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 825 PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 826 PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 827 PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW), 828 PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW), 829 PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 830 PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 831 }; 832 833 static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev, 834 struct palmas_gpadc_platform_data **gpadc_pdata) 835 { 836 struct device_node *np = pdev->dev.of_node; 837 struct palmas_gpadc_platform_data *gp_data; 838 int ret; 839 u32 pval; 840 841 gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL); 842 if (!gp_data) 843 return -ENOMEM; 844 845 ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval); 846 if (!ret) 847 gp_data->ch0_current = pval; 848 849 ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval); 850 if (!ret) 851 gp_data->ch3_current = pval; 852 853 gp_data->extended_delay = of_property_read_bool(np, 854 "ti,enable-extended-delay"); 855 856 *gpadc_pdata = gp_data; 857 858 return 0; 859 } 860 861 static void palmas_gpadc_reset(void *data) 862 { 863 struct palmas_gpadc *adc = data; 864 if (adc->event0.enabled || adc->event1.enabled) 865 palmas_adc_reset_events(adc); 866 } 867 868 static int palmas_gpadc_probe(struct platform_device *pdev) 869 { 870 struct palmas_gpadc *adc; 871 struct palmas_platform_data *pdata; 872 struct palmas_gpadc_platform_data *gpadc_pdata = NULL; 873 struct iio_dev *indio_dev; 874 int ret, i; 875 876 pdata = dev_get_platdata(pdev->dev.parent); 877 878 if (pdata && pdata->gpadc_pdata) 879 gpadc_pdata = pdata->gpadc_pdata; 880 881 if (!gpadc_pdata && pdev->dev.of_node) { 882 ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata); 883 if (ret < 0) 884 return ret; 885 } 886 if (!gpadc_pdata) 887 return -EINVAL; 888 889 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 890 if (!indio_dev) { 891 dev_err(&pdev->dev, "iio_device_alloc failed\n"); 892 return -ENOMEM; 893 } 894 895 adc = iio_priv(indio_dev); 896 adc->dev = &pdev->dev; 897 adc->palmas = dev_get_drvdata(pdev->dev.parent); 898 adc->adc_info = palmas_gpadc_info; 899 900 mutex_init(&adc->lock); 901 902 init_completion(&adc->conv_completion); 903 platform_set_drvdata(pdev, indio_dev); 904 905 adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms; 906 adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ); 907 if (adc->irq < 0) 908 return dev_err_probe(adc->dev, adc->irq, "get virq failed\n"); 909 910 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, NULL, 911 palmas_gpadc_irq, 912 IRQF_ONESHOT, dev_name(adc->dev), 913 adc); 914 if (ret < 0) 915 return dev_err_probe(adc->dev, ret, 916 "request irq %d failed\n", adc->irq); 917 918 adc->irq_auto_0 = platform_get_irq(pdev, 1); 919 if (adc->irq_auto_0 < 0) 920 return dev_err_probe(adc->dev, adc->irq_auto_0, 921 "get auto0 irq failed\n"); 922 923 ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_0, NULL, 924 palmas_gpadc_irq_auto, IRQF_ONESHOT, 925 "palmas-adc-auto-0", indio_dev); 926 if (ret < 0) 927 return dev_err_probe(adc->dev, ret, 928 "request auto0 irq %d failed\n", 929 adc->irq_auto_0); 930 931 adc->irq_auto_1 = platform_get_irq(pdev, 2); 932 if (adc->irq_auto_1 < 0) 933 return dev_err_probe(adc->dev, adc->irq_auto_1, 934 "get auto1 irq failed\n"); 935 936 ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_1, NULL, 937 palmas_gpadc_irq_auto, IRQF_ONESHOT, 938 "palmas-adc-auto-1", indio_dev); 939 if (ret < 0) 940 return dev_err_probe(adc->dev, ret, 941 "request auto1 irq %d failed\n", 942 adc->irq_auto_1); 943 944 adc->event0.enabled = false; 945 adc->event0.channel = -1; 946 adc->event0.direction = IIO_EV_DIR_NONE; 947 adc->event1.enabled = false; 948 adc->event1.channel = -1; 949 adc->event1.direction = IIO_EV_DIR_NONE; 950 951 /* set the current source 0 (value 0/5/15/20 uA => 0..3) */ 952 if (gpadc_pdata->ch0_current <= 1) 953 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0; 954 else if (gpadc_pdata->ch0_current <= 5) 955 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5; 956 else if (gpadc_pdata->ch0_current <= 15) 957 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15; 958 else 959 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20; 960 961 /* set the current source 3 (value 0/10/400/800 uA => 0..3) */ 962 if (gpadc_pdata->ch3_current <= 1) 963 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0; 964 else if (gpadc_pdata->ch3_current <= 10) 965 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10; 966 else if (gpadc_pdata->ch3_current <= 400) 967 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400; 968 else 969 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800; 970 971 adc->extended_delay = gpadc_pdata->extended_delay; 972 973 indio_dev->name = MOD_NAME; 974 indio_dev->info = &palmas_gpadc_iio_info; 975 indio_dev->modes = INDIO_DIRECT_MODE; 976 indio_dev->channels = palmas_gpadc_iio_channel; 977 indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel); 978 979 ret = devm_iio_device_register(&pdev->dev, indio_dev); 980 if (ret < 0) 981 return dev_err_probe(adc->dev, ret, 982 "iio_device_register() failed\n"); 983 984 device_set_wakeup_capable(&pdev->dev, 1); 985 for (i = 0; i < PALMAS_ADC_CH_MAX; i++) { 986 if (!(adc->adc_info[i].is_uncalibrated)) 987 palmas_gpadc_calibrate(adc, i); 988 } 989 990 ret = devm_add_action(&pdev->dev, palmas_gpadc_reset, adc); 991 if (ret) 992 return ret; 993 994 return 0; 995 } 996 997 static int palmas_adc_configure_events(struct palmas_gpadc *adc) 998 { 999 int adc_period, conv; 1000 int i; 1001 int ch0 = 0, ch1 = 0; 1002 int thres; 1003 int ret; 1004 1005 adc_period = adc->auto_conversion_period; 1006 for (i = 0; i < 16; ++i) { 1007 if (((1000 * (1 << i)) / 32) >= adc_period) 1008 break; 1009 } 1010 if (i > 0) 1011 i--; 1012 adc_period = i; 1013 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 1014 PALMAS_GPADC_AUTO_CTRL, 1015 PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK, 1016 adc_period); 1017 if (ret < 0) { 1018 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret); 1019 return ret; 1020 } 1021 1022 conv = 0; 1023 if (adc->event0.enabled) { 1024 struct palmas_adc_event *ev = &adc->event0; 1025 int polarity; 1026 1027 ch0 = ev->channel; 1028 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN; 1029 switch (ev->direction) { 1030 case IIO_EV_DIR_RISING: 1031 thres = palmas_gpadc_get_high_threshold_raw(adc, ev); 1032 polarity = 0; 1033 break; 1034 case IIO_EV_DIR_FALLING: 1035 thres = palmas_gpadc_get_low_threshold_raw(adc, ev); 1036 polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL; 1037 break; 1038 default: 1039 return -EINVAL; 1040 } 1041 1042 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1043 PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF); 1044 if (ret < 0) { 1045 dev_err(adc->dev, 1046 "THRES_CONV0_LSB write failed: %d\n", ret); 1047 return ret; 1048 } 1049 1050 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1051 PALMAS_GPADC_THRES_CONV0_MSB, 1052 ((thres >> 8) & 0xF) | polarity); 1053 if (ret < 0) { 1054 dev_err(adc->dev, 1055 "THRES_CONV0_MSB write failed: %d\n", ret); 1056 return ret; 1057 } 1058 } 1059 1060 if (adc->event1.enabled) { 1061 struct palmas_adc_event *ev = &adc->event1; 1062 int polarity; 1063 1064 ch1 = ev->channel; 1065 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN; 1066 switch (ev->direction) { 1067 case IIO_EV_DIR_RISING: 1068 thres = palmas_gpadc_get_high_threshold_raw(adc, ev); 1069 polarity = 0; 1070 break; 1071 case IIO_EV_DIR_FALLING: 1072 thres = palmas_gpadc_get_low_threshold_raw(adc, ev); 1073 polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL; 1074 break; 1075 default: 1076 return -EINVAL; 1077 } 1078 1079 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1080 PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF); 1081 if (ret < 0) { 1082 dev_err(adc->dev, 1083 "THRES_CONV1_LSB write failed: %d\n", ret); 1084 return ret; 1085 } 1086 1087 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1088 PALMAS_GPADC_THRES_CONV1_MSB, 1089 ((thres >> 8) & 0xF) | polarity); 1090 if (ret < 0) { 1091 dev_err(adc->dev, 1092 "THRES_CONV1_MSB write failed: %d\n", ret); 1093 return ret; 1094 } 1095 } 1096 1097 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1098 PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0); 1099 if (ret < 0) { 1100 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret); 1101 return ret; 1102 } 1103 1104 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 1105 PALMAS_GPADC_AUTO_CTRL, 1106 PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN | 1107 PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv); 1108 if (ret < 0) 1109 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret); 1110 1111 return ret; 1112 } 1113 1114 static int palmas_adc_reset_events(struct palmas_gpadc *adc) 1115 { 1116 int ret; 1117 1118 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1119 PALMAS_GPADC_AUTO_SELECT, 0); 1120 if (ret < 0) { 1121 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret); 1122 return ret; 1123 } 1124 1125 ret = palmas_disable_auto_conversion(adc); 1126 if (ret < 0) 1127 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret); 1128 1129 return ret; 1130 } 1131 1132 static int palmas_gpadc_suspend(struct device *dev) 1133 { 1134 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1135 struct palmas_gpadc *adc = iio_priv(indio_dev); 1136 1137 if (!device_may_wakeup(dev)) 1138 return 0; 1139 1140 if (adc->event0.enabled) 1141 enable_irq_wake(adc->irq_auto_0); 1142 1143 if (adc->event1.enabled) 1144 enable_irq_wake(adc->irq_auto_1); 1145 1146 return 0; 1147 } 1148 1149 static int palmas_gpadc_resume(struct device *dev) 1150 { 1151 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1152 struct palmas_gpadc *adc = iio_priv(indio_dev); 1153 1154 if (!device_may_wakeup(dev)) 1155 return 0; 1156 1157 if (adc->event0.enabled) 1158 disable_irq_wake(adc->irq_auto_0); 1159 1160 if (adc->event1.enabled) 1161 disable_irq_wake(adc->irq_auto_1); 1162 1163 return 0; 1164 }; 1165 1166 static DEFINE_SIMPLE_DEV_PM_OPS(palmas_pm_ops, palmas_gpadc_suspend, 1167 palmas_gpadc_resume); 1168 1169 static const struct of_device_id of_palmas_gpadc_match_tbl[] = { 1170 { .compatible = "ti,palmas-gpadc", }, 1171 { /* end */ } 1172 }; 1173 MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl); 1174 1175 static struct platform_driver palmas_gpadc_driver = { 1176 .probe = palmas_gpadc_probe, 1177 .driver = { 1178 .name = MOD_NAME, 1179 .pm = pm_sleep_ptr(&palmas_pm_ops), 1180 .of_match_table = of_palmas_gpadc_match_tbl, 1181 }, 1182 }; 1183 module_platform_driver(palmas_gpadc_driver); 1184 1185 MODULE_DESCRIPTION("palmas GPADC driver"); 1186 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>"); 1187 MODULE_ALIAS("platform:palmas-gpadc"); 1188 MODULE_LICENSE("GPL v2"); 1189