1 /* 2 * palmas-adc.c -- TI PALMAS GPADC. 3 * 4 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. 5 * 6 * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/err.h> 15 #include <linux/irq.h> 16 #include <linux/interrupt.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/i2c.h> 21 #include <linux/pm.h> 22 #include <linux/mfd/palmas.h> 23 #include <linux/completion.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/iio/iio.h> 27 #include <linux/iio/machine.h> 28 #include <linux/iio/driver.h> 29 30 #define MOD_NAME "palmas-gpadc" 31 #define PALMAS_ADC_CONVERSION_TIMEOUT (msecs_to_jiffies(5000)) 32 #define PALMAS_TO_BE_CALCULATED 0 33 #define PALMAS_GPADC_TRIMINVALID -1 34 35 struct palmas_gpadc_info { 36 /* calibration codes and regs */ 37 int x1; /* lower ideal code */ 38 int x2; /* higher ideal code */ 39 int v1; /* expected lower volt reading */ 40 int v2; /* expected higher volt reading */ 41 u8 trim1_reg; /* register number for lower trim */ 42 u8 trim2_reg; /* register number for upper trim */ 43 int gain; /* calculated from above (after reading trim regs) */ 44 int offset; /* calculated from above (after reading trim regs) */ 45 int gain_error; /* calculated from above (after reading trim regs) */ 46 bool is_uncalibrated; /* if channel has calibration data */ 47 }; 48 49 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \ 50 [PALMAS_ADC_CH_##_chan] = { \ 51 .x1 = _x1, \ 52 .x2 = _x2, \ 53 .v1 = _v1, \ 54 .v2 = _v2, \ 55 .gain = PALMAS_TO_BE_CALCULATED, \ 56 .offset = PALMAS_TO_BE_CALCULATED, \ 57 .gain_error = PALMAS_TO_BE_CALCULATED, \ 58 .trim1_reg = PALMAS_GPADC_TRIM##_t1, \ 59 .trim2_reg = PALMAS_GPADC_TRIM##_t2, \ 60 .is_uncalibrated = _is_uncalibrated \ 61 } 62 63 static struct palmas_gpadc_info palmas_gpadc_info[] = { 64 PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false), 65 PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false), 66 PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false), 67 PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false), 68 PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false), 69 PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false), 70 PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false), 71 PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false), 72 PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false), 73 PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false), 74 PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false), 75 PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true), 76 PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true), 77 PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true), 78 PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false), 79 PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true), 80 }; 81 82 /** 83 * struct palmas_gpadc - the palmas_gpadc structure 84 * @ch0_current: channel 0 current source setting 85 * 0: 0 uA 86 * 1: 5 uA 87 * 2: 15 uA 88 * 3: 20 uA 89 * @ch3_current: channel 0 current source setting 90 * 0: 0 uA 91 * 1: 10 uA 92 * 2: 400 uA 93 * 3: 800 uA 94 * @extended_delay: enable the gpadc extended delay mode 95 * @auto_conversion_period: define the auto_conversion_period 96 * 97 * This is the palmas_gpadc structure to store run-time information 98 * and pointers for this driver instance. 99 */ 100 101 struct palmas_gpadc { 102 struct device *dev; 103 struct palmas *palmas; 104 u8 ch0_current; 105 u8 ch3_current; 106 bool extended_delay; 107 int irq; 108 int irq_auto_0; 109 int irq_auto_1; 110 struct palmas_gpadc_info *adc_info; 111 struct completion conv_completion; 112 struct palmas_adc_wakeup_property wakeup1_data; 113 struct palmas_adc_wakeup_property wakeup2_data; 114 bool wakeup1_enable; 115 bool wakeup2_enable; 116 int auto_conversion_period; 117 }; 118 119 /* 120 * GPADC lock issue in AUTO mode. 121 * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO 122 * mode feature. 123 * Details: 124 * When the AUTO mode is the only conversion mode enabled, if the AUTO 125 * mode feature is disabled with bit GPADC_AUTO_CTRL. AUTO_CONV1_EN = 0 126 * or bit GPADC_AUTO_CTRL. AUTO_CONV0_EN = 0 during a conversion, the 127 * conversion mechanism can be seen as locked meaning that all following 128 * conversion will give 0 as a result. Bit GPADC_STATUS.GPADC_AVAILABLE 129 * will stay at 0 meaning that GPADC is busy. An RT conversion can unlock 130 * the GPADC. 131 * 132 * Workaround(s): 133 * To avoid the lock mechanism, the workaround to follow before any stop 134 * conversion request is: 135 * Force the GPADC state machine to be ON by using the GPADC_CTRL1. 136 * GPADC_FORCE bit = 1 137 * Shutdown the GPADC AUTO conversion using 138 * GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0. 139 * After 100us, force the GPADC state machine to be OFF by using the 140 * GPADC_CTRL1. GPADC_FORCE bit = 0 141 */ 142 143 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc) 144 { 145 int ret; 146 147 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 148 PALMAS_GPADC_CTRL1, 149 PALMAS_GPADC_CTRL1_GPADC_FORCE, 150 PALMAS_GPADC_CTRL1_GPADC_FORCE); 151 if (ret < 0) { 152 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret); 153 return ret; 154 } 155 156 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 157 PALMAS_GPADC_AUTO_CTRL, 158 PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 | 159 PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0, 160 0); 161 if (ret < 0) { 162 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret); 163 return ret; 164 } 165 166 udelay(100); 167 168 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 169 PALMAS_GPADC_CTRL1, 170 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0); 171 if (ret < 0) 172 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret); 173 174 return ret; 175 } 176 177 static irqreturn_t palmas_gpadc_irq(int irq, void *data) 178 { 179 struct palmas_gpadc *adc = data; 180 181 complete(&adc->conv_completion); 182 183 return IRQ_HANDLED; 184 } 185 186 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data) 187 { 188 struct palmas_gpadc *adc = data; 189 190 dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq); 191 palmas_disable_auto_conversion(adc); 192 193 return IRQ_HANDLED; 194 } 195 196 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc, 197 bool mask) 198 { 199 int ret; 200 201 if (!mask) 202 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE, 203 PALMAS_INT3_MASK, 204 PALMAS_INT3_MASK_GPADC_EOC_SW, 0); 205 else 206 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE, 207 PALMAS_INT3_MASK, 208 PALMAS_INT3_MASK_GPADC_EOC_SW, 209 PALMAS_INT3_MASK_GPADC_EOC_SW); 210 if (ret < 0) 211 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret); 212 213 return ret; 214 } 215 216 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan, 217 int enable) 218 { 219 unsigned int mask, val; 220 int ret; 221 222 if (enable) { 223 val = (adc->extended_delay 224 << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT); 225 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 226 PALMAS_GPADC_RT_CTRL, 227 PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val); 228 if (ret < 0) { 229 dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret); 230 return ret; 231 } 232 233 mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK | 234 PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK | 235 PALMAS_GPADC_CTRL1_GPADC_FORCE); 236 val = (adc->ch0_current 237 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT); 238 val |= (adc->ch3_current 239 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT); 240 val |= PALMAS_GPADC_CTRL1_GPADC_FORCE; 241 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 242 PALMAS_GPADC_CTRL1, mask, val); 243 if (ret < 0) { 244 dev_err(adc->dev, 245 "Failed to update current setting: %d\n", ret); 246 return ret; 247 } 248 249 mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK | 250 PALMAS_GPADC_SW_SELECT_SW_CONV_EN); 251 val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN); 252 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 253 PALMAS_GPADC_SW_SELECT, mask, val); 254 if (ret < 0) { 255 dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret); 256 return ret; 257 } 258 } else { 259 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 260 PALMAS_GPADC_SW_SELECT, 0); 261 if (ret < 0) 262 dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret); 263 264 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 265 PALMAS_GPADC_CTRL1, 266 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0); 267 if (ret < 0) { 268 dev_err(adc->dev, "CTRL1 update failed: %d\n", ret); 269 return ret; 270 } 271 } 272 273 return ret; 274 } 275 276 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan) 277 { 278 int ret; 279 280 ret = palmas_gpadc_enable(adc, adc_chan, true); 281 if (ret < 0) 282 return ret; 283 284 return palmas_gpadc_start_mask_interrupt(adc, 0); 285 } 286 287 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan) 288 { 289 palmas_gpadc_start_mask_interrupt(adc, 1); 290 palmas_gpadc_enable(adc, adc_chan, false); 291 } 292 293 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan) 294 { 295 int k; 296 int d1; 297 int d2; 298 int ret; 299 int gain; 300 int x1 = adc->adc_info[adc_chan].x1; 301 int x2 = adc->adc_info[adc_chan].x2; 302 int v1 = adc->adc_info[adc_chan].v1; 303 int v2 = adc->adc_info[adc_chan].v2; 304 305 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE, 306 adc->adc_info[adc_chan].trim1_reg, &d1); 307 if (ret < 0) { 308 dev_err(adc->dev, "TRIM read failed: %d\n", ret); 309 goto scrub; 310 } 311 312 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE, 313 adc->adc_info[adc_chan].trim2_reg, &d2); 314 if (ret < 0) { 315 dev_err(adc->dev, "TRIM read failed: %d\n", ret); 316 goto scrub; 317 } 318 319 /* gain error calculation */ 320 k = (1000 + (1000 * (d2 - d1)) / (x2 - x1)); 321 322 /* gain calculation */ 323 gain = ((v2 - v1) * 1000) / (x2 - x1); 324 325 adc->adc_info[adc_chan].gain_error = k; 326 adc->adc_info[adc_chan].gain = gain; 327 /* offset Calculation */ 328 adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1); 329 330 scrub: 331 return ret; 332 } 333 334 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan) 335 { 336 unsigned int val; 337 int ret; 338 339 init_completion(&adc->conv_completion); 340 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 341 PALMAS_GPADC_SW_SELECT, 342 PALMAS_GPADC_SW_SELECT_SW_START_CONV0, 343 PALMAS_GPADC_SW_SELECT_SW_START_CONV0); 344 if (ret < 0) { 345 dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret); 346 return ret; 347 } 348 349 ret = wait_for_completion_timeout(&adc->conv_completion, 350 PALMAS_ADC_CONVERSION_TIMEOUT); 351 if (ret == 0) { 352 dev_err(adc->dev, "conversion not completed\n"); 353 return -ETIMEDOUT; 354 } 355 356 ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE, 357 PALMAS_GPADC_SW_CONV0_LSB, &val, 2); 358 if (ret < 0) { 359 dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret); 360 return ret; 361 } 362 363 ret = val & 0xFFF; 364 365 return ret; 366 } 367 368 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc, 369 int adc_chan, int val) 370 { 371 if (!adc->adc_info[adc_chan].is_uncalibrated) 372 val = (val*1000 - adc->adc_info[adc_chan].offset) / 373 adc->adc_info[adc_chan].gain_error; 374 375 if (val < 0) { 376 dev_err(adc->dev, "Mismatch with calibration\n"); 377 return 0; 378 } 379 380 val = (val * adc->adc_info[adc_chan].gain) / 1000; 381 382 return val; 383 } 384 385 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev, 386 struct iio_chan_spec const *chan, int *val, int *val2, long mask) 387 { 388 struct palmas_gpadc *adc = iio_priv(indio_dev); 389 int adc_chan = chan->channel; 390 int ret = 0; 391 392 if (adc_chan > PALMAS_ADC_CH_MAX) 393 return -EINVAL; 394 395 mutex_lock(&indio_dev->mlock); 396 397 switch (mask) { 398 case IIO_CHAN_INFO_RAW: 399 case IIO_CHAN_INFO_PROCESSED: 400 ret = palmas_gpadc_read_prepare(adc, adc_chan); 401 if (ret < 0) 402 goto out; 403 404 ret = palmas_gpadc_start_conversion(adc, adc_chan); 405 if (ret < 0) { 406 dev_err(adc->dev, 407 "ADC start conversion failed\n"); 408 goto out; 409 } 410 411 if (mask == IIO_CHAN_INFO_PROCESSED) 412 ret = palmas_gpadc_get_calibrated_code( 413 adc, adc_chan, ret); 414 415 *val = ret; 416 417 ret = IIO_VAL_INT; 418 goto out; 419 } 420 421 mutex_unlock(&indio_dev->mlock); 422 return ret; 423 424 out: 425 palmas_gpadc_read_done(adc, adc_chan); 426 mutex_unlock(&indio_dev->mlock); 427 428 return ret; 429 } 430 431 static const struct iio_info palmas_gpadc_iio_info = { 432 .read_raw = palmas_gpadc_read_raw, 433 }; 434 435 #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \ 436 { \ 437 .datasheet_name = PALMAS_DATASHEET_NAME(chan), \ 438 .type = _type, \ 439 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 440 BIT(chan_info), \ 441 .indexed = 1, \ 442 .channel = PALMAS_ADC_CH_##chan, \ 443 } 444 445 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = { 446 PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 447 PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW), 448 PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 449 PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW), 450 PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 451 PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 452 PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 453 PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 454 PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 455 PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 456 PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 457 PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 458 PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW), 459 PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW), 460 PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 461 PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 462 }; 463 464 static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev, 465 struct palmas_gpadc_platform_data **gpadc_pdata) 466 { 467 struct device_node *np = pdev->dev.of_node; 468 struct palmas_gpadc_platform_data *gp_data; 469 int ret; 470 u32 pval; 471 472 gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL); 473 if (!gp_data) 474 return -ENOMEM; 475 476 ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval); 477 if (!ret) 478 gp_data->ch0_current = pval; 479 480 ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval); 481 if (!ret) 482 gp_data->ch3_current = pval; 483 484 gp_data->extended_delay = of_property_read_bool(np, 485 "ti,enable-extended-delay"); 486 487 *gpadc_pdata = gp_data; 488 489 return 0; 490 } 491 492 static int palmas_gpadc_probe(struct platform_device *pdev) 493 { 494 struct palmas_gpadc *adc; 495 struct palmas_platform_data *pdata; 496 struct palmas_gpadc_platform_data *gpadc_pdata = NULL; 497 struct iio_dev *indio_dev; 498 int ret, i; 499 500 pdata = dev_get_platdata(pdev->dev.parent); 501 502 if (pdata && pdata->gpadc_pdata) 503 gpadc_pdata = pdata->gpadc_pdata; 504 505 if (!gpadc_pdata && pdev->dev.of_node) { 506 ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata); 507 if (ret < 0) 508 return ret; 509 } 510 if (!gpadc_pdata) 511 return -EINVAL; 512 513 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 514 if (!indio_dev) { 515 dev_err(&pdev->dev, "iio_device_alloc failed\n"); 516 return -ENOMEM; 517 } 518 519 adc = iio_priv(indio_dev); 520 adc->dev = &pdev->dev; 521 adc->palmas = dev_get_drvdata(pdev->dev.parent); 522 adc->adc_info = palmas_gpadc_info; 523 init_completion(&adc->conv_completion); 524 dev_set_drvdata(&pdev->dev, indio_dev); 525 526 adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms; 527 adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ); 528 if (adc->irq < 0) { 529 dev_err(adc->dev, 530 "get virq failed: %d\n", adc->irq); 531 ret = adc->irq; 532 goto out; 533 } 534 ret = request_threaded_irq(adc->irq, NULL, 535 palmas_gpadc_irq, 536 IRQF_ONESHOT, dev_name(adc->dev), 537 adc); 538 if (ret < 0) { 539 dev_err(adc->dev, 540 "request irq %d failed: %d\n", adc->irq, ret); 541 goto out; 542 } 543 544 if (gpadc_pdata->adc_wakeup1_data) { 545 memcpy(&adc->wakeup1_data, gpadc_pdata->adc_wakeup1_data, 546 sizeof(adc->wakeup1_data)); 547 adc->wakeup1_enable = true; 548 adc->irq_auto_0 = platform_get_irq(pdev, 1); 549 ret = request_threaded_irq(adc->irq_auto_0, NULL, 550 palmas_gpadc_irq_auto, 551 IRQF_ONESHOT, 552 "palmas-adc-auto-0", adc); 553 if (ret < 0) { 554 dev_err(adc->dev, "request auto0 irq %d failed: %d\n", 555 adc->irq_auto_0, ret); 556 goto out_irq_free; 557 } 558 } 559 560 if (gpadc_pdata->adc_wakeup2_data) { 561 memcpy(&adc->wakeup2_data, gpadc_pdata->adc_wakeup2_data, 562 sizeof(adc->wakeup2_data)); 563 adc->wakeup2_enable = true; 564 adc->irq_auto_1 = platform_get_irq(pdev, 2); 565 ret = request_threaded_irq(adc->irq_auto_1, NULL, 566 palmas_gpadc_irq_auto, 567 IRQF_ONESHOT, 568 "palmas-adc-auto-1", adc); 569 if (ret < 0) { 570 dev_err(adc->dev, "request auto1 irq %d failed: %d\n", 571 adc->irq_auto_1, ret); 572 goto out_irq_auto0_free; 573 } 574 } 575 576 /* set the current source 0 (value 0/5/15/20 uA => 0..3) */ 577 if (gpadc_pdata->ch0_current <= 1) 578 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0; 579 else if (gpadc_pdata->ch0_current <= 5) 580 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5; 581 else if (gpadc_pdata->ch0_current <= 15) 582 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15; 583 else 584 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20; 585 586 /* set the current source 3 (value 0/10/400/800 uA => 0..3) */ 587 if (gpadc_pdata->ch3_current <= 1) 588 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0; 589 else if (gpadc_pdata->ch3_current <= 10) 590 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10; 591 else if (gpadc_pdata->ch3_current <= 400) 592 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400; 593 else 594 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800; 595 596 adc->extended_delay = gpadc_pdata->extended_delay; 597 598 indio_dev->name = MOD_NAME; 599 indio_dev->dev.parent = &pdev->dev; 600 indio_dev->info = &palmas_gpadc_iio_info; 601 indio_dev->modes = INDIO_DIRECT_MODE; 602 indio_dev->channels = palmas_gpadc_iio_channel; 603 indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel); 604 605 ret = iio_device_register(indio_dev); 606 if (ret < 0) { 607 dev_err(adc->dev, "iio_device_register() failed: %d\n", ret); 608 goto out_irq_auto1_free; 609 } 610 611 device_set_wakeup_capable(&pdev->dev, 1); 612 for (i = 0; i < PALMAS_ADC_CH_MAX; i++) { 613 if (!(adc->adc_info[i].is_uncalibrated)) 614 palmas_gpadc_calibrate(adc, i); 615 } 616 617 if (adc->wakeup1_enable || adc->wakeup2_enable) 618 device_wakeup_enable(&pdev->dev); 619 620 return 0; 621 622 out_irq_auto1_free: 623 if (gpadc_pdata->adc_wakeup2_data) 624 free_irq(adc->irq_auto_1, adc); 625 out_irq_auto0_free: 626 if (gpadc_pdata->adc_wakeup1_data) 627 free_irq(adc->irq_auto_0, adc); 628 out_irq_free: 629 free_irq(adc->irq, adc); 630 out: 631 return ret; 632 } 633 634 static int palmas_gpadc_remove(struct platform_device *pdev) 635 { 636 struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev); 637 struct palmas_gpadc *adc = iio_priv(indio_dev); 638 639 if (adc->wakeup1_enable || adc->wakeup2_enable) 640 device_wakeup_disable(&pdev->dev); 641 iio_device_unregister(indio_dev); 642 free_irq(adc->irq, adc); 643 if (adc->wakeup1_enable) 644 free_irq(adc->irq_auto_0, adc); 645 if (adc->wakeup2_enable) 646 free_irq(adc->irq_auto_1, adc); 647 648 return 0; 649 } 650 651 #ifdef CONFIG_PM_SLEEP 652 static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc) 653 { 654 int adc_period, conv; 655 int i; 656 int ch0 = 0, ch1 = 0; 657 int thres; 658 int ret; 659 660 adc_period = adc->auto_conversion_period; 661 for (i = 0; i < 16; ++i) { 662 if (((1000 * (1 << i)) / 32) < adc_period) 663 continue; 664 } 665 if (i > 0) 666 i--; 667 adc_period = i; 668 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 669 PALMAS_GPADC_AUTO_CTRL, 670 PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK, 671 adc_period); 672 if (ret < 0) { 673 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret); 674 return ret; 675 } 676 677 conv = 0; 678 if (adc->wakeup1_enable) { 679 int polarity; 680 681 ch0 = adc->wakeup1_data.adc_channel_number; 682 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN; 683 if (adc->wakeup1_data.adc_high_threshold > 0) { 684 thres = adc->wakeup1_data.adc_high_threshold; 685 polarity = 0; 686 } else { 687 thres = adc->wakeup1_data.adc_low_threshold; 688 polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL; 689 } 690 691 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 692 PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF); 693 if (ret < 0) { 694 dev_err(adc->dev, 695 "THRES_CONV0_LSB write failed: %d\n", ret); 696 return ret; 697 } 698 699 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 700 PALMAS_GPADC_THRES_CONV0_MSB, 701 ((thres >> 8) & 0xF) | polarity); 702 if (ret < 0) { 703 dev_err(adc->dev, 704 "THRES_CONV0_MSB write failed: %d\n", ret); 705 return ret; 706 } 707 } 708 709 if (adc->wakeup2_enable) { 710 int polarity; 711 712 ch1 = adc->wakeup2_data.adc_channel_number; 713 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN; 714 if (adc->wakeup2_data.adc_high_threshold > 0) { 715 thres = adc->wakeup2_data.adc_high_threshold; 716 polarity = 0; 717 } else { 718 thres = adc->wakeup2_data.adc_low_threshold; 719 polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL; 720 } 721 722 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 723 PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF); 724 if (ret < 0) { 725 dev_err(adc->dev, 726 "THRES_CONV1_LSB write failed: %d\n", ret); 727 return ret; 728 } 729 730 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 731 PALMAS_GPADC_THRES_CONV1_MSB, 732 ((thres >> 8) & 0xF) | polarity); 733 if (ret < 0) { 734 dev_err(adc->dev, 735 "THRES_CONV1_MSB write failed: %d\n", ret); 736 return ret; 737 } 738 } 739 740 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 741 PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0); 742 if (ret < 0) { 743 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret); 744 return ret; 745 } 746 747 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 748 PALMAS_GPADC_AUTO_CTRL, 749 PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN | 750 PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv); 751 if (ret < 0) 752 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret); 753 754 return ret; 755 } 756 757 static int palmas_adc_wakeup_reset(struct palmas_gpadc *adc) 758 { 759 int ret; 760 761 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 762 PALMAS_GPADC_AUTO_SELECT, 0); 763 if (ret < 0) { 764 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret); 765 return ret; 766 } 767 768 ret = palmas_disable_auto_conversion(adc); 769 if (ret < 0) 770 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret); 771 772 return ret; 773 } 774 775 static int palmas_gpadc_suspend(struct device *dev) 776 { 777 struct iio_dev *indio_dev = dev_get_drvdata(dev); 778 struct palmas_gpadc *adc = iio_priv(indio_dev); 779 int wakeup = adc->wakeup1_enable || adc->wakeup2_enable; 780 int ret; 781 782 if (!device_may_wakeup(dev) || !wakeup) 783 return 0; 784 785 ret = palmas_adc_wakeup_configure(adc); 786 if (ret < 0) 787 return ret; 788 789 if (adc->wakeup1_enable) 790 enable_irq_wake(adc->irq_auto_0); 791 792 if (adc->wakeup2_enable) 793 enable_irq_wake(adc->irq_auto_1); 794 795 return 0; 796 } 797 798 static int palmas_gpadc_resume(struct device *dev) 799 { 800 struct iio_dev *indio_dev = dev_get_drvdata(dev); 801 struct palmas_gpadc *adc = iio_priv(indio_dev); 802 int wakeup = adc->wakeup1_enable || adc->wakeup2_enable; 803 int ret; 804 805 if (!device_may_wakeup(dev) || !wakeup) 806 return 0; 807 808 ret = palmas_adc_wakeup_reset(adc); 809 if (ret < 0) 810 return ret; 811 812 if (adc->wakeup1_enable) 813 disable_irq_wake(adc->irq_auto_0); 814 815 if (adc->wakeup2_enable) 816 disable_irq_wake(adc->irq_auto_1); 817 818 return 0; 819 }; 820 #endif 821 822 static const struct dev_pm_ops palmas_pm_ops = { 823 SET_SYSTEM_SLEEP_PM_OPS(palmas_gpadc_suspend, 824 palmas_gpadc_resume) 825 }; 826 827 static const struct of_device_id of_palmas_gpadc_match_tbl[] = { 828 { .compatible = "ti,palmas-gpadc", }, 829 { /* end */ } 830 }; 831 MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl); 832 833 static struct platform_driver palmas_gpadc_driver = { 834 .probe = palmas_gpadc_probe, 835 .remove = palmas_gpadc_remove, 836 .driver = { 837 .name = MOD_NAME, 838 .pm = &palmas_pm_ops, 839 .of_match_table = of_palmas_gpadc_match_tbl, 840 }, 841 }; 842 843 static int __init palmas_gpadc_init(void) 844 { 845 return platform_driver_register(&palmas_gpadc_driver); 846 } 847 module_init(palmas_gpadc_init); 848 849 static void __exit palmas_gpadc_exit(void) 850 { 851 platform_driver_unregister(&palmas_gpadc_driver); 852 } 853 module_exit(palmas_gpadc_exit); 854 855 MODULE_DESCRIPTION("palmas GPADC driver"); 856 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>"); 857 MODULE_ALIAS("platform:palmas-gpadc"); 858 MODULE_LICENSE("GPL v2"); 859