xref: /openbmc/linux/drivers/iio/adc/palmas_gpadc.c (revision 4da722ca)
1 /*
2  * palmas-adc.c -- TI PALMAS GPADC.
3  *
4  * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
5  *
6  * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation version 2.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/err.h>
15 #include <linux/irq.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/pm.h>
22 #include <linux/mfd/palmas.h>
23 #include <linux/completion.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/iio/iio.h>
27 #include <linux/iio/machine.h>
28 #include <linux/iio/driver.h>
29 
30 #define MOD_NAME "palmas-gpadc"
31 #define PALMAS_ADC_CONVERSION_TIMEOUT	(msecs_to_jiffies(5000))
32 #define PALMAS_TO_BE_CALCULATED 0
33 #define PALMAS_GPADC_TRIMINVALID	-1
34 
35 struct palmas_gpadc_info {
36 /* calibration codes and regs */
37 	int x1;	/* lower ideal code */
38 	int x2;	/* higher ideal code */
39 	int v1;	/* expected lower volt reading */
40 	int v2;	/* expected higher volt reading */
41 	u8 trim1_reg;	/* register number for lower trim */
42 	u8 trim2_reg;	/* register number for upper trim */
43 	int gain;	/* calculated from above (after reading trim regs) */
44 	int offset;	/* calculated from above (after reading trim regs) */
45 	int gain_error;	/* calculated from above (after reading trim regs) */
46 	bool is_uncalibrated;	/* if channel has calibration data */
47 };
48 
49 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \
50 	[PALMAS_ADC_CH_##_chan] = { \
51 		.x1 = _x1, \
52 		.x2 = _x2, \
53 		.v1 = _v1, \
54 		.v2 = _v2, \
55 		.gain = PALMAS_TO_BE_CALCULATED, \
56 		.offset = PALMAS_TO_BE_CALCULATED, \
57 		.gain_error = PALMAS_TO_BE_CALCULATED, \
58 		.trim1_reg = PALMAS_GPADC_TRIM##_t1, \
59 		.trim2_reg = PALMAS_GPADC_TRIM##_t2,  \
60 		.is_uncalibrated = _is_uncalibrated \
61 	}
62 
63 static struct palmas_gpadc_info palmas_gpadc_info[] = {
64 	PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false),
65 	PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false),
66 	PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false),
67 	PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false),
68 	PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false),
69 	PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false),
70 	PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false),
71 	PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false),
72 	PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false),
73 	PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false),
74 	PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false),
75 	PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true),
76 	PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true),
77 	PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true),
78 	PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false),
79 	PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true),
80 };
81 
82 /**
83  * struct palmas_gpadc - the palmas_gpadc structure
84  * @ch0_current:	channel 0 current source setting
85  *			0: 0 uA
86  *			1: 5 uA
87  *			2: 15 uA
88  *			3: 20 uA
89  * @ch3_current:	channel 0 current source setting
90  *			0: 0 uA
91  *			1: 10 uA
92  *			2: 400 uA
93  *			3: 800 uA
94  * @extended_delay:	enable the gpadc extended delay mode
95  * @auto_conversion_period:	define the auto_conversion_period
96  *
97  * This is the palmas_gpadc structure to store run-time information
98  * and pointers for this driver instance.
99  */
100 
101 struct palmas_gpadc {
102 	struct device			*dev;
103 	struct palmas			*palmas;
104 	u8				ch0_current;
105 	u8				ch3_current;
106 	bool				extended_delay;
107 	int				irq;
108 	int				irq_auto_0;
109 	int				irq_auto_1;
110 	struct palmas_gpadc_info	*adc_info;
111 	struct completion		conv_completion;
112 	struct palmas_adc_wakeup_property wakeup1_data;
113 	struct palmas_adc_wakeup_property wakeup2_data;
114 	bool				wakeup1_enable;
115 	bool				wakeup2_enable;
116 	int				auto_conversion_period;
117 };
118 
119 /*
120  * GPADC lock issue in AUTO mode.
121  * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
122  *	   mode feature.
123  * Details:
124  *	When the AUTO mode is the only conversion mode enabled, if the AUTO
125  *	mode feature is disabled with bit GPADC_AUTO_CTRL.  AUTO_CONV1_EN = 0
126  *	or bit GPADC_AUTO_CTRL.  AUTO_CONV0_EN = 0 during a conversion, the
127  *	conversion mechanism can be seen as locked meaning that all following
128  *	conversion will give 0 as a result.  Bit GPADC_STATUS.GPADC_AVAILABLE
129  *	will stay at 0 meaning that GPADC is busy.  An RT conversion can unlock
130  *	the GPADC.
131  *
132  * Workaround(s):
133  *	To avoid the lock mechanism, the workaround to follow before any stop
134  *	conversion request is:
135  *	Force the GPADC state machine to be ON by using the GPADC_CTRL1.
136  *		GPADC_FORCE bit = 1
137  *	Shutdown the GPADC AUTO conversion using
138  *		GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
139  *	After 100us, force the GPADC state machine to be OFF by using the
140  *		GPADC_CTRL1.  GPADC_FORCE bit = 0
141  */
142 
143 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
144 {
145 	int ret;
146 
147 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
148 			PALMAS_GPADC_CTRL1,
149 			PALMAS_GPADC_CTRL1_GPADC_FORCE,
150 			PALMAS_GPADC_CTRL1_GPADC_FORCE);
151 	if (ret < 0) {
152 		dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
153 		return ret;
154 	}
155 
156 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
157 			PALMAS_GPADC_AUTO_CTRL,
158 			PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
159 			PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
160 			0);
161 	if (ret < 0) {
162 		dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
163 		return ret;
164 	}
165 
166 	udelay(100);
167 
168 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
169 			PALMAS_GPADC_CTRL1,
170 			PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
171 	if (ret < 0)
172 		dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
173 
174 	return ret;
175 }
176 
177 static irqreturn_t palmas_gpadc_irq(int irq, void *data)
178 {
179 	struct palmas_gpadc *adc = data;
180 
181 	complete(&adc->conv_completion);
182 
183 	return IRQ_HANDLED;
184 }
185 
186 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
187 {
188 	struct palmas_gpadc *adc = data;
189 
190 	dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq);
191 	palmas_disable_auto_conversion(adc);
192 
193 	return IRQ_HANDLED;
194 }
195 
196 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc,
197 						bool mask)
198 {
199 	int ret;
200 
201 	if (!mask)
202 		ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
203 					PALMAS_INT3_MASK,
204 					PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
205 	else
206 		ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
207 					PALMAS_INT3_MASK,
208 					PALMAS_INT3_MASK_GPADC_EOC_SW,
209 					PALMAS_INT3_MASK_GPADC_EOC_SW);
210 	if (ret < 0)
211 		dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
212 
213 	return ret;
214 }
215 
216 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
217 			       int enable)
218 {
219 	unsigned int mask, val;
220 	int ret;
221 
222 	if (enable) {
223 		val = (adc->extended_delay
224 			<< PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
225 		ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
226 					PALMAS_GPADC_RT_CTRL,
227 					PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
228 		if (ret < 0) {
229 			dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
230 			return ret;
231 		}
232 
233 		mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
234 			PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
235 			PALMAS_GPADC_CTRL1_GPADC_FORCE);
236 		val = (adc->ch0_current
237 			<< PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
238 		val |= (adc->ch3_current
239 			<< PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
240 		val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
241 		ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
242 				PALMAS_GPADC_CTRL1, mask, val);
243 		if (ret < 0) {
244 			dev_err(adc->dev,
245 				"Failed to update current setting: %d\n", ret);
246 			return ret;
247 		}
248 
249 		mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
250 			PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
251 		val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
252 		ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
253 				PALMAS_GPADC_SW_SELECT, mask, val);
254 		if (ret < 0) {
255 			dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
256 			return ret;
257 		}
258 	} else {
259 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
260 				PALMAS_GPADC_SW_SELECT, 0);
261 		if (ret < 0)
262 			dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
263 
264 		ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
265 				PALMAS_GPADC_CTRL1,
266 				PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
267 		if (ret < 0) {
268 			dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
269 			return ret;
270 		}
271 	}
272 
273 	return ret;
274 }
275 
276 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
277 {
278 	int ret;
279 
280 	ret = palmas_gpadc_enable(adc, adc_chan, true);
281 	if (ret < 0)
282 		return ret;
283 
284 	return palmas_gpadc_start_mask_interrupt(adc, 0);
285 }
286 
287 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
288 {
289 	palmas_gpadc_start_mask_interrupt(adc, 1);
290 	palmas_gpadc_enable(adc, adc_chan, false);
291 }
292 
293 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
294 {
295 	int k;
296 	int d1;
297 	int d2;
298 	int ret;
299 	int gain;
300 	int x1 =  adc->adc_info[adc_chan].x1;
301 	int x2 =  adc->adc_info[adc_chan].x2;
302 	int v1 = adc->adc_info[adc_chan].v1;
303 	int v2 = adc->adc_info[adc_chan].v2;
304 
305 	ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
306 				adc->adc_info[adc_chan].trim1_reg, &d1);
307 	if (ret < 0) {
308 		dev_err(adc->dev, "TRIM read failed: %d\n", ret);
309 		goto scrub;
310 	}
311 
312 	ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
313 				adc->adc_info[adc_chan].trim2_reg, &d2);
314 	if (ret < 0) {
315 		dev_err(adc->dev, "TRIM read failed: %d\n", ret);
316 		goto scrub;
317 	}
318 
319 	/* gain error calculation */
320 	k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
321 
322 	/* gain calculation */
323 	gain = ((v2 - v1) * 1000) / (x2 - x1);
324 
325 	adc->adc_info[adc_chan].gain_error = k;
326 	adc->adc_info[adc_chan].gain = gain;
327 	/* offset Calculation */
328 	adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
329 
330 scrub:
331 	return ret;
332 }
333 
334 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan)
335 {
336 	unsigned int val;
337 	int ret;
338 
339 	init_completion(&adc->conv_completion);
340 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
341 				PALMAS_GPADC_SW_SELECT,
342 				PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
343 				PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
344 	if (ret < 0) {
345 		dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret);
346 		return ret;
347 	}
348 
349 	ret = wait_for_completion_timeout(&adc->conv_completion,
350 				PALMAS_ADC_CONVERSION_TIMEOUT);
351 	if (ret == 0) {
352 		dev_err(adc->dev, "conversion not completed\n");
353 		return -ETIMEDOUT;
354 	}
355 
356 	ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
357 				PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
358 	if (ret < 0) {
359 		dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret);
360 		return ret;
361 	}
362 
363 	ret = val & 0xFFF;
364 
365 	return ret;
366 }
367 
368 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
369 						int adc_chan, int val)
370 {
371 	if (!adc->adc_info[adc_chan].is_uncalibrated)
372 		val  = (val*1000 - adc->adc_info[adc_chan].offset) /
373 					adc->adc_info[adc_chan].gain_error;
374 
375 	if (val < 0) {
376 		dev_err(adc->dev, "Mismatch with calibration\n");
377 		return 0;
378 	}
379 
380 	val = (val * adc->adc_info[adc_chan].gain) / 1000;
381 
382 	return val;
383 }
384 
385 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
386 	struct iio_chan_spec const *chan, int *val, int *val2, long mask)
387 {
388 	struct  palmas_gpadc *adc = iio_priv(indio_dev);
389 	int adc_chan = chan->channel;
390 	int ret = 0;
391 
392 	if (adc_chan > PALMAS_ADC_CH_MAX)
393 		return -EINVAL;
394 
395 	mutex_lock(&indio_dev->mlock);
396 
397 	switch (mask) {
398 	case IIO_CHAN_INFO_RAW:
399 	case IIO_CHAN_INFO_PROCESSED:
400 		ret = palmas_gpadc_read_prepare(adc, adc_chan);
401 		if (ret < 0)
402 			goto out;
403 
404 		ret = palmas_gpadc_start_conversion(adc, adc_chan);
405 		if (ret < 0) {
406 			dev_err(adc->dev,
407 			"ADC start conversion failed\n");
408 			goto out;
409 		}
410 
411 		if (mask == IIO_CHAN_INFO_PROCESSED)
412 			ret = palmas_gpadc_get_calibrated_code(
413 							adc, adc_chan, ret);
414 
415 		*val = ret;
416 
417 		ret = IIO_VAL_INT;
418 		goto out;
419 	}
420 
421 	mutex_unlock(&indio_dev->mlock);
422 	return ret;
423 
424 out:
425 	palmas_gpadc_read_done(adc, adc_chan);
426 	mutex_unlock(&indio_dev->mlock);
427 
428 	return ret;
429 }
430 
431 static const struct iio_info palmas_gpadc_iio_info = {
432 	.read_raw = palmas_gpadc_read_raw,
433 	.driver_module = THIS_MODULE,
434 };
435 
436 #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info)	\
437 {							\
438 	.datasheet_name = PALMAS_DATASHEET_NAME(chan),	\
439 	.type = _type,					\
440 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |	\
441 			BIT(chan_info),			\
442 	.indexed = 1,					\
443 	.channel = PALMAS_ADC_CH_##chan,		\
444 }
445 
446 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
447 	PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
448 	PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW),
449 	PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
450 	PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW),
451 	PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
452 	PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
453 	PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
454 	PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
455 	PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
456 	PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
457 	PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
458 	PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
459 	PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW),
460 	PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW),
461 	PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
462 	PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
463 };
464 
465 static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev,
466 	struct palmas_gpadc_platform_data **gpadc_pdata)
467 {
468 	struct device_node *np = pdev->dev.of_node;
469 	struct palmas_gpadc_platform_data *gp_data;
470 	int ret;
471 	u32 pval;
472 
473 	gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL);
474 	if (!gp_data)
475 		return -ENOMEM;
476 
477 	ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval);
478 	if (!ret)
479 		gp_data->ch0_current = pval;
480 
481 	ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval);
482 	if (!ret)
483 		gp_data->ch3_current = pval;
484 
485 	gp_data->extended_delay = of_property_read_bool(np,
486 					"ti,enable-extended-delay");
487 
488 	*gpadc_pdata = gp_data;
489 
490 	return 0;
491 }
492 
493 static int palmas_gpadc_probe(struct platform_device *pdev)
494 {
495 	struct palmas_gpadc *adc;
496 	struct palmas_platform_data *pdata;
497 	struct palmas_gpadc_platform_data *gpadc_pdata = NULL;
498 	struct iio_dev *indio_dev;
499 	int ret, i;
500 
501 	pdata = dev_get_platdata(pdev->dev.parent);
502 
503 	if (pdata && pdata->gpadc_pdata)
504 		gpadc_pdata = pdata->gpadc_pdata;
505 
506 	if (!gpadc_pdata && pdev->dev.of_node) {
507 		ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata);
508 		if (ret < 0)
509 			return ret;
510 	}
511 	if (!gpadc_pdata)
512 		return -EINVAL;
513 
514 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
515 	if (!indio_dev) {
516 		dev_err(&pdev->dev, "iio_device_alloc failed\n");
517 		return -ENOMEM;
518 	}
519 
520 	adc = iio_priv(indio_dev);
521 	adc->dev = &pdev->dev;
522 	adc->palmas = dev_get_drvdata(pdev->dev.parent);
523 	adc->adc_info = palmas_gpadc_info;
524 	init_completion(&adc->conv_completion);
525 	dev_set_drvdata(&pdev->dev, indio_dev);
526 
527 	adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms;
528 	adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
529 	if (adc->irq < 0) {
530 		dev_err(adc->dev,
531 			"get virq failed: %d\n", adc->irq);
532 		ret = adc->irq;
533 		goto out;
534 	}
535 	ret = request_threaded_irq(adc->irq, NULL,
536 		palmas_gpadc_irq,
537 		IRQF_ONESHOT, dev_name(adc->dev),
538 		adc);
539 	if (ret < 0) {
540 		dev_err(adc->dev,
541 			"request irq %d failed: %d\n", adc->irq, ret);
542 		goto out;
543 	}
544 
545 	if (gpadc_pdata->adc_wakeup1_data) {
546 		memcpy(&adc->wakeup1_data, gpadc_pdata->adc_wakeup1_data,
547 			sizeof(adc->wakeup1_data));
548 		adc->wakeup1_enable = true;
549 		adc->irq_auto_0 =  platform_get_irq(pdev, 1);
550 		ret = request_threaded_irq(adc->irq_auto_0, NULL,
551 				palmas_gpadc_irq_auto,
552 				IRQF_ONESHOT,
553 				"palmas-adc-auto-0", adc);
554 		if (ret < 0) {
555 			dev_err(adc->dev, "request auto0 irq %d failed: %d\n",
556 				adc->irq_auto_0, ret);
557 			goto out_irq_free;
558 		}
559 	}
560 
561 	if (gpadc_pdata->adc_wakeup2_data) {
562 		memcpy(&adc->wakeup2_data, gpadc_pdata->adc_wakeup2_data,
563 				sizeof(adc->wakeup2_data));
564 		adc->wakeup2_enable = true;
565 		adc->irq_auto_1 =  platform_get_irq(pdev, 2);
566 		ret = request_threaded_irq(adc->irq_auto_1, NULL,
567 				palmas_gpadc_irq_auto,
568 				IRQF_ONESHOT,
569 				"palmas-adc-auto-1", adc);
570 		if (ret < 0) {
571 			dev_err(adc->dev, "request auto1 irq %d failed: %d\n",
572 				adc->irq_auto_1, ret);
573 			goto out_irq_auto0_free;
574 		}
575 	}
576 
577 	/* set the current source 0 (value 0/5/15/20 uA => 0..3) */
578 	if (gpadc_pdata->ch0_current <= 1)
579 		adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
580 	else if (gpadc_pdata->ch0_current <= 5)
581 		adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
582 	else if (gpadc_pdata->ch0_current <= 15)
583 		adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
584 	else
585 		adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
586 
587 	/* set the current source 3 (value 0/10/400/800 uA => 0..3) */
588 	if (gpadc_pdata->ch3_current <= 1)
589 		adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
590 	else if (gpadc_pdata->ch3_current <= 10)
591 		adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
592 	else if (gpadc_pdata->ch3_current <= 400)
593 		adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
594 	else
595 		adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
596 
597 	adc->extended_delay = gpadc_pdata->extended_delay;
598 
599 	indio_dev->name = MOD_NAME;
600 	indio_dev->dev.parent = &pdev->dev;
601 	indio_dev->info = &palmas_gpadc_iio_info;
602 	indio_dev->modes = INDIO_DIRECT_MODE;
603 	indio_dev->channels = palmas_gpadc_iio_channel;
604 	indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
605 
606 	ret = iio_device_register(indio_dev);
607 	if (ret < 0) {
608 		dev_err(adc->dev, "iio_device_register() failed: %d\n", ret);
609 		goto out_irq_auto1_free;
610 	}
611 
612 	device_set_wakeup_capable(&pdev->dev, 1);
613 	for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
614 		if (!(adc->adc_info[i].is_uncalibrated))
615 			palmas_gpadc_calibrate(adc, i);
616 	}
617 
618 	if (adc->wakeup1_enable || adc->wakeup2_enable)
619 		device_wakeup_enable(&pdev->dev);
620 
621 	return 0;
622 
623 out_irq_auto1_free:
624 	if (gpadc_pdata->adc_wakeup2_data)
625 		free_irq(adc->irq_auto_1, adc);
626 out_irq_auto0_free:
627 	if (gpadc_pdata->adc_wakeup1_data)
628 		free_irq(adc->irq_auto_0, adc);
629 out_irq_free:
630 	free_irq(adc->irq, adc);
631 out:
632 	return ret;
633 }
634 
635 static int palmas_gpadc_remove(struct platform_device *pdev)
636 {
637 	struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev);
638 	struct palmas_gpadc *adc = iio_priv(indio_dev);
639 
640 	if (adc->wakeup1_enable || adc->wakeup2_enable)
641 		device_wakeup_disable(&pdev->dev);
642 	iio_device_unregister(indio_dev);
643 	free_irq(adc->irq, adc);
644 	if (adc->wakeup1_enable)
645 		free_irq(adc->irq_auto_0, adc);
646 	if (adc->wakeup2_enable)
647 		free_irq(adc->irq_auto_1, adc);
648 
649 	return 0;
650 }
651 
652 #ifdef CONFIG_PM_SLEEP
653 static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc)
654 {
655 	int adc_period, conv;
656 	int i;
657 	int ch0 = 0, ch1 = 0;
658 	int thres;
659 	int ret;
660 
661 	adc_period = adc->auto_conversion_period;
662 	for (i = 0; i < 16; ++i) {
663 		if (((1000 * (1 << i)) / 32) < adc_period)
664 			continue;
665 	}
666 	if (i > 0)
667 		i--;
668 	adc_period = i;
669 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
670 			PALMAS_GPADC_AUTO_CTRL,
671 			PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
672 			adc_period);
673 	if (ret < 0) {
674 		dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
675 		return ret;
676 	}
677 
678 	conv = 0;
679 	if (adc->wakeup1_enable) {
680 		int polarity;
681 
682 		ch0 = adc->wakeup1_data.adc_channel_number;
683 		conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
684 		if (adc->wakeup1_data.adc_high_threshold > 0) {
685 			thres = adc->wakeup1_data.adc_high_threshold;
686 			polarity = 0;
687 		} else {
688 			thres = adc->wakeup1_data.adc_low_threshold;
689 			polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL;
690 		}
691 
692 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
693 				PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
694 		if (ret < 0) {
695 			dev_err(adc->dev,
696 				"THRES_CONV0_LSB write failed: %d\n", ret);
697 			return ret;
698 		}
699 
700 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
701 				PALMAS_GPADC_THRES_CONV0_MSB,
702 				((thres >> 8) & 0xF) | polarity);
703 		if (ret < 0) {
704 			dev_err(adc->dev,
705 				"THRES_CONV0_MSB write failed: %d\n", ret);
706 			return ret;
707 		}
708 	}
709 
710 	if (adc->wakeup2_enable) {
711 		int polarity;
712 
713 		ch1 = adc->wakeup2_data.adc_channel_number;
714 		conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
715 		if (adc->wakeup2_data.adc_high_threshold > 0) {
716 			thres = adc->wakeup2_data.adc_high_threshold;
717 			polarity = 0;
718 		} else {
719 			thres = adc->wakeup2_data.adc_low_threshold;
720 			polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL;
721 		}
722 
723 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
724 				PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
725 		if (ret < 0) {
726 			dev_err(adc->dev,
727 				"THRES_CONV1_LSB write failed: %d\n", ret);
728 			return ret;
729 		}
730 
731 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
732 				PALMAS_GPADC_THRES_CONV1_MSB,
733 				((thres >> 8) & 0xF) | polarity);
734 		if (ret < 0) {
735 			dev_err(adc->dev,
736 				"THRES_CONV1_MSB write failed: %d\n", ret);
737 			return ret;
738 		}
739 	}
740 
741 	ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
742 			PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
743 	if (ret < 0) {
744 		dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
745 		return ret;
746 	}
747 
748 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
749 			PALMAS_GPADC_AUTO_CTRL,
750 			PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
751 			PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
752 	if (ret < 0)
753 		dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
754 
755 	return ret;
756 }
757 
758 static int palmas_adc_wakeup_reset(struct palmas_gpadc *adc)
759 {
760 	int ret;
761 
762 	ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
763 			PALMAS_GPADC_AUTO_SELECT, 0);
764 	if (ret < 0) {
765 		dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
766 		return ret;
767 	}
768 
769 	ret = palmas_disable_auto_conversion(adc);
770 	if (ret < 0)
771 		dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
772 
773 	return ret;
774 }
775 
776 static int palmas_gpadc_suspend(struct device *dev)
777 {
778 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
779 	struct palmas_gpadc *adc = iio_priv(indio_dev);
780 	int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
781 	int ret;
782 
783 	if (!device_may_wakeup(dev) || !wakeup)
784 		return 0;
785 
786 	ret = palmas_adc_wakeup_configure(adc);
787 	if (ret < 0)
788 		return ret;
789 
790 	if (adc->wakeup1_enable)
791 		enable_irq_wake(adc->irq_auto_0);
792 
793 	if (adc->wakeup2_enable)
794 		enable_irq_wake(adc->irq_auto_1);
795 
796 	return 0;
797 }
798 
799 static int palmas_gpadc_resume(struct device *dev)
800 {
801 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
802 	struct palmas_gpadc *adc = iio_priv(indio_dev);
803 	int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
804 	int ret;
805 
806 	if (!device_may_wakeup(dev) || !wakeup)
807 		return 0;
808 
809 	ret = palmas_adc_wakeup_reset(adc);
810 	if (ret < 0)
811 		return ret;
812 
813 	if (adc->wakeup1_enable)
814 		disable_irq_wake(adc->irq_auto_0);
815 
816 	if (adc->wakeup2_enable)
817 		disable_irq_wake(adc->irq_auto_1);
818 
819 	return 0;
820 };
821 #endif
822 
823 static const struct dev_pm_ops palmas_pm_ops = {
824 	SET_SYSTEM_SLEEP_PM_OPS(palmas_gpadc_suspend,
825 				palmas_gpadc_resume)
826 };
827 
828 static const struct of_device_id of_palmas_gpadc_match_tbl[] = {
829 	{ .compatible = "ti,palmas-gpadc", },
830 	{ /* end */ }
831 };
832 MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl);
833 
834 static struct platform_driver palmas_gpadc_driver = {
835 	.probe = palmas_gpadc_probe,
836 	.remove = palmas_gpadc_remove,
837 	.driver = {
838 		.name = MOD_NAME,
839 		.pm = &palmas_pm_ops,
840 		.of_match_table = of_palmas_gpadc_match_tbl,
841 	},
842 };
843 
844 static int __init palmas_gpadc_init(void)
845 {
846 	return platform_driver_register(&palmas_gpadc_driver);
847 }
848 module_init(palmas_gpadc_init);
849 
850 static void __exit palmas_gpadc_exit(void)
851 {
852 	platform_driver_unregister(&palmas_gpadc_driver);
853 }
854 module_exit(palmas_gpadc_exit);
855 
856 MODULE_DESCRIPTION("palmas GPADC driver");
857 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>");
858 MODULE_ALIAS("platform:palmas-gpadc");
859 MODULE_LICENSE("GPL v2");
860