1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * palmas-adc.c -- TI PALMAS GPADC. 4 * 5 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. 6 * 7 * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/err.h> 12 #include <linux/irq.h> 13 #include <linux/interrupt.h> 14 #include <linux/platform_device.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/mfd/palmas.h> 19 #include <linux/completion.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/iio/events.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/machine.h> 25 #include <linux/iio/driver.h> 26 27 #define MOD_NAME "palmas-gpadc" 28 #define PALMAS_ADC_CONVERSION_TIMEOUT (msecs_to_jiffies(5000)) 29 #define PALMAS_TO_BE_CALCULATED 0 30 #define PALMAS_GPADC_TRIMINVALID -1 31 32 struct palmas_gpadc_info { 33 /* calibration codes and regs */ 34 int x1; /* lower ideal code */ 35 int x2; /* higher ideal code */ 36 int v1; /* expected lower volt reading */ 37 int v2; /* expected higher volt reading */ 38 u8 trim1_reg; /* register number for lower trim */ 39 u8 trim2_reg; /* register number for upper trim */ 40 int gain; /* calculated from above (after reading trim regs) */ 41 int offset; /* calculated from above (after reading trim regs) */ 42 int gain_error; /* calculated from above (after reading trim regs) */ 43 bool is_uncalibrated; /* if channel has calibration data */ 44 }; 45 46 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \ 47 [PALMAS_ADC_CH_##_chan] = { \ 48 .x1 = _x1, \ 49 .x2 = _x2, \ 50 .v1 = _v1, \ 51 .v2 = _v2, \ 52 .gain = PALMAS_TO_BE_CALCULATED, \ 53 .offset = PALMAS_TO_BE_CALCULATED, \ 54 .gain_error = PALMAS_TO_BE_CALCULATED, \ 55 .trim1_reg = PALMAS_GPADC_TRIM##_t1, \ 56 .trim2_reg = PALMAS_GPADC_TRIM##_t2, \ 57 .is_uncalibrated = _is_uncalibrated \ 58 } 59 60 static struct palmas_gpadc_info palmas_gpadc_info[] = { 61 PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false), 62 PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false), 63 PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false), 64 PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false), 65 PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false), 66 PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false), 67 PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false), 68 PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false), 69 PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false), 70 PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false), 71 PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false), 72 PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true), 73 PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true), 74 PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true), 75 PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false), 76 PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true), 77 }; 78 79 struct palmas_adc_event { 80 bool enabled; 81 int channel; 82 enum iio_event_direction direction; 83 }; 84 85 struct palmas_gpadc_thresholds { 86 int high; 87 int low; 88 }; 89 90 /* 91 * struct palmas_gpadc - the palmas_gpadc structure 92 * @ch0_current: channel 0 current source setting 93 * 0: 0 uA 94 * 1: 5 uA 95 * 2: 15 uA 96 * 3: 20 uA 97 * @ch3_current: channel 0 current source setting 98 * 0: 0 uA 99 * 1: 10 uA 100 * 2: 400 uA 101 * 3: 800 uA 102 * @extended_delay: enable the gpadc extended delay mode 103 * @auto_conversion_period: define the auto_conversion_period 104 * @lock: Lock to protect the device state during a potential concurrent 105 * read access from userspace. Reading a raw value requires a sequence 106 * of register writes, then a wait for a completion callback, 107 * and finally a register read, during which userspace could issue 108 * another read request. This lock protects a read access from 109 * ocurring before another one has finished. 110 * 111 * This is the palmas_gpadc structure to store run-time information 112 * and pointers for this driver instance. 113 */ 114 struct palmas_gpadc { 115 struct device *dev; 116 struct palmas *palmas; 117 u8 ch0_current; 118 u8 ch3_current; 119 bool extended_delay; 120 int irq; 121 int irq_auto_0; 122 int irq_auto_1; 123 struct palmas_gpadc_info *adc_info; 124 struct completion conv_completion; 125 struct palmas_adc_event event0; 126 struct palmas_adc_event event1; 127 struct palmas_gpadc_thresholds thresholds[PALMAS_ADC_CH_MAX]; 128 int auto_conversion_period; 129 struct mutex lock; 130 }; 131 132 static struct palmas_adc_event *palmas_gpadc_get_event(struct palmas_gpadc *adc, 133 int adc_chan, 134 enum iio_event_direction dir) 135 { 136 if (adc_chan == adc->event0.channel && dir == adc->event0.direction) 137 return &adc->event0; 138 139 if (adc_chan == adc->event1.channel && dir == adc->event1.direction) 140 return &adc->event1; 141 142 return NULL; 143 } 144 145 static bool palmas_gpadc_channel_is_freerunning(struct palmas_gpadc *adc, 146 int adc_chan) 147 { 148 return palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_RISING) || 149 palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_FALLING); 150 } 151 152 /* 153 * GPADC lock issue in AUTO mode. 154 * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO 155 * mode feature. 156 * Details: 157 * When the AUTO mode is the only conversion mode enabled, if the AUTO 158 * mode feature is disabled with bit GPADC_AUTO_CTRL. AUTO_CONV1_EN = 0 159 * or bit GPADC_AUTO_CTRL. AUTO_CONV0_EN = 0 during a conversion, the 160 * conversion mechanism can be seen as locked meaning that all following 161 * conversion will give 0 as a result. Bit GPADC_STATUS.GPADC_AVAILABLE 162 * will stay at 0 meaning that GPADC is busy. An RT conversion can unlock 163 * the GPADC. 164 * 165 * Workaround(s): 166 * To avoid the lock mechanism, the workaround to follow before any stop 167 * conversion request is: 168 * Force the GPADC state machine to be ON by using the GPADC_CTRL1. 169 * GPADC_FORCE bit = 1 170 * Shutdown the GPADC AUTO conversion using 171 * GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0. 172 * After 100us, force the GPADC state machine to be OFF by using the 173 * GPADC_CTRL1. GPADC_FORCE bit = 0 174 */ 175 176 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc) 177 { 178 int ret; 179 180 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 181 PALMAS_GPADC_CTRL1, 182 PALMAS_GPADC_CTRL1_GPADC_FORCE, 183 PALMAS_GPADC_CTRL1_GPADC_FORCE); 184 if (ret < 0) { 185 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret); 186 return ret; 187 } 188 189 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 190 PALMAS_GPADC_AUTO_CTRL, 191 PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 | 192 PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0, 193 0); 194 if (ret < 0) { 195 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret); 196 return ret; 197 } 198 199 udelay(100); 200 201 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 202 PALMAS_GPADC_CTRL1, 203 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0); 204 if (ret < 0) 205 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret); 206 207 return ret; 208 } 209 210 static irqreturn_t palmas_gpadc_irq(int irq, void *data) 211 { 212 struct palmas_gpadc *adc = data; 213 214 complete(&adc->conv_completion); 215 216 return IRQ_HANDLED; 217 } 218 219 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data) 220 { 221 struct iio_dev *indio_dev = data; 222 struct palmas_gpadc *adc = iio_priv(indio_dev); 223 struct palmas_adc_event *ev; 224 225 dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq); 226 palmas_disable_auto_conversion(adc); 227 228 ev = (irq == adc->irq_auto_0) ? &adc->event0 : &adc->event1; 229 if (ev->channel != -1) { 230 enum iio_event_direction dir; 231 u64 code; 232 233 dir = ev->direction; 234 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, ev->channel, 235 IIO_EV_TYPE_THRESH, dir); 236 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev)); 237 } 238 239 return IRQ_HANDLED; 240 } 241 242 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc, 243 bool mask) 244 { 245 int ret; 246 247 if (!mask) 248 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE, 249 PALMAS_INT3_MASK, 250 PALMAS_INT3_MASK_GPADC_EOC_SW, 0); 251 else 252 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE, 253 PALMAS_INT3_MASK, 254 PALMAS_INT3_MASK_GPADC_EOC_SW, 255 PALMAS_INT3_MASK_GPADC_EOC_SW); 256 if (ret < 0) 257 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret); 258 259 return ret; 260 } 261 262 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan, 263 int enable) 264 { 265 unsigned int mask, val; 266 int ret; 267 268 if (enable) { 269 val = (adc->extended_delay 270 << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT); 271 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 272 PALMAS_GPADC_RT_CTRL, 273 PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val); 274 if (ret < 0) { 275 dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret); 276 return ret; 277 } 278 279 mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK | 280 PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK | 281 PALMAS_GPADC_CTRL1_GPADC_FORCE); 282 val = (adc->ch0_current 283 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT); 284 val |= (adc->ch3_current 285 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT); 286 val |= PALMAS_GPADC_CTRL1_GPADC_FORCE; 287 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 288 PALMAS_GPADC_CTRL1, mask, val); 289 if (ret < 0) { 290 dev_err(adc->dev, 291 "Failed to update current setting: %d\n", ret); 292 return ret; 293 } 294 295 mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK | 296 PALMAS_GPADC_SW_SELECT_SW_CONV_EN); 297 val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN); 298 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 299 PALMAS_GPADC_SW_SELECT, mask, val); 300 if (ret < 0) { 301 dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret); 302 return ret; 303 } 304 } else { 305 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 306 PALMAS_GPADC_SW_SELECT, 0); 307 if (ret < 0) 308 dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret); 309 310 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 311 PALMAS_GPADC_CTRL1, 312 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0); 313 if (ret < 0) { 314 dev_err(adc->dev, "CTRL1 update failed: %d\n", ret); 315 return ret; 316 } 317 } 318 319 return ret; 320 } 321 322 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan) 323 { 324 int ret; 325 326 if (palmas_gpadc_channel_is_freerunning(adc, adc_chan)) 327 return 0; /* ADC already running */ 328 329 ret = palmas_gpadc_enable(adc, adc_chan, true); 330 if (ret < 0) 331 return ret; 332 333 return palmas_gpadc_start_mask_interrupt(adc, 0); 334 } 335 336 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan) 337 { 338 palmas_gpadc_start_mask_interrupt(adc, 1); 339 palmas_gpadc_enable(adc, adc_chan, false); 340 } 341 342 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan) 343 { 344 int k; 345 int d1; 346 int d2; 347 int ret; 348 int gain; 349 int x1 = adc->adc_info[adc_chan].x1; 350 int x2 = adc->adc_info[adc_chan].x2; 351 int v1 = adc->adc_info[adc_chan].v1; 352 int v2 = adc->adc_info[adc_chan].v2; 353 354 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE, 355 adc->adc_info[adc_chan].trim1_reg, &d1); 356 if (ret < 0) { 357 dev_err(adc->dev, "TRIM read failed: %d\n", ret); 358 goto scrub; 359 } 360 361 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE, 362 adc->adc_info[adc_chan].trim2_reg, &d2); 363 if (ret < 0) { 364 dev_err(adc->dev, "TRIM read failed: %d\n", ret); 365 goto scrub; 366 } 367 368 /* gain error calculation */ 369 k = (1000 + (1000 * (d2 - d1)) / (x2 - x1)); 370 371 /* gain calculation */ 372 gain = ((v2 - v1) * 1000) / (x2 - x1); 373 374 adc->adc_info[adc_chan].gain_error = k; 375 adc->adc_info[adc_chan].gain = gain; 376 /* offset Calculation */ 377 adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1); 378 379 scrub: 380 return ret; 381 } 382 383 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan) 384 { 385 unsigned int val; 386 int ret; 387 388 if (palmas_gpadc_channel_is_freerunning(adc, adc_chan)) { 389 int event = (adc_chan == adc->event0.channel) ? 0 : 1; 390 unsigned int reg = (event == 0) ? 391 PALMAS_GPADC_AUTO_CONV0_LSB : 392 PALMAS_GPADC_AUTO_CONV1_LSB; 393 394 ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE, 395 reg, &val, 2); 396 if (ret < 0) { 397 dev_err(adc->dev, "AUTO_CONV%x_LSB read failed: %d\n", 398 event, ret); 399 return ret; 400 } 401 } else { 402 init_completion(&adc->conv_completion); 403 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 404 PALMAS_GPADC_SW_SELECT, 405 PALMAS_GPADC_SW_SELECT_SW_START_CONV0, 406 PALMAS_GPADC_SW_SELECT_SW_START_CONV0); 407 if (ret < 0) { 408 dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret); 409 return ret; 410 } 411 412 ret = wait_for_completion_timeout(&adc->conv_completion, 413 PALMAS_ADC_CONVERSION_TIMEOUT); 414 if (ret == 0) { 415 dev_err(adc->dev, "conversion not completed\n"); 416 return -ETIMEDOUT; 417 } 418 419 ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE, 420 PALMAS_GPADC_SW_CONV0_LSB, &val, 2); 421 if (ret < 0) { 422 dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret); 423 return ret; 424 } 425 } 426 427 ret = val & 0xFFF; 428 429 return ret; 430 } 431 432 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc, 433 int adc_chan, int val) 434 { 435 if (!adc->adc_info[adc_chan].is_uncalibrated) 436 val = (val*1000 - adc->adc_info[adc_chan].offset) / 437 adc->adc_info[adc_chan].gain_error; 438 439 if (val < 0) { 440 if (val < -10) 441 dev_err(adc->dev, "Mismatch with calibration var = %d\n", val); 442 return 0; 443 } 444 445 val = (val * adc->adc_info[adc_chan].gain) / 1000; 446 447 return val; 448 } 449 450 /* 451 * The high and low threshold values are calculated based on the advice given 452 * in TI Application Report SLIA087A, "Guide to Using the GPADC in PS65903x, 453 * TPS65917-Q1, TPS65919-Q1, and TPS65916 Devices". This document recommend 454 * taking ADC tolerances into account and is based on the device integral non- 455 * linearity (INL), offset error and gain error: 456 * 457 * raw high threshold = (ideal threshold + INL) * gain error + offset error 458 * 459 * The gain error include both gain error, as specified in the datasheet, and 460 * the gain error drift. These paramenters vary depending on device and whether 461 * the the channel is calibrated (trimmed) or not. 462 */ 463 static int palmas_gpadc_threshold_with_tolerance(int val, const int INL, 464 const int gain_error, 465 const int offset_error) 466 { 467 val = ((val + INL) * (1000 + gain_error)) / 1000 + offset_error; 468 469 return clamp(val, 0, 0xFFF); 470 } 471 472 /* 473 * The values below are taken from the datasheet of TWL6035, TWL6037. 474 * todo: get max INL, gain error, and offset error from OF. 475 */ 476 static int palmas_gpadc_get_high_threshold_raw(struct palmas_gpadc *adc, 477 struct palmas_adc_event *ev) 478 { 479 const int adc_chan = ev->channel; 480 int val = adc->thresholds[adc_chan].high; 481 /* integral nonlinearity, measured in LSB */ 482 const int max_INL = 2; 483 /* measured in LSB */ 484 int max_offset_error; 485 /* 0.2% when calibrated */ 486 int max_gain_error = 2; 487 488 val = (val * 1000) / adc->adc_info[adc_chan].gain; 489 490 if (adc->adc_info[adc_chan].is_uncalibrated) { 491 /* 2% worse */ 492 max_gain_error += 20; 493 max_offset_error = 36; 494 } else { 495 val = (val * adc->adc_info[adc_chan].gain_error + 496 adc->adc_info[adc_chan].offset) / 497 1000; 498 max_offset_error = 2; 499 } 500 501 return palmas_gpadc_threshold_with_tolerance(val, 502 max_INL, 503 max_gain_error, 504 max_offset_error); 505 } 506 507 /* 508 * The values below are taken from the datasheet of TWL6035, TWL6037. 509 * todo: get min INL, gain error, and offset error from OF. 510 */ 511 static int palmas_gpadc_get_low_threshold_raw(struct palmas_gpadc *adc, 512 struct palmas_adc_event *ev) 513 { 514 const int adc_chan = ev->channel; 515 int val = adc->thresholds[adc_chan].low; 516 /* integral nonlinearity, measured in LSB */ 517 const int min_INL = -2; 518 /* measured in LSB */ 519 int min_offset_error; 520 /* -0.6% when calibrated */ 521 int min_gain_error = -6; 522 523 val = (val * 1000) / adc->adc_info[adc_chan].gain; 524 525 if (adc->adc_info[adc_chan].is_uncalibrated) { 526 /* 2% worse */ 527 min_gain_error -= 20; 528 min_offset_error = -36; 529 } else { 530 val = (val * adc->adc_info[adc_chan].gain_error - 531 adc->adc_info[adc_chan].offset) / 532 1000; 533 min_offset_error = -2; 534 } 535 536 return palmas_gpadc_threshold_with_tolerance(val, 537 min_INL, 538 min_gain_error, 539 min_offset_error); 540 } 541 542 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev, 543 struct iio_chan_spec const *chan, int *val, int *val2, long mask) 544 { 545 struct palmas_gpadc *adc = iio_priv(indio_dev); 546 int adc_chan = chan->channel; 547 int ret = 0; 548 549 if (adc_chan >= PALMAS_ADC_CH_MAX) 550 return -EINVAL; 551 552 mutex_lock(&adc->lock); 553 554 switch (mask) { 555 case IIO_CHAN_INFO_RAW: 556 case IIO_CHAN_INFO_PROCESSED: 557 ret = palmas_gpadc_read_prepare(adc, adc_chan); 558 if (ret < 0) 559 goto out; 560 561 ret = palmas_gpadc_start_conversion(adc, adc_chan); 562 if (ret < 0) { 563 dev_err(adc->dev, 564 "ADC start conversion failed\n"); 565 goto out; 566 } 567 568 if (mask == IIO_CHAN_INFO_PROCESSED) 569 ret = palmas_gpadc_get_calibrated_code( 570 adc, adc_chan, ret); 571 572 *val = ret; 573 574 ret = IIO_VAL_INT; 575 goto out; 576 } 577 578 mutex_unlock(&adc->lock); 579 return ret; 580 581 out: 582 palmas_gpadc_read_done(adc, adc_chan); 583 mutex_unlock(&adc->lock); 584 585 return ret; 586 } 587 588 static int palmas_gpadc_read_event_config(struct iio_dev *indio_dev, 589 const struct iio_chan_spec *chan, 590 enum iio_event_type type, 591 enum iio_event_direction dir) 592 { 593 struct palmas_gpadc *adc = iio_priv(indio_dev); 594 int adc_chan = chan->channel; 595 int ret = 0; 596 597 if (adc_chan >= PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH) 598 return -EINVAL; 599 600 mutex_lock(&adc->lock); 601 602 if (palmas_gpadc_get_event(adc, adc_chan, dir)) 603 ret = 1; 604 605 mutex_unlock(&adc->lock); 606 607 return ret; 608 } 609 610 static int palmas_adc_configure_events(struct palmas_gpadc *adc); 611 static int palmas_adc_reset_events(struct palmas_gpadc *adc); 612 613 static int palmas_gpadc_reconfigure_event_channels(struct palmas_gpadc *adc) 614 { 615 return (adc->event0.enabled || adc->event1.enabled) ? 616 palmas_adc_configure_events(adc) : 617 palmas_adc_reset_events(adc); 618 } 619 620 static int palmas_gpadc_enable_event_config(struct palmas_gpadc *adc, 621 const struct iio_chan_spec *chan, 622 enum iio_event_direction dir) 623 { 624 struct palmas_adc_event *ev; 625 int adc_chan = chan->channel; 626 627 if (palmas_gpadc_get_event(adc, adc_chan, dir)) 628 /* already enabled */ 629 return 0; 630 631 if (adc->event0.channel == -1) { 632 ev = &adc->event0; 633 } else if (adc->event1.channel == -1) { 634 /* event0 has to be the lowest channel */ 635 if (adc_chan < adc->event0.channel) { 636 adc->event1 = adc->event0; 637 ev = &adc->event0; 638 } else { 639 ev = &adc->event1; 640 } 641 } else { /* both AUTO channels already in use */ 642 dev_warn(adc->dev, "event0 - %d, event1 - %d\n", 643 adc->event0.channel, adc->event1.channel); 644 return -EBUSY; 645 } 646 647 ev->enabled = true; 648 ev->channel = adc_chan; 649 ev->direction = dir; 650 651 return palmas_gpadc_reconfigure_event_channels(adc); 652 } 653 654 static int palmas_gpadc_disable_event_config(struct palmas_gpadc *adc, 655 const struct iio_chan_spec *chan, 656 enum iio_event_direction dir) 657 { 658 int adc_chan = chan->channel; 659 struct palmas_adc_event *ev = palmas_gpadc_get_event(adc, adc_chan, dir); 660 661 if (!ev) 662 return 0; 663 664 if (ev == &adc->event0) { 665 adc->event0 = adc->event1; 666 ev = &adc->event1; 667 } 668 669 ev->enabled = false; 670 ev->channel = -1; 671 ev->direction = IIO_EV_DIR_NONE; 672 673 return palmas_gpadc_reconfigure_event_channels(adc); 674 } 675 676 static int palmas_gpadc_write_event_config(struct iio_dev *indio_dev, 677 const struct iio_chan_spec *chan, 678 enum iio_event_type type, 679 enum iio_event_direction dir, 680 int state) 681 { 682 struct palmas_gpadc *adc = iio_priv(indio_dev); 683 int adc_chan = chan->channel; 684 int ret; 685 686 if (adc_chan >= PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH) 687 return -EINVAL; 688 689 mutex_lock(&adc->lock); 690 691 if (state) 692 ret = palmas_gpadc_enable_event_config(adc, chan, dir); 693 else 694 ret = palmas_gpadc_disable_event_config(adc, chan, dir); 695 696 mutex_unlock(&adc->lock); 697 698 return ret; 699 } 700 701 static int palmas_gpadc_read_event_value(struct iio_dev *indio_dev, 702 const struct iio_chan_spec *chan, 703 enum iio_event_type type, 704 enum iio_event_direction dir, 705 enum iio_event_info info, 706 int *val, int *val2) 707 { 708 struct palmas_gpadc *adc = iio_priv(indio_dev); 709 int adc_chan = chan->channel; 710 int ret; 711 712 if (adc_chan >= PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH) 713 return -EINVAL; 714 715 mutex_lock(&adc->lock); 716 717 switch (info) { 718 case IIO_EV_INFO_VALUE: 719 *val = (dir == IIO_EV_DIR_RISING) ? 720 adc->thresholds[adc_chan].high : 721 adc->thresholds[adc_chan].low; 722 ret = IIO_VAL_INT; 723 break; 724 default: 725 ret = -EINVAL; 726 break; 727 } 728 729 mutex_unlock(&adc->lock); 730 731 return ret; 732 } 733 734 static int palmas_gpadc_write_event_value(struct iio_dev *indio_dev, 735 const struct iio_chan_spec *chan, 736 enum iio_event_type type, 737 enum iio_event_direction dir, 738 enum iio_event_info info, 739 int val, int val2) 740 { 741 struct palmas_gpadc *adc = iio_priv(indio_dev); 742 int adc_chan = chan->channel; 743 int old; 744 int ret; 745 746 if (adc_chan >= PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH) 747 return -EINVAL; 748 749 mutex_lock(&adc->lock); 750 switch (info) { 751 case IIO_EV_INFO_VALUE: 752 if (val < 0 || val > 0xFFF) { 753 ret = -EINVAL; 754 goto out_unlock; 755 } 756 if (dir == IIO_EV_DIR_RISING) { 757 old = adc->thresholds[adc_chan].high; 758 adc->thresholds[adc_chan].high = val; 759 } else { 760 old = adc->thresholds[adc_chan].low; 761 adc->thresholds[adc_chan].low = val; 762 } 763 ret = 0; 764 break; 765 default: 766 ret = -EINVAL; 767 goto out_unlock; 768 } 769 770 if (val != old && palmas_gpadc_get_event(adc, adc_chan, dir)) 771 ret = palmas_gpadc_reconfigure_event_channels(adc); 772 773 out_unlock: 774 mutex_unlock(&adc->lock); 775 776 return ret; 777 } 778 779 static const struct iio_info palmas_gpadc_iio_info = { 780 .read_raw = palmas_gpadc_read_raw, 781 .read_event_config = palmas_gpadc_read_event_config, 782 .write_event_config = palmas_gpadc_write_event_config, 783 .read_event_value = palmas_gpadc_read_event_value, 784 .write_event_value = palmas_gpadc_write_event_value, 785 }; 786 787 static const struct iio_event_spec palmas_gpadc_events[] = { 788 { 789 .type = IIO_EV_TYPE_THRESH, 790 .dir = IIO_EV_DIR_RISING, 791 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 792 BIT(IIO_EV_INFO_ENABLE), 793 }, { 794 .type = IIO_EV_TYPE_THRESH, 795 .dir = IIO_EV_DIR_FALLING, 796 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 797 BIT(IIO_EV_INFO_ENABLE), 798 }, 799 }; 800 801 #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \ 802 { \ 803 .datasheet_name = PALMAS_DATASHEET_NAME(chan), \ 804 .type = _type, \ 805 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 806 BIT(chan_info), \ 807 .indexed = 1, \ 808 .channel = PALMAS_ADC_CH_##chan, \ 809 .event_spec = palmas_gpadc_events, \ 810 .num_event_specs = ARRAY_SIZE(palmas_gpadc_events) \ 811 } 812 813 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = { 814 PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 815 PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW), 816 PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 817 PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW), 818 PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 819 PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 820 PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 821 PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 822 PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 823 PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 824 PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 825 PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 826 PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW), 827 PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW), 828 PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 829 PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED), 830 }; 831 832 static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev, 833 struct palmas_gpadc_platform_data **gpadc_pdata) 834 { 835 struct device_node *np = pdev->dev.of_node; 836 struct palmas_gpadc_platform_data *gp_data; 837 int ret; 838 u32 pval; 839 840 gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL); 841 if (!gp_data) 842 return -ENOMEM; 843 844 ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval); 845 if (!ret) 846 gp_data->ch0_current = pval; 847 848 ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval); 849 if (!ret) 850 gp_data->ch3_current = pval; 851 852 gp_data->extended_delay = of_property_read_bool(np, 853 "ti,enable-extended-delay"); 854 855 *gpadc_pdata = gp_data; 856 857 return 0; 858 } 859 860 static void palmas_gpadc_reset(void *data) 861 { 862 struct palmas_gpadc *adc = data; 863 if (adc->event0.enabled || adc->event1.enabled) 864 palmas_adc_reset_events(adc); 865 } 866 867 static int palmas_gpadc_probe(struct platform_device *pdev) 868 { 869 struct palmas_gpadc *adc; 870 struct palmas_platform_data *pdata; 871 struct palmas_gpadc_platform_data *gpadc_pdata = NULL; 872 struct iio_dev *indio_dev; 873 int ret, i; 874 875 pdata = dev_get_platdata(pdev->dev.parent); 876 877 if (pdata && pdata->gpadc_pdata) 878 gpadc_pdata = pdata->gpadc_pdata; 879 880 if (!gpadc_pdata && pdev->dev.of_node) { 881 ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata); 882 if (ret < 0) 883 return ret; 884 } 885 if (!gpadc_pdata) 886 return -EINVAL; 887 888 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 889 if (!indio_dev) { 890 dev_err(&pdev->dev, "iio_device_alloc failed\n"); 891 return -ENOMEM; 892 } 893 894 adc = iio_priv(indio_dev); 895 adc->dev = &pdev->dev; 896 adc->palmas = dev_get_drvdata(pdev->dev.parent); 897 adc->adc_info = palmas_gpadc_info; 898 899 mutex_init(&adc->lock); 900 901 init_completion(&adc->conv_completion); 902 platform_set_drvdata(pdev, indio_dev); 903 904 adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms; 905 adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ); 906 if (adc->irq < 0) 907 return dev_err_probe(adc->dev, adc->irq, "get virq failed\n"); 908 909 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, NULL, 910 palmas_gpadc_irq, 911 IRQF_ONESHOT, dev_name(adc->dev), 912 adc); 913 if (ret < 0) 914 return dev_err_probe(adc->dev, ret, 915 "request irq %d failed\n", adc->irq); 916 917 adc->irq_auto_0 = platform_get_irq(pdev, 1); 918 if (adc->irq_auto_0 < 0) 919 return dev_err_probe(adc->dev, adc->irq_auto_0, 920 "get auto0 irq failed\n"); 921 922 ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_0, NULL, 923 palmas_gpadc_irq_auto, IRQF_ONESHOT, 924 "palmas-adc-auto-0", indio_dev); 925 if (ret < 0) 926 return dev_err_probe(adc->dev, ret, 927 "request auto0 irq %d failed\n", 928 adc->irq_auto_0); 929 930 adc->irq_auto_1 = platform_get_irq(pdev, 2); 931 if (adc->irq_auto_1 < 0) 932 return dev_err_probe(adc->dev, adc->irq_auto_1, 933 "get auto1 irq failed\n"); 934 935 ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_1, NULL, 936 palmas_gpadc_irq_auto, IRQF_ONESHOT, 937 "palmas-adc-auto-1", indio_dev); 938 if (ret < 0) 939 return dev_err_probe(adc->dev, ret, 940 "request auto1 irq %d failed\n", 941 adc->irq_auto_1); 942 943 adc->event0.enabled = false; 944 adc->event0.channel = -1; 945 adc->event0.direction = IIO_EV_DIR_NONE; 946 adc->event1.enabled = false; 947 adc->event1.channel = -1; 948 adc->event1.direction = IIO_EV_DIR_NONE; 949 950 /* set the current source 0 (value 0/5/15/20 uA => 0..3) */ 951 if (gpadc_pdata->ch0_current <= 1) 952 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0; 953 else if (gpadc_pdata->ch0_current <= 5) 954 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5; 955 else if (gpadc_pdata->ch0_current <= 15) 956 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15; 957 else 958 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20; 959 960 /* set the current source 3 (value 0/10/400/800 uA => 0..3) */ 961 if (gpadc_pdata->ch3_current <= 1) 962 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0; 963 else if (gpadc_pdata->ch3_current <= 10) 964 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10; 965 else if (gpadc_pdata->ch3_current <= 400) 966 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400; 967 else 968 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800; 969 970 adc->extended_delay = gpadc_pdata->extended_delay; 971 972 indio_dev->name = MOD_NAME; 973 indio_dev->info = &palmas_gpadc_iio_info; 974 indio_dev->modes = INDIO_DIRECT_MODE; 975 indio_dev->channels = palmas_gpadc_iio_channel; 976 indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel); 977 978 ret = devm_iio_device_register(&pdev->dev, indio_dev); 979 if (ret < 0) 980 return dev_err_probe(adc->dev, ret, 981 "iio_device_register() failed\n"); 982 983 device_set_wakeup_capable(&pdev->dev, 1); 984 for (i = 0; i < PALMAS_ADC_CH_MAX; i++) { 985 if (!(adc->adc_info[i].is_uncalibrated)) 986 palmas_gpadc_calibrate(adc, i); 987 } 988 989 ret = devm_add_action(&pdev->dev, palmas_gpadc_reset, adc); 990 if (ret) 991 return ret; 992 993 return 0; 994 } 995 996 static int palmas_adc_configure_events(struct palmas_gpadc *adc) 997 { 998 int adc_period, conv; 999 int i; 1000 int ch0 = 0, ch1 = 0; 1001 int thres; 1002 int ret; 1003 1004 adc_period = adc->auto_conversion_period; 1005 for (i = 0; i < 16; ++i) { 1006 if (((1000 * (1 << i)) / 32) >= adc_period) 1007 break; 1008 } 1009 if (i > 0) 1010 i--; 1011 adc_period = i; 1012 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 1013 PALMAS_GPADC_AUTO_CTRL, 1014 PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK, 1015 adc_period); 1016 if (ret < 0) { 1017 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret); 1018 return ret; 1019 } 1020 1021 conv = 0; 1022 if (adc->event0.enabled) { 1023 struct palmas_adc_event *ev = &adc->event0; 1024 int polarity; 1025 1026 ch0 = ev->channel; 1027 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN; 1028 switch (ev->direction) { 1029 case IIO_EV_DIR_RISING: 1030 thres = palmas_gpadc_get_high_threshold_raw(adc, ev); 1031 polarity = 0; 1032 break; 1033 case IIO_EV_DIR_FALLING: 1034 thres = palmas_gpadc_get_low_threshold_raw(adc, ev); 1035 polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL; 1036 break; 1037 default: 1038 return -EINVAL; 1039 } 1040 1041 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1042 PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF); 1043 if (ret < 0) { 1044 dev_err(adc->dev, 1045 "THRES_CONV0_LSB write failed: %d\n", ret); 1046 return ret; 1047 } 1048 1049 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1050 PALMAS_GPADC_THRES_CONV0_MSB, 1051 ((thres >> 8) & 0xF) | polarity); 1052 if (ret < 0) { 1053 dev_err(adc->dev, 1054 "THRES_CONV0_MSB write failed: %d\n", ret); 1055 return ret; 1056 } 1057 } 1058 1059 if (adc->event1.enabled) { 1060 struct palmas_adc_event *ev = &adc->event1; 1061 int polarity; 1062 1063 ch1 = ev->channel; 1064 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN; 1065 switch (ev->direction) { 1066 case IIO_EV_DIR_RISING: 1067 thres = palmas_gpadc_get_high_threshold_raw(adc, ev); 1068 polarity = 0; 1069 break; 1070 case IIO_EV_DIR_FALLING: 1071 thres = palmas_gpadc_get_low_threshold_raw(adc, ev); 1072 polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL; 1073 break; 1074 default: 1075 return -EINVAL; 1076 } 1077 1078 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1079 PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF); 1080 if (ret < 0) { 1081 dev_err(adc->dev, 1082 "THRES_CONV1_LSB write failed: %d\n", ret); 1083 return ret; 1084 } 1085 1086 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1087 PALMAS_GPADC_THRES_CONV1_MSB, 1088 ((thres >> 8) & 0xF) | polarity); 1089 if (ret < 0) { 1090 dev_err(adc->dev, 1091 "THRES_CONV1_MSB write failed: %d\n", ret); 1092 return ret; 1093 } 1094 } 1095 1096 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1097 PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0); 1098 if (ret < 0) { 1099 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret); 1100 return ret; 1101 } 1102 1103 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE, 1104 PALMAS_GPADC_AUTO_CTRL, 1105 PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN | 1106 PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv); 1107 if (ret < 0) 1108 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret); 1109 1110 return ret; 1111 } 1112 1113 static int palmas_adc_reset_events(struct palmas_gpadc *adc) 1114 { 1115 int ret; 1116 1117 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE, 1118 PALMAS_GPADC_AUTO_SELECT, 0); 1119 if (ret < 0) { 1120 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret); 1121 return ret; 1122 } 1123 1124 ret = palmas_disable_auto_conversion(adc); 1125 if (ret < 0) 1126 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret); 1127 1128 return ret; 1129 } 1130 1131 static int palmas_gpadc_suspend(struct device *dev) 1132 { 1133 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1134 struct palmas_gpadc *adc = iio_priv(indio_dev); 1135 1136 if (!device_may_wakeup(dev)) 1137 return 0; 1138 1139 if (adc->event0.enabled) 1140 enable_irq_wake(adc->irq_auto_0); 1141 1142 if (adc->event1.enabled) 1143 enable_irq_wake(adc->irq_auto_1); 1144 1145 return 0; 1146 } 1147 1148 static int palmas_gpadc_resume(struct device *dev) 1149 { 1150 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1151 struct palmas_gpadc *adc = iio_priv(indio_dev); 1152 1153 if (!device_may_wakeup(dev)) 1154 return 0; 1155 1156 if (adc->event0.enabled) 1157 disable_irq_wake(adc->irq_auto_0); 1158 1159 if (adc->event1.enabled) 1160 disable_irq_wake(adc->irq_auto_1); 1161 1162 return 0; 1163 }; 1164 1165 static DEFINE_SIMPLE_DEV_PM_OPS(palmas_pm_ops, palmas_gpadc_suspend, 1166 palmas_gpadc_resume); 1167 1168 static const struct of_device_id of_palmas_gpadc_match_tbl[] = { 1169 { .compatible = "ti,palmas-gpadc", }, 1170 { /* end */ } 1171 }; 1172 MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl); 1173 1174 static struct platform_driver palmas_gpadc_driver = { 1175 .probe = palmas_gpadc_probe, 1176 .driver = { 1177 .name = MOD_NAME, 1178 .pm = pm_sleep_ptr(&palmas_pm_ops), 1179 .of_match_table = of_palmas_gpadc_match_tbl, 1180 }, 1181 }; 1182 module_platform_driver(palmas_gpadc_driver); 1183 1184 MODULE_DESCRIPTION("palmas GPADC driver"); 1185 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>"); 1186 MODULE_ALIAS("platform:palmas-gpadc"); 1187 MODULE_LICENSE("GPL v2"); 1188