xref: /openbmc/linux/drivers/iio/adc/palmas_gpadc.c (revision 2cf1c348)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * palmas-adc.c -- TI PALMAS GPADC.
4  *
5  * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
6  *
7  * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com>
8  */
9 
10 #include <linux/module.h>
11 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/pm.h>
19 #include <linux/mfd/palmas.h>
20 #include <linux/completion.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/machine.h>
25 #include <linux/iio/driver.h>
26 
27 #define MOD_NAME "palmas-gpadc"
28 #define PALMAS_ADC_CONVERSION_TIMEOUT	(msecs_to_jiffies(5000))
29 #define PALMAS_TO_BE_CALCULATED 0
30 #define PALMAS_GPADC_TRIMINVALID	-1
31 
32 struct palmas_gpadc_info {
33 /* calibration codes and regs */
34 	int x1;	/* lower ideal code */
35 	int x2;	/* higher ideal code */
36 	int v1;	/* expected lower volt reading */
37 	int v2;	/* expected higher volt reading */
38 	u8 trim1_reg;	/* register number for lower trim */
39 	u8 trim2_reg;	/* register number for upper trim */
40 	int gain;	/* calculated from above (after reading trim regs) */
41 	int offset;	/* calculated from above (after reading trim regs) */
42 	int gain_error;	/* calculated from above (after reading trim regs) */
43 	bool is_uncalibrated;	/* if channel has calibration data */
44 };
45 
46 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \
47 	[PALMAS_ADC_CH_##_chan] = { \
48 		.x1 = _x1, \
49 		.x2 = _x2, \
50 		.v1 = _v1, \
51 		.v2 = _v2, \
52 		.gain = PALMAS_TO_BE_CALCULATED, \
53 		.offset = PALMAS_TO_BE_CALCULATED, \
54 		.gain_error = PALMAS_TO_BE_CALCULATED, \
55 		.trim1_reg = PALMAS_GPADC_TRIM##_t1, \
56 		.trim2_reg = PALMAS_GPADC_TRIM##_t2,  \
57 		.is_uncalibrated = _is_uncalibrated \
58 	}
59 
60 static struct palmas_gpadc_info palmas_gpadc_info[] = {
61 	PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false),
62 	PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false),
63 	PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false),
64 	PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false),
65 	PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false),
66 	PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false),
67 	PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false),
68 	PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false),
69 	PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false),
70 	PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false),
71 	PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false),
72 	PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true),
73 	PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true),
74 	PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true),
75 	PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false),
76 	PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true),
77 };
78 
79 /*
80  * struct palmas_gpadc - the palmas_gpadc structure
81  * @ch0_current:	channel 0 current source setting
82  *			0: 0 uA
83  *			1: 5 uA
84  *			2: 15 uA
85  *			3: 20 uA
86  * @ch3_current:	channel 0 current source setting
87  *			0: 0 uA
88  *			1: 10 uA
89  *			2: 400 uA
90  *			3: 800 uA
91  * @extended_delay:	enable the gpadc extended delay mode
92  * @auto_conversion_period:	define the auto_conversion_period
93  * @lock:	Lock to protect the device state during a potential concurrent
94  *		read access from userspace. Reading a raw value requires a sequence
95  *		of register writes, then a wait for a completion callback,
96  *		and finally a register read, during which userspace could issue
97  *		another read request. This lock protects a read access from
98  *		ocurring before another one has finished.
99  *
100  * This is the palmas_gpadc structure to store run-time information
101  * and pointers for this driver instance.
102  */
103 struct palmas_gpadc {
104 	struct device			*dev;
105 	struct palmas			*palmas;
106 	u8				ch0_current;
107 	u8				ch3_current;
108 	bool				extended_delay;
109 	int				irq;
110 	int				irq_auto_0;
111 	int				irq_auto_1;
112 	struct palmas_gpadc_info	*adc_info;
113 	struct completion		conv_completion;
114 	struct palmas_adc_wakeup_property wakeup1_data;
115 	struct palmas_adc_wakeup_property wakeup2_data;
116 	bool				wakeup1_enable;
117 	bool				wakeup2_enable;
118 	int				auto_conversion_period;
119 	struct mutex			lock;
120 };
121 
122 /*
123  * GPADC lock issue in AUTO mode.
124  * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
125  *	   mode feature.
126  * Details:
127  *	When the AUTO mode is the only conversion mode enabled, if the AUTO
128  *	mode feature is disabled with bit GPADC_AUTO_CTRL.  AUTO_CONV1_EN = 0
129  *	or bit GPADC_AUTO_CTRL.  AUTO_CONV0_EN = 0 during a conversion, the
130  *	conversion mechanism can be seen as locked meaning that all following
131  *	conversion will give 0 as a result.  Bit GPADC_STATUS.GPADC_AVAILABLE
132  *	will stay at 0 meaning that GPADC is busy.  An RT conversion can unlock
133  *	the GPADC.
134  *
135  * Workaround(s):
136  *	To avoid the lock mechanism, the workaround to follow before any stop
137  *	conversion request is:
138  *	Force the GPADC state machine to be ON by using the GPADC_CTRL1.
139  *		GPADC_FORCE bit = 1
140  *	Shutdown the GPADC AUTO conversion using
141  *		GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
142  *	After 100us, force the GPADC state machine to be OFF by using the
143  *		GPADC_CTRL1.  GPADC_FORCE bit = 0
144  */
145 
146 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
147 {
148 	int ret;
149 
150 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
151 			PALMAS_GPADC_CTRL1,
152 			PALMAS_GPADC_CTRL1_GPADC_FORCE,
153 			PALMAS_GPADC_CTRL1_GPADC_FORCE);
154 	if (ret < 0) {
155 		dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
156 		return ret;
157 	}
158 
159 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
160 			PALMAS_GPADC_AUTO_CTRL,
161 			PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
162 			PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
163 			0);
164 	if (ret < 0) {
165 		dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
166 		return ret;
167 	}
168 
169 	udelay(100);
170 
171 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
172 			PALMAS_GPADC_CTRL1,
173 			PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
174 	if (ret < 0)
175 		dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
176 
177 	return ret;
178 }
179 
180 static irqreturn_t palmas_gpadc_irq(int irq, void *data)
181 {
182 	struct palmas_gpadc *adc = data;
183 
184 	complete(&adc->conv_completion);
185 
186 	return IRQ_HANDLED;
187 }
188 
189 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
190 {
191 	struct palmas_gpadc *adc = data;
192 
193 	dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq);
194 	palmas_disable_auto_conversion(adc);
195 
196 	return IRQ_HANDLED;
197 }
198 
199 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc,
200 						bool mask)
201 {
202 	int ret;
203 
204 	if (!mask)
205 		ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
206 					PALMAS_INT3_MASK,
207 					PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
208 	else
209 		ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
210 					PALMAS_INT3_MASK,
211 					PALMAS_INT3_MASK_GPADC_EOC_SW,
212 					PALMAS_INT3_MASK_GPADC_EOC_SW);
213 	if (ret < 0)
214 		dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
215 
216 	return ret;
217 }
218 
219 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
220 			       int enable)
221 {
222 	unsigned int mask, val;
223 	int ret;
224 
225 	if (enable) {
226 		val = (adc->extended_delay
227 			<< PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
228 		ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
229 					PALMAS_GPADC_RT_CTRL,
230 					PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
231 		if (ret < 0) {
232 			dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
233 			return ret;
234 		}
235 
236 		mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
237 			PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
238 			PALMAS_GPADC_CTRL1_GPADC_FORCE);
239 		val = (adc->ch0_current
240 			<< PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
241 		val |= (adc->ch3_current
242 			<< PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
243 		val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
244 		ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
245 				PALMAS_GPADC_CTRL1, mask, val);
246 		if (ret < 0) {
247 			dev_err(adc->dev,
248 				"Failed to update current setting: %d\n", ret);
249 			return ret;
250 		}
251 
252 		mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
253 			PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
254 		val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
255 		ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
256 				PALMAS_GPADC_SW_SELECT, mask, val);
257 		if (ret < 0) {
258 			dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
259 			return ret;
260 		}
261 	} else {
262 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
263 				PALMAS_GPADC_SW_SELECT, 0);
264 		if (ret < 0)
265 			dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
266 
267 		ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
268 				PALMAS_GPADC_CTRL1,
269 				PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
270 		if (ret < 0) {
271 			dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
272 			return ret;
273 		}
274 	}
275 
276 	return ret;
277 }
278 
279 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
280 {
281 	int ret;
282 
283 	ret = palmas_gpadc_enable(adc, adc_chan, true);
284 	if (ret < 0)
285 		return ret;
286 
287 	return palmas_gpadc_start_mask_interrupt(adc, 0);
288 }
289 
290 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
291 {
292 	palmas_gpadc_start_mask_interrupt(adc, 1);
293 	palmas_gpadc_enable(adc, adc_chan, false);
294 }
295 
296 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
297 {
298 	int k;
299 	int d1;
300 	int d2;
301 	int ret;
302 	int gain;
303 	int x1 =  adc->adc_info[adc_chan].x1;
304 	int x2 =  adc->adc_info[adc_chan].x2;
305 	int v1 = adc->adc_info[adc_chan].v1;
306 	int v2 = adc->adc_info[adc_chan].v2;
307 
308 	ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
309 				adc->adc_info[adc_chan].trim1_reg, &d1);
310 	if (ret < 0) {
311 		dev_err(adc->dev, "TRIM read failed: %d\n", ret);
312 		goto scrub;
313 	}
314 
315 	ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
316 				adc->adc_info[adc_chan].trim2_reg, &d2);
317 	if (ret < 0) {
318 		dev_err(adc->dev, "TRIM read failed: %d\n", ret);
319 		goto scrub;
320 	}
321 
322 	/* gain error calculation */
323 	k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
324 
325 	/* gain calculation */
326 	gain = ((v2 - v1) * 1000) / (x2 - x1);
327 
328 	adc->adc_info[adc_chan].gain_error = k;
329 	adc->adc_info[adc_chan].gain = gain;
330 	/* offset Calculation */
331 	adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
332 
333 scrub:
334 	return ret;
335 }
336 
337 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan)
338 {
339 	unsigned int val;
340 	int ret;
341 
342 	init_completion(&adc->conv_completion);
343 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
344 				PALMAS_GPADC_SW_SELECT,
345 				PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
346 				PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
347 	if (ret < 0) {
348 		dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret);
349 		return ret;
350 	}
351 
352 	ret = wait_for_completion_timeout(&adc->conv_completion,
353 				PALMAS_ADC_CONVERSION_TIMEOUT);
354 	if (ret == 0) {
355 		dev_err(adc->dev, "conversion not completed\n");
356 		return -ETIMEDOUT;
357 	}
358 
359 	ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
360 				PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
361 	if (ret < 0) {
362 		dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret);
363 		return ret;
364 	}
365 
366 	ret = val & 0xFFF;
367 
368 	return ret;
369 }
370 
371 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
372 						int adc_chan, int val)
373 {
374 	if (!adc->adc_info[adc_chan].is_uncalibrated)
375 		val  = (val*1000 - adc->adc_info[adc_chan].offset) /
376 					adc->adc_info[adc_chan].gain_error;
377 
378 	if (val < 0) {
379 		dev_err(adc->dev, "Mismatch with calibration\n");
380 		return 0;
381 	}
382 
383 	val = (val * adc->adc_info[adc_chan].gain) / 1000;
384 
385 	return val;
386 }
387 
388 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
389 	struct iio_chan_spec const *chan, int *val, int *val2, long mask)
390 {
391 	struct  palmas_gpadc *adc = iio_priv(indio_dev);
392 	int adc_chan = chan->channel;
393 	int ret = 0;
394 
395 	if (adc_chan > PALMAS_ADC_CH_MAX)
396 		return -EINVAL;
397 
398 	mutex_lock(&adc->lock);
399 
400 	switch (mask) {
401 	case IIO_CHAN_INFO_RAW:
402 	case IIO_CHAN_INFO_PROCESSED:
403 		ret = palmas_gpadc_read_prepare(adc, adc_chan);
404 		if (ret < 0)
405 			goto out;
406 
407 		ret = palmas_gpadc_start_conversion(adc, adc_chan);
408 		if (ret < 0) {
409 			dev_err(adc->dev,
410 			"ADC start conversion failed\n");
411 			goto out;
412 		}
413 
414 		if (mask == IIO_CHAN_INFO_PROCESSED)
415 			ret = palmas_gpadc_get_calibrated_code(
416 							adc, adc_chan, ret);
417 
418 		*val = ret;
419 
420 		ret = IIO_VAL_INT;
421 		goto out;
422 	}
423 
424 	mutex_unlock(&adc->lock);
425 	return ret;
426 
427 out:
428 	palmas_gpadc_read_done(adc, adc_chan);
429 	mutex_unlock(&adc->lock);
430 
431 	return ret;
432 }
433 
434 static const struct iio_info palmas_gpadc_iio_info = {
435 	.read_raw = palmas_gpadc_read_raw,
436 };
437 
438 #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info)	\
439 {							\
440 	.datasheet_name = PALMAS_DATASHEET_NAME(chan),	\
441 	.type = _type,					\
442 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |	\
443 			BIT(chan_info),			\
444 	.indexed = 1,					\
445 	.channel = PALMAS_ADC_CH_##chan,		\
446 }
447 
448 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
449 	PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
450 	PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW),
451 	PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
452 	PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW),
453 	PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
454 	PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
455 	PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
456 	PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
457 	PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
458 	PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
459 	PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
460 	PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
461 	PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW),
462 	PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW),
463 	PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
464 	PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
465 };
466 
467 static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev,
468 	struct palmas_gpadc_platform_data **gpadc_pdata)
469 {
470 	struct device_node *np = pdev->dev.of_node;
471 	struct palmas_gpadc_platform_data *gp_data;
472 	int ret;
473 	u32 pval;
474 
475 	gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL);
476 	if (!gp_data)
477 		return -ENOMEM;
478 
479 	ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval);
480 	if (!ret)
481 		gp_data->ch0_current = pval;
482 
483 	ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval);
484 	if (!ret)
485 		gp_data->ch3_current = pval;
486 
487 	gp_data->extended_delay = of_property_read_bool(np,
488 					"ti,enable-extended-delay");
489 
490 	*gpadc_pdata = gp_data;
491 
492 	return 0;
493 }
494 
495 static int palmas_gpadc_probe(struct platform_device *pdev)
496 {
497 	struct palmas_gpadc *adc;
498 	struct palmas_platform_data *pdata;
499 	struct palmas_gpadc_platform_data *gpadc_pdata = NULL;
500 	struct iio_dev *indio_dev;
501 	int ret, i;
502 
503 	pdata = dev_get_platdata(pdev->dev.parent);
504 
505 	if (pdata && pdata->gpadc_pdata)
506 		gpadc_pdata = pdata->gpadc_pdata;
507 
508 	if (!gpadc_pdata && pdev->dev.of_node) {
509 		ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata);
510 		if (ret < 0)
511 			return ret;
512 	}
513 	if (!gpadc_pdata)
514 		return -EINVAL;
515 
516 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
517 	if (!indio_dev) {
518 		dev_err(&pdev->dev, "iio_device_alloc failed\n");
519 		return -ENOMEM;
520 	}
521 
522 	adc = iio_priv(indio_dev);
523 	adc->dev = &pdev->dev;
524 	adc->palmas = dev_get_drvdata(pdev->dev.parent);
525 	adc->adc_info = palmas_gpadc_info;
526 
527 	mutex_init(&adc->lock);
528 
529 	init_completion(&adc->conv_completion);
530 	platform_set_drvdata(pdev, indio_dev);
531 
532 	adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms;
533 	adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
534 	if (adc->irq < 0) {
535 		dev_err(adc->dev,
536 			"get virq failed: %d\n", adc->irq);
537 		ret = adc->irq;
538 		goto out;
539 	}
540 	ret = request_threaded_irq(adc->irq, NULL,
541 		palmas_gpadc_irq,
542 		IRQF_ONESHOT, dev_name(adc->dev),
543 		adc);
544 	if (ret < 0) {
545 		dev_err(adc->dev,
546 			"request irq %d failed: %d\n", adc->irq, ret);
547 		goto out;
548 	}
549 
550 	if (gpadc_pdata->adc_wakeup1_data) {
551 		memcpy(&adc->wakeup1_data, gpadc_pdata->adc_wakeup1_data,
552 			sizeof(adc->wakeup1_data));
553 		adc->wakeup1_enable = true;
554 		adc->irq_auto_0 =  platform_get_irq(pdev, 1);
555 		ret = request_threaded_irq(adc->irq_auto_0, NULL,
556 				palmas_gpadc_irq_auto,
557 				IRQF_ONESHOT,
558 				"palmas-adc-auto-0", adc);
559 		if (ret < 0) {
560 			dev_err(adc->dev, "request auto0 irq %d failed: %d\n",
561 				adc->irq_auto_0, ret);
562 			goto out_irq_free;
563 		}
564 	}
565 
566 	if (gpadc_pdata->adc_wakeup2_data) {
567 		memcpy(&adc->wakeup2_data, gpadc_pdata->adc_wakeup2_data,
568 				sizeof(adc->wakeup2_data));
569 		adc->wakeup2_enable = true;
570 		adc->irq_auto_1 =  platform_get_irq(pdev, 2);
571 		ret = request_threaded_irq(adc->irq_auto_1, NULL,
572 				palmas_gpadc_irq_auto,
573 				IRQF_ONESHOT,
574 				"palmas-adc-auto-1", adc);
575 		if (ret < 0) {
576 			dev_err(adc->dev, "request auto1 irq %d failed: %d\n",
577 				adc->irq_auto_1, ret);
578 			goto out_irq_auto0_free;
579 		}
580 	}
581 
582 	/* set the current source 0 (value 0/5/15/20 uA => 0..3) */
583 	if (gpadc_pdata->ch0_current <= 1)
584 		adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
585 	else if (gpadc_pdata->ch0_current <= 5)
586 		adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
587 	else if (gpadc_pdata->ch0_current <= 15)
588 		adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
589 	else
590 		adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
591 
592 	/* set the current source 3 (value 0/10/400/800 uA => 0..3) */
593 	if (gpadc_pdata->ch3_current <= 1)
594 		adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
595 	else if (gpadc_pdata->ch3_current <= 10)
596 		adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
597 	else if (gpadc_pdata->ch3_current <= 400)
598 		adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
599 	else
600 		adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
601 
602 	adc->extended_delay = gpadc_pdata->extended_delay;
603 
604 	indio_dev->name = MOD_NAME;
605 	indio_dev->info = &palmas_gpadc_iio_info;
606 	indio_dev->modes = INDIO_DIRECT_MODE;
607 	indio_dev->channels = palmas_gpadc_iio_channel;
608 	indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
609 
610 	ret = iio_device_register(indio_dev);
611 	if (ret < 0) {
612 		dev_err(adc->dev, "iio_device_register() failed: %d\n", ret);
613 		goto out_irq_auto1_free;
614 	}
615 
616 	device_set_wakeup_capable(&pdev->dev, 1);
617 	for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
618 		if (!(adc->adc_info[i].is_uncalibrated))
619 			palmas_gpadc_calibrate(adc, i);
620 	}
621 
622 	if (adc->wakeup1_enable || adc->wakeup2_enable)
623 		device_wakeup_enable(&pdev->dev);
624 
625 	return 0;
626 
627 out_irq_auto1_free:
628 	if (gpadc_pdata->adc_wakeup2_data)
629 		free_irq(adc->irq_auto_1, adc);
630 out_irq_auto0_free:
631 	if (gpadc_pdata->adc_wakeup1_data)
632 		free_irq(adc->irq_auto_0, adc);
633 out_irq_free:
634 	free_irq(adc->irq, adc);
635 out:
636 	return ret;
637 }
638 
639 static int palmas_gpadc_remove(struct platform_device *pdev)
640 {
641 	struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev);
642 	struct palmas_gpadc *adc = iio_priv(indio_dev);
643 
644 	if (adc->wakeup1_enable || adc->wakeup2_enable)
645 		device_wakeup_disable(&pdev->dev);
646 	iio_device_unregister(indio_dev);
647 	free_irq(adc->irq, adc);
648 	if (adc->wakeup1_enable)
649 		free_irq(adc->irq_auto_0, adc);
650 	if (adc->wakeup2_enable)
651 		free_irq(adc->irq_auto_1, adc);
652 
653 	return 0;
654 }
655 
656 #ifdef CONFIG_PM_SLEEP
657 static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc)
658 {
659 	int adc_period, conv;
660 	int i;
661 	int ch0 = 0, ch1 = 0;
662 	int thres;
663 	int ret;
664 
665 	adc_period = adc->auto_conversion_period;
666 	for (i = 0; i < 16; ++i) {
667 		if (((1000 * (1 << i)) / 32) >= adc_period)
668 			break;
669 	}
670 	if (i > 0)
671 		i--;
672 	adc_period = i;
673 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
674 			PALMAS_GPADC_AUTO_CTRL,
675 			PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
676 			adc_period);
677 	if (ret < 0) {
678 		dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
679 		return ret;
680 	}
681 
682 	conv = 0;
683 	if (adc->wakeup1_enable) {
684 		int polarity;
685 
686 		ch0 = adc->wakeup1_data.adc_channel_number;
687 		conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
688 		if (adc->wakeup1_data.adc_high_threshold > 0) {
689 			thres = adc->wakeup1_data.adc_high_threshold;
690 			polarity = 0;
691 		} else {
692 			thres = adc->wakeup1_data.adc_low_threshold;
693 			polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL;
694 		}
695 
696 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
697 				PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
698 		if (ret < 0) {
699 			dev_err(adc->dev,
700 				"THRES_CONV0_LSB write failed: %d\n", ret);
701 			return ret;
702 		}
703 
704 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
705 				PALMAS_GPADC_THRES_CONV0_MSB,
706 				((thres >> 8) & 0xF) | polarity);
707 		if (ret < 0) {
708 			dev_err(adc->dev,
709 				"THRES_CONV0_MSB write failed: %d\n", ret);
710 			return ret;
711 		}
712 	}
713 
714 	if (adc->wakeup2_enable) {
715 		int polarity;
716 
717 		ch1 = adc->wakeup2_data.adc_channel_number;
718 		conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
719 		if (adc->wakeup2_data.adc_high_threshold > 0) {
720 			thres = adc->wakeup2_data.adc_high_threshold;
721 			polarity = 0;
722 		} else {
723 			thres = adc->wakeup2_data.adc_low_threshold;
724 			polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL;
725 		}
726 
727 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
728 				PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
729 		if (ret < 0) {
730 			dev_err(adc->dev,
731 				"THRES_CONV1_LSB write failed: %d\n", ret);
732 			return ret;
733 		}
734 
735 		ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
736 				PALMAS_GPADC_THRES_CONV1_MSB,
737 				((thres >> 8) & 0xF) | polarity);
738 		if (ret < 0) {
739 			dev_err(adc->dev,
740 				"THRES_CONV1_MSB write failed: %d\n", ret);
741 			return ret;
742 		}
743 	}
744 
745 	ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
746 			PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
747 	if (ret < 0) {
748 		dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
749 		return ret;
750 	}
751 
752 	ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
753 			PALMAS_GPADC_AUTO_CTRL,
754 			PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
755 			PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
756 	if (ret < 0)
757 		dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
758 
759 	return ret;
760 }
761 
762 static int palmas_adc_wakeup_reset(struct palmas_gpadc *adc)
763 {
764 	int ret;
765 
766 	ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
767 			PALMAS_GPADC_AUTO_SELECT, 0);
768 	if (ret < 0) {
769 		dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
770 		return ret;
771 	}
772 
773 	ret = palmas_disable_auto_conversion(adc);
774 	if (ret < 0)
775 		dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
776 
777 	return ret;
778 }
779 
780 static int palmas_gpadc_suspend(struct device *dev)
781 {
782 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
783 	struct palmas_gpadc *adc = iio_priv(indio_dev);
784 	int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
785 	int ret;
786 
787 	if (!device_may_wakeup(dev) || !wakeup)
788 		return 0;
789 
790 	ret = palmas_adc_wakeup_configure(adc);
791 	if (ret < 0)
792 		return ret;
793 
794 	if (adc->wakeup1_enable)
795 		enable_irq_wake(adc->irq_auto_0);
796 
797 	if (adc->wakeup2_enable)
798 		enable_irq_wake(adc->irq_auto_1);
799 
800 	return 0;
801 }
802 
803 static int palmas_gpadc_resume(struct device *dev)
804 {
805 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
806 	struct palmas_gpadc *adc = iio_priv(indio_dev);
807 	int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
808 	int ret;
809 
810 	if (!device_may_wakeup(dev) || !wakeup)
811 		return 0;
812 
813 	ret = palmas_adc_wakeup_reset(adc);
814 	if (ret < 0)
815 		return ret;
816 
817 	if (adc->wakeup1_enable)
818 		disable_irq_wake(adc->irq_auto_0);
819 
820 	if (adc->wakeup2_enable)
821 		disable_irq_wake(adc->irq_auto_1);
822 
823 	return 0;
824 };
825 #endif
826 
827 static const struct dev_pm_ops palmas_pm_ops = {
828 	SET_SYSTEM_SLEEP_PM_OPS(palmas_gpadc_suspend,
829 				palmas_gpadc_resume)
830 };
831 
832 static const struct of_device_id of_palmas_gpadc_match_tbl[] = {
833 	{ .compatible = "ti,palmas-gpadc", },
834 	{ /* end */ }
835 };
836 MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl);
837 
838 static struct platform_driver palmas_gpadc_driver = {
839 	.probe = palmas_gpadc_probe,
840 	.remove = palmas_gpadc_remove,
841 	.driver = {
842 		.name = MOD_NAME,
843 		.pm = &palmas_pm_ops,
844 		.of_match_table = of_palmas_gpadc_match_tbl,
845 	},
846 };
847 module_platform_driver(palmas_gpadc_driver);
848 
849 MODULE_DESCRIPTION("palmas GPADC driver");
850 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>");
851 MODULE_ALIAS("platform:palmas-gpadc");
852 MODULE_LICENSE("GPL v2");
853