1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for the Nuvoton NAU7802 ADC 4 * 5 * Copyright 2013 Free Electrons 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/i2c.h> 10 #include <linux/interrupt.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/property.h> 14 #include <linux/wait.h> 15 #include <linux/log2.h> 16 17 #include <linux/iio/iio.h> 18 #include <linux/iio/sysfs.h> 19 20 #define NAU7802_REG_PUCTRL 0x00 21 #define NAU7802_PUCTRL_RR(x) (x << 0) 22 #define NAU7802_PUCTRL_RR_BIT NAU7802_PUCTRL_RR(1) 23 #define NAU7802_PUCTRL_PUD(x) (x << 1) 24 #define NAU7802_PUCTRL_PUD_BIT NAU7802_PUCTRL_PUD(1) 25 #define NAU7802_PUCTRL_PUA(x) (x << 2) 26 #define NAU7802_PUCTRL_PUA_BIT NAU7802_PUCTRL_PUA(1) 27 #define NAU7802_PUCTRL_PUR(x) (x << 3) 28 #define NAU7802_PUCTRL_PUR_BIT NAU7802_PUCTRL_PUR(1) 29 #define NAU7802_PUCTRL_CS(x) (x << 4) 30 #define NAU7802_PUCTRL_CS_BIT NAU7802_PUCTRL_CS(1) 31 #define NAU7802_PUCTRL_CR(x) (x << 5) 32 #define NAU7802_PUCTRL_CR_BIT NAU7802_PUCTRL_CR(1) 33 #define NAU7802_PUCTRL_AVDDS(x) (x << 7) 34 #define NAU7802_PUCTRL_AVDDS_BIT NAU7802_PUCTRL_AVDDS(1) 35 #define NAU7802_REG_CTRL1 0x01 36 #define NAU7802_CTRL1_VLDO(x) (x << 3) 37 #define NAU7802_CTRL1_GAINS(x) (x) 38 #define NAU7802_CTRL1_GAINS_BITS 0x07 39 #define NAU7802_REG_CTRL2 0x02 40 #define NAU7802_CTRL2_CHS(x) (x << 7) 41 #define NAU7802_CTRL2_CRS(x) (x << 4) 42 #define NAU7802_SAMP_FREQ_320 0x07 43 #define NAU7802_CTRL2_CHS_BIT NAU7802_CTRL2_CHS(1) 44 #define NAU7802_REG_ADC_B2 0x12 45 #define NAU7802_REG_ADC_B1 0x13 46 #define NAU7802_REG_ADC_B0 0x14 47 #define NAU7802_REG_ADC_CTRL 0x15 48 49 #define NAU7802_MIN_CONVERSIONS 6 50 51 struct nau7802_state { 52 struct i2c_client *client; 53 s32 last_value; 54 struct mutex lock; 55 struct mutex data_lock; 56 u32 vref_mv; 57 u32 conversion_count; 58 u32 min_conversions; 59 u8 sample_rate; 60 u32 scale_avail[8]; 61 struct completion value_ok; 62 }; 63 64 #define NAU7802_CHANNEL(chan) { \ 65 .type = IIO_VOLTAGE, \ 66 .indexed = 1, \ 67 .channel = (chan), \ 68 .scan_index = (chan), \ 69 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 70 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 71 BIT(IIO_CHAN_INFO_SAMP_FREQ) \ 72 } 73 74 static const struct iio_chan_spec nau7802_chan_array[] = { 75 NAU7802_CHANNEL(0), 76 NAU7802_CHANNEL(1), 77 }; 78 79 static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80, 80 10, 10, 10, 320}; 81 82 static ssize_t nau7802_show_scales(struct device *dev, 83 struct device_attribute *attr, char *buf) 84 { 85 struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev)); 86 int i, len = 0; 87 88 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 89 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09d ", 90 st->scale_avail[i]); 91 92 buf[len-1] = '\n'; 93 94 return len; 95 } 96 97 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320"); 98 99 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, nau7802_show_scales, 100 NULL, 0); 101 102 static struct attribute *nau7802_attributes[] = { 103 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 104 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 105 NULL 106 }; 107 108 static const struct attribute_group nau7802_attribute_group = { 109 .attrs = nau7802_attributes, 110 }; 111 112 static int nau7802_set_gain(struct nau7802_state *st, int gain) 113 { 114 int ret; 115 116 mutex_lock(&st->lock); 117 st->conversion_count = 0; 118 119 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1); 120 if (ret < 0) 121 goto nau7802_sysfs_set_gain_out; 122 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1, 123 (ret & (~NAU7802_CTRL1_GAINS_BITS)) | 124 gain); 125 126 nau7802_sysfs_set_gain_out: 127 mutex_unlock(&st->lock); 128 129 return ret; 130 } 131 132 static int nau7802_read_conversion(struct nau7802_state *st) 133 { 134 int data; 135 136 mutex_lock(&st->data_lock); 137 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2); 138 if (data < 0) 139 goto nau7802_read_conversion_out; 140 st->last_value = data << 16; 141 142 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1); 143 if (data < 0) 144 goto nau7802_read_conversion_out; 145 st->last_value |= data << 8; 146 147 data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0); 148 if (data < 0) 149 goto nau7802_read_conversion_out; 150 st->last_value |= data; 151 152 st->last_value = sign_extend32(st->last_value, 23); 153 154 nau7802_read_conversion_out: 155 mutex_unlock(&st->data_lock); 156 157 return data; 158 } 159 160 /* 161 * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT 162 */ 163 static int nau7802_sync(struct nau7802_state *st) 164 { 165 int ret; 166 167 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL); 168 if (ret < 0) 169 return ret; 170 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, 171 ret | NAU7802_PUCTRL_CS_BIT); 172 173 return ret; 174 } 175 176 static irqreturn_t nau7802_eoc_trigger(int irq, void *private) 177 { 178 struct iio_dev *indio_dev = private; 179 struct nau7802_state *st = iio_priv(indio_dev); 180 int status; 181 182 status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL); 183 if (status < 0) 184 return IRQ_HANDLED; 185 186 if (!(status & NAU7802_PUCTRL_CR_BIT)) 187 return IRQ_NONE; 188 189 if (nau7802_read_conversion(st) < 0) 190 return IRQ_HANDLED; 191 192 /* 193 * Because there is actually only one ADC for both channels, we have to 194 * wait for enough conversions to happen before getting a significant 195 * value when changing channels and the values are far apart. 196 */ 197 if (st->conversion_count < NAU7802_MIN_CONVERSIONS) 198 st->conversion_count++; 199 if (st->conversion_count >= NAU7802_MIN_CONVERSIONS) 200 complete(&st->value_ok); 201 202 return IRQ_HANDLED; 203 } 204 205 static int nau7802_read_irq(struct iio_dev *indio_dev, 206 struct iio_chan_spec const *chan, 207 int *val) 208 { 209 struct nau7802_state *st = iio_priv(indio_dev); 210 int ret; 211 212 reinit_completion(&st->value_ok); 213 enable_irq(st->client->irq); 214 215 nau7802_sync(st); 216 217 /* read registers to ensure we flush everything */ 218 ret = nau7802_read_conversion(st); 219 if (ret < 0) 220 goto read_chan_info_failure; 221 222 /* Wait for a conversion to finish */ 223 ret = wait_for_completion_interruptible_timeout(&st->value_ok, 224 msecs_to_jiffies(1000)); 225 if (ret == 0) 226 ret = -ETIMEDOUT; 227 228 if (ret < 0) 229 goto read_chan_info_failure; 230 231 disable_irq(st->client->irq); 232 233 *val = st->last_value; 234 235 return IIO_VAL_INT; 236 237 read_chan_info_failure: 238 disable_irq(st->client->irq); 239 240 return ret; 241 } 242 243 static int nau7802_read_poll(struct iio_dev *indio_dev, 244 struct iio_chan_spec const *chan, 245 int *val) 246 { 247 struct nau7802_state *st = iio_priv(indio_dev); 248 int ret; 249 250 nau7802_sync(st); 251 252 /* read registers to ensure we flush everything */ 253 ret = nau7802_read_conversion(st); 254 if (ret < 0) 255 return ret; 256 257 /* 258 * Because there is actually only one ADC for both channels, we have to 259 * wait for enough conversions to happen before getting a significant 260 * value when changing channels and the values are far appart. 261 */ 262 do { 263 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL); 264 if (ret < 0) 265 return ret; 266 267 while (!(ret & NAU7802_PUCTRL_CR_BIT)) { 268 if (st->sample_rate != NAU7802_SAMP_FREQ_320) 269 msleep(20); 270 else 271 mdelay(4); 272 ret = i2c_smbus_read_byte_data(st->client, 273 NAU7802_REG_PUCTRL); 274 if (ret < 0) 275 return ret; 276 } 277 278 ret = nau7802_read_conversion(st); 279 if (ret < 0) 280 return ret; 281 if (st->conversion_count < NAU7802_MIN_CONVERSIONS) 282 st->conversion_count++; 283 } while (st->conversion_count < NAU7802_MIN_CONVERSIONS); 284 285 *val = st->last_value; 286 287 return IIO_VAL_INT; 288 } 289 290 static int nau7802_read_raw(struct iio_dev *indio_dev, 291 struct iio_chan_spec const *chan, 292 int *val, int *val2, long mask) 293 { 294 struct nau7802_state *st = iio_priv(indio_dev); 295 int ret; 296 297 switch (mask) { 298 case IIO_CHAN_INFO_RAW: 299 mutex_lock(&st->lock); 300 /* 301 * Select the channel to use 302 * - Channel 1 is value 0 in the CHS register 303 * - Channel 2 is value 1 in the CHS register 304 */ 305 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2); 306 if (ret < 0) { 307 mutex_unlock(&st->lock); 308 return ret; 309 } 310 311 if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) || 312 (!(ret & NAU7802_CTRL2_CHS_BIT) && 313 chan->channel)) { 314 st->conversion_count = 0; 315 ret = i2c_smbus_write_byte_data(st->client, 316 NAU7802_REG_CTRL2, 317 NAU7802_CTRL2_CHS(chan->channel) | 318 NAU7802_CTRL2_CRS(st->sample_rate)); 319 320 if (ret < 0) { 321 mutex_unlock(&st->lock); 322 return ret; 323 } 324 } 325 326 if (st->client->irq) 327 ret = nau7802_read_irq(indio_dev, chan, val); 328 else 329 ret = nau7802_read_poll(indio_dev, chan, val); 330 331 mutex_unlock(&st->lock); 332 return ret; 333 334 case IIO_CHAN_INFO_SCALE: 335 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1); 336 if (ret < 0) 337 return ret; 338 339 /* 340 * We have 24 bits of signed data, that means 23 bits of data 341 * plus the sign bit 342 */ 343 *val = st->vref_mv; 344 *val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS); 345 346 return IIO_VAL_FRACTIONAL_LOG2; 347 348 case IIO_CHAN_INFO_SAMP_FREQ: 349 *val = nau7802_sample_freq_avail[st->sample_rate]; 350 *val2 = 0; 351 return IIO_VAL_INT; 352 353 default: 354 break; 355 } 356 357 return -EINVAL; 358 } 359 360 static int nau7802_write_raw(struct iio_dev *indio_dev, 361 struct iio_chan_spec const *chan, 362 int val, int val2, long mask) 363 { 364 struct nau7802_state *st = iio_priv(indio_dev); 365 int i, ret; 366 367 switch (mask) { 368 case IIO_CHAN_INFO_SCALE: 369 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 370 if (val2 == st->scale_avail[i]) 371 return nau7802_set_gain(st, i); 372 373 break; 374 375 case IIO_CHAN_INFO_SAMP_FREQ: 376 for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++) 377 if (val == nau7802_sample_freq_avail[i]) { 378 mutex_lock(&st->lock); 379 st->sample_rate = i; 380 st->conversion_count = 0; 381 ret = i2c_smbus_write_byte_data(st->client, 382 NAU7802_REG_CTRL2, 383 NAU7802_CTRL2_CRS(st->sample_rate)); 384 mutex_unlock(&st->lock); 385 return ret; 386 } 387 388 break; 389 390 default: 391 break; 392 } 393 394 return -EINVAL; 395 } 396 397 static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev, 398 struct iio_chan_spec const *chan, 399 long mask) 400 { 401 return IIO_VAL_INT_PLUS_NANO; 402 } 403 404 static const struct iio_info nau7802_info = { 405 .read_raw = &nau7802_read_raw, 406 .write_raw = &nau7802_write_raw, 407 .write_raw_get_fmt = nau7802_write_raw_get_fmt, 408 .attrs = &nau7802_attribute_group, 409 }; 410 411 static int nau7802_probe(struct i2c_client *client) 412 { 413 struct iio_dev *indio_dev; 414 struct nau7802_state *st; 415 int i, ret; 416 u8 data; 417 u32 tmp = 0; 418 419 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st)); 420 if (indio_dev == NULL) 421 return -ENOMEM; 422 423 st = iio_priv(indio_dev); 424 425 indio_dev->name = dev_name(&client->dev); 426 indio_dev->modes = INDIO_DIRECT_MODE; 427 indio_dev->info = &nau7802_info; 428 429 st->client = client; 430 431 /* Reset the device */ 432 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, 433 NAU7802_PUCTRL_RR_BIT); 434 if (ret < 0) 435 return ret; 436 437 /* Enter normal operation mode */ 438 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, 439 NAU7802_PUCTRL_PUD_BIT); 440 if (ret < 0) 441 return ret; 442 443 /* 444 * After about 200 usecs, the device should be ready and then 445 * the Power Up bit will be set to 1. If not, wait for it. 446 */ 447 udelay(210); 448 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL); 449 if (ret < 0) 450 return ret; 451 if (!(ret & NAU7802_PUCTRL_PUR_BIT)) 452 return ret; 453 454 device_property_read_u32(&client->dev, "nuvoton,vldo", &tmp); 455 st->vref_mv = tmp; 456 457 data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT | 458 NAU7802_PUCTRL_CS_BIT; 459 if (tmp >= 2400) 460 data |= NAU7802_PUCTRL_AVDDS_BIT; 461 462 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data); 463 if (ret < 0) 464 return ret; 465 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30); 466 if (ret < 0) 467 return ret; 468 469 if (tmp >= 2400) { 470 data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300); 471 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1, 472 data); 473 if (ret < 0) 474 return ret; 475 } 476 477 /* Populate available ADC input ranges */ 478 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 479 st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL) 480 >> (23 + i); 481 482 init_completion(&st->value_ok); 483 484 /* 485 * The ADC fires continuously and we can't do anything about 486 * it. So we need to have the IRQ disabled by default, and we 487 * will enable them back when we will need them.. 488 */ 489 if (client->irq) { 490 ret = devm_request_threaded_irq(&client->dev, client->irq, 491 NULL, 492 nau7802_eoc_trigger, 493 IRQF_TRIGGER_HIGH | IRQF_ONESHOT | 494 IRQF_NO_AUTOEN, 495 client->dev.driver->name, 496 indio_dev); 497 if (ret) { 498 /* 499 * What may happen here is that our IRQ controller is 500 * not able to get level interrupt but this is required 501 * by this ADC as when going over 40 sample per second, 502 * the interrupt line may stay high between conversions. 503 * So, we continue no matter what but we switch to 504 * polling mode. 505 */ 506 dev_info(&client->dev, 507 "Failed to allocate IRQ, using polling mode\n"); 508 client->irq = 0; 509 } 510 } 511 512 if (!client->irq) { 513 /* 514 * We are polling, use the fastest sample rate by 515 * default 516 */ 517 st->sample_rate = NAU7802_SAMP_FREQ_320; 518 ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2, 519 NAU7802_CTRL2_CRS(st->sample_rate)); 520 if (ret) 521 return ret; 522 } 523 524 /* Setup the ADC channels available on the board */ 525 indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array); 526 indio_dev->channels = nau7802_chan_array; 527 528 mutex_init(&st->lock); 529 mutex_init(&st->data_lock); 530 531 return devm_iio_device_register(&client->dev, indio_dev); 532 } 533 534 static const struct i2c_device_id nau7802_i2c_id[] = { 535 { "nau7802", 0 }, 536 { } 537 }; 538 MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id); 539 540 static const struct of_device_id nau7802_dt_ids[] = { 541 { .compatible = "nuvoton,nau7802" }, 542 {}, 543 }; 544 MODULE_DEVICE_TABLE(of, nau7802_dt_ids); 545 546 static struct i2c_driver nau7802_driver = { 547 .probe = nau7802_probe, 548 .id_table = nau7802_i2c_id, 549 .driver = { 550 .name = "nau7802", 551 .of_match_table = nau7802_dt_ids, 552 }, 553 }; 554 555 module_i2c_driver(nau7802_driver); 556 557 MODULE_LICENSE("GPL"); 558 MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver"); 559 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 560 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>"); 561