1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale MXS LRADC ADC driver 4 * 5 * Copyright (c) 2012 DENX Software Engineering, GmbH. 6 * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 7 * 8 * Authors: 9 * Marek Vasut <marex@denx.de> 10 * Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 11 */ 12 13 #include <linux/completion.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/mfd/core.h> 18 #include <linux/mfd/mxs-lradc.h> 19 #include <linux/module.h> 20 #include <linux/of_irq.h> 21 #include <linux/platform_device.h> 22 #include <linux/sysfs.h> 23 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/iio/sysfs.h> 30 31 /* 32 * Make this runtime configurable if necessary. Currently, if the buffered mode 33 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before 34 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000) 35 * seconds. The result is that the samples arrive every 500mS. 36 */ 37 #define LRADC_DELAY_TIMER_PER 200 38 #define LRADC_DELAY_TIMER_LOOP 5 39 40 #define VREF_MV_BASE 1850 41 42 static const char *mx23_lradc_adc_irq_names[] = { 43 "mxs-lradc-channel0", 44 "mxs-lradc-channel1", 45 "mxs-lradc-channel2", 46 "mxs-lradc-channel3", 47 "mxs-lradc-channel4", 48 "mxs-lradc-channel5", 49 }; 50 51 static const char *mx28_lradc_adc_irq_names[] = { 52 "mxs-lradc-thresh0", 53 "mxs-lradc-thresh1", 54 "mxs-lradc-channel0", 55 "mxs-lradc-channel1", 56 "mxs-lradc-channel2", 57 "mxs-lradc-channel3", 58 "mxs-lradc-channel4", 59 "mxs-lradc-channel5", 60 "mxs-lradc-button0", 61 "mxs-lradc-button1", 62 }; 63 64 static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = { 65 [IMX23_LRADC] = { 66 VREF_MV_BASE, /* CH0 */ 67 VREF_MV_BASE, /* CH1 */ 68 VREF_MV_BASE, /* CH2 */ 69 VREF_MV_BASE, /* CH3 */ 70 VREF_MV_BASE, /* CH4 */ 71 VREF_MV_BASE, /* CH5 */ 72 VREF_MV_BASE * 2, /* CH6 VDDIO */ 73 VREF_MV_BASE * 4, /* CH7 VBATT */ 74 VREF_MV_BASE, /* CH8 Temp sense 0 */ 75 VREF_MV_BASE, /* CH9 Temp sense 1 */ 76 VREF_MV_BASE, /* CH10 */ 77 VREF_MV_BASE, /* CH11 */ 78 VREF_MV_BASE, /* CH12 USB_DP */ 79 VREF_MV_BASE, /* CH13 USB_DN */ 80 VREF_MV_BASE, /* CH14 VBG */ 81 VREF_MV_BASE * 4, /* CH15 VDD5V */ 82 }, 83 [IMX28_LRADC] = { 84 VREF_MV_BASE, /* CH0 */ 85 VREF_MV_BASE, /* CH1 */ 86 VREF_MV_BASE, /* CH2 */ 87 VREF_MV_BASE, /* CH3 */ 88 VREF_MV_BASE, /* CH4 */ 89 VREF_MV_BASE, /* CH5 */ 90 VREF_MV_BASE, /* CH6 */ 91 VREF_MV_BASE * 4, /* CH7 VBATT */ 92 VREF_MV_BASE, /* CH8 Temp sense 0 */ 93 VREF_MV_BASE, /* CH9 Temp sense 1 */ 94 VREF_MV_BASE * 2, /* CH10 VDDIO */ 95 VREF_MV_BASE, /* CH11 VTH */ 96 VREF_MV_BASE * 2, /* CH12 VDDA */ 97 VREF_MV_BASE, /* CH13 VDDD */ 98 VREF_MV_BASE, /* CH14 VBG */ 99 VREF_MV_BASE * 4, /* CH15 VDD5V */ 100 }, 101 }; 102 103 enum mxs_lradc_divbytwo { 104 MXS_LRADC_DIV_DISABLED = 0, 105 MXS_LRADC_DIV_ENABLED, 106 }; 107 108 struct mxs_lradc_scale { 109 unsigned int integer; 110 unsigned int nano; 111 }; 112 113 struct mxs_lradc_adc { 114 struct mxs_lradc *lradc; 115 struct device *dev; 116 117 void __iomem *base; 118 u32 buffer[10]; 119 struct iio_trigger *trig; 120 struct completion completion; 121 spinlock_t lock; 122 123 const u32 *vref_mv; 124 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2]; 125 unsigned long is_divided; 126 }; 127 128 129 /* Raw I/O operations */ 130 static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan, 131 int *val) 132 { 133 struct mxs_lradc_adc *adc = iio_priv(iio_dev); 134 struct mxs_lradc *lradc = adc->lradc; 135 int ret; 136 137 /* 138 * See if there is no buffered operation in progress. If there is simply 139 * bail out. This can be improved to support both buffered and raw IO at 140 * the same time, yet the code becomes horribly complicated. Therefore I 141 * applied KISS principle here. 142 */ 143 ret = iio_device_claim_direct_mode(iio_dev); 144 if (ret) 145 return ret; 146 147 reinit_completion(&adc->completion); 148 149 /* 150 * No buffered operation in progress, map the channel and trigger it. 151 * Virtual channel 0 is always used here as the others are always not 152 * used if doing raw sampling. 153 */ 154 if (lradc->soc == IMX28_LRADC) 155 writel(LRADC_CTRL1_LRADC_IRQ_EN(0), 156 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 157 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 158 159 /* Enable / disable the divider per requirement */ 160 if (test_bit(chan, &adc->is_divided)) 161 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, 162 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); 163 else 164 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, 165 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); 166 167 /* Clean the slot's previous content, then set new one. */ 168 writel(LRADC_CTRL4_LRADCSELECT_MASK(0), 169 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); 170 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); 171 172 writel(0, adc->base + LRADC_CH(0)); 173 174 /* Enable the IRQ and start sampling the channel. */ 175 writel(LRADC_CTRL1_LRADC_IRQ_EN(0), 176 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); 177 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); 178 179 /* Wait for completion on the channel, 1 second max. */ 180 ret = wait_for_completion_killable_timeout(&adc->completion, HZ); 181 if (!ret) 182 ret = -ETIMEDOUT; 183 if (ret < 0) 184 goto err; 185 186 /* Read the data. */ 187 *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; 188 ret = IIO_VAL_INT; 189 190 err: 191 writel(LRADC_CTRL1_LRADC_IRQ_EN(0), 192 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 193 194 iio_device_release_direct_mode(iio_dev); 195 196 return ret; 197 } 198 199 static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val) 200 { 201 int ret, min, max; 202 203 ret = mxs_lradc_adc_read_single(iio_dev, 8, &min); 204 if (ret != IIO_VAL_INT) 205 return ret; 206 207 ret = mxs_lradc_adc_read_single(iio_dev, 9, &max); 208 if (ret != IIO_VAL_INT) 209 return ret; 210 211 *val = max - min; 212 213 return IIO_VAL_INT; 214 } 215 216 static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev, 217 const struct iio_chan_spec *chan, 218 int *val, int *val2, long m) 219 { 220 struct mxs_lradc_adc *adc = iio_priv(iio_dev); 221 222 switch (m) { 223 case IIO_CHAN_INFO_RAW: 224 if (chan->type == IIO_TEMP) 225 return mxs_lradc_adc_read_temp(iio_dev, val); 226 227 return mxs_lradc_adc_read_single(iio_dev, chan->channel, val); 228 229 case IIO_CHAN_INFO_SCALE: 230 if (chan->type == IIO_TEMP) { 231 /* 232 * From the datasheet, we have to multiply by 1.012 and 233 * divide by 4 234 */ 235 *val = 0; 236 *val2 = 253000; 237 return IIO_VAL_INT_PLUS_MICRO; 238 } 239 240 *val = adc->vref_mv[chan->channel]; 241 *val2 = chan->scan_type.realbits - 242 test_bit(chan->channel, &adc->is_divided); 243 return IIO_VAL_FRACTIONAL_LOG2; 244 245 case IIO_CHAN_INFO_OFFSET: 246 if (chan->type == IIO_TEMP) { 247 /* 248 * The calculated value from the ADC is in Kelvin, we 249 * want Celsius for hwmon so the offset is -273.15 250 * The offset is applied before scaling so it is 251 * actually -213.15 * 4 / 1.012 = -1079.644268 252 */ 253 *val = -1079; 254 *val2 = 644268; 255 256 return IIO_VAL_INT_PLUS_MICRO; 257 } 258 259 return -EINVAL; 260 261 default: 262 break; 263 } 264 265 return -EINVAL; 266 } 267 268 static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev, 269 const struct iio_chan_spec *chan, 270 int val, int val2, long m) 271 { 272 struct mxs_lradc_adc *adc = iio_priv(iio_dev); 273 struct mxs_lradc_scale *scale_avail = 274 adc->scale_avail[chan->channel]; 275 int ret; 276 277 ret = iio_device_claim_direct_mode(iio_dev); 278 if (ret) 279 return ret; 280 281 switch (m) { 282 case IIO_CHAN_INFO_SCALE: 283 ret = -EINVAL; 284 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer && 285 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) { 286 /* divider by two disabled */ 287 clear_bit(chan->channel, &adc->is_divided); 288 ret = 0; 289 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer && 290 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) { 291 /* divider by two enabled */ 292 set_bit(chan->channel, &adc->is_divided); 293 ret = 0; 294 } 295 296 break; 297 default: 298 ret = -EINVAL; 299 break; 300 } 301 302 iio_device_release_direct_mode(iio_dev); 303 304 return ret; 305 } 306 307 static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev, 308 const struct iio_chan_spec *chan, 309 long m) 310 { 311 return IIO_VAL_INT_PLUS_NANO; 312 } 313 314 static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev, 315 struct device_attribute *attr, 316 char *buf) 317 { 318 struct iio_dev *iio = dev_to_iio_dev(dev); 319 struct mxs_lradc_adc *adc = iio_priv(iio); 320 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr); 321 int i, ch, len = 0; 322 323 ch = iio_attr->address; 324 for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++) 325 len += sprintf(buf + len, "%u.%09u ", 326 adc->scale_avail[ch][i].integer, 327 adc->scale_avail[ch][i].nano); 328 329 len += sprintf(buf + len, "\n"); 330 331 return len; 332 } 333 334 #define SHOW_SCALE_AVAILABLE_ATTR(ch)\ 335 IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\ 336 mxs_lradc_adc_show_scale_avail, NULL, ch) 337 338 static SHOW_SCALE_AVAILABLE_ATTR(0); 339 static SHOW_SCALE_AVAILABLE_ATTR(1); 340 static SHOW_SCALE_AVAILABLE_ATTR(2); 341 static SHOW_SCALE_AVAILABLE_ATTR(3); 342 static SHOW_SCALE_AVAILABLE_ATTR(4); 343 static SHOW_SCALE_AVAILABLE_ATTR(5); 344 static SHOW_SCALE_AVAILABLE_ATTR(6); 345 static SHOW_SCALE_AVAILABLE_ATTR(7); 346 static SHOW_SCALE_AVAILABLE_ATTR(10); 347 static SHOW_SCALE_AVAILABLE_ATTR(11); 348 static SHOW_SCALE_AVAILABLE_ATTR(12); 349 static SHOW_SCALE_AVAILABLE_ATTR(13); 350 static SHOW_SCALE_AVAILABLE_ATTR(14); 351 static SHOW_SCALE_AVAILABLE_ATTR(15); 352 353 static struct attribute *mxs_lradc_adc_attributes[] = { 354 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr, 355 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr, 356 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr, 357 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr, 358 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr, 359 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr, 360 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr, 361 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr, 362 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr, 363 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr, 364 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr, 365 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr, 366 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr, 367 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr, 368 NULL 369 }; 370 371 static const struct attribute_group mxs_lradc_adc_attribute_group = { 372 .attrs = mxs_lradc_adc_attributes, 373 }; 374 375 static const struct iio_info mxs_lradc_adc_iio_info = { 376 .read_raw = mxs_lradc_adc_read_raw, 377 .write_raw = mxs_lradc_adc_write_raw, 378 .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt, 379 .attrs = &mxs_lradc_adc_attribute_group, 380 }; 381 382 /* IRQ Handling */ 383 static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data) 384 { 385 struct iio_dev *iio = data; 386 struct mxs_lradc_adc *adc = iio_priv(iio); 387 struct mxs_lradc *lradc = adc->lradc; 388 unsigned long reg = readl(adc->base + LRADC_CTRL1); 389 unsigned long flags; 390 391 if (!(reg & mxs_lradc_irq_mask(lradc))) 392 return IRQ_NONE; 393 394 if (iio_buffer_enabled(iio)) { 395 if (reg & lradc->buffer_vchans) { 396 spin_lock_irqsave(&adc->lock, flags); 397 iio_trigger_poll(iio->trig); 398 spin_unlock_irqrestore(&adc->lock, flags); 399 } 400 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) { 401 complete(&adc->completion); 402 } 403 404 writel(reg & mxs_lradc_irq_mask(lradc), 405 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 406 407 return IRQ_HANDLED; 408 } 409 410 411 /* Trigger handling */ 412 static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p) 413 { 414 struct iio_poll_func *pf = p; 415 struct iio_dev *iio = pf->indio_dev; 416 struct mxs_lradc_adc *adc = iio_priv(iio); 417 const u32 chan_value = LRADC_CH_ACCUMULATE | 418 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); 419 unsigned int i, j = 0; 420 421 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { 422 adc->buffer[j] = readl(adc->base + LRADC_CH(j)); 423 writel(chan_value, adc->base + LRADC_CH(j)); 424 adc->buffer[j] &= LRADC_CH_VALUE_MASK; 425 adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP; 426 j++; 427 } 428 429 iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp); 430 431 iio_trigger_notify_done(iio->trig); 432 433 return IRQ_HANDLED; 434 } 435 436 static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state) 437 { 438 struct iio_dev *iio = iio_trigger_get_drvdata(trig); 439 struct mxs_lradc_adc *adc = iio_priv(iio); 440 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; 441 442 writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st)); 443 444 return 0; 445 } 446 447 static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = { 448 .set_trigger_state = &mxs_lradc_adc_configure_trigger, 449 }; 450 451 static int mxs_lradc_adc_trigger_init(struct iio_dev *iio) 452 { 453 int ret; 454 struct iio_trigger *trig; 455 struct mxs_lradc_adc *adc = iio_priv(iio); 456 457 trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name, 458 iio->id); 459 if (!trig) 460 return -ENOMEM; 461 462 trig->dev.parent = adc->dev; 463 iio_trigger_set_drvdata(trig, iio); 464 trig->ops = &mxs_lradc_adc_trigger_ops; 465 466 ret = iio_trigger_register(trig); 467 if (ret) 468 return ret; 469 470 adc->trig = trig; 471 472 return 0; 473 } 474 475 static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio) 476 { 477 struct mxs_lradc_adc *adc = iio_priv(iio); 478 479 iio_trigger_unregister(adc->trig); 480 } 481 482 static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio) 483 { 484 struct mxs_lradc_adc *adc = iio_priv(iio); 485 struct mxs_lradc *lradc = adc->lradc; 486 int chan, ofs = 0; 487 unsigned long enable = 0; 488 u32 ctrl4_set = 0; 489 u32 ctrl4_clr = 0; 490 u32 ctrl1_irq = 0; 491 const u32 chan_value = LRADC_CH_ACCUMULATE | 492 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); 493 494 if (lradc->soc == IMX28_LRADC) 495 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET, 496 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 497 writel(lradc->buffer_vchans, 498 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 499 500 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { 501 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs); 502 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs); 503 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs); 504 writel(chan_value, adc->base + LRADC_CH(ofs)); 505 bitmap_set(&enable, ofs, 1); 506 ofs++; 507 } 508 509 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK, 510 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); 511 writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); 512 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); 513 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); 514 writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET, 515 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET); 516 517 return 0; 518 } 519 520 static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio) 521 { 522 struct mxs_lradc_adc *adc = iio_priv(iio); 523 struct mxs_lradc *lradc = adc->lradc; 524 525 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK, 526 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); 527 528 writel(lradc->buffer_vchans, 529 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 530 if (lradc->soc == IMX28_LRADC) 531 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET, 532 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 533 534 return 0; 535 } 536 537 static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio, 538 const unsigned long *mask) 539 { 540 struct mxs_lradc_adc *adc = iio_priv(iio); 541 struct mxs_lradc *lradc = adc->lradc; 542 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS); 543 int rsvd_chans = 0; 544 unsigned long rsvd_mask = 0; 545 546 if (lradc->use_touchbutton) 547 rsvd_mask |= CHAN_MASK_TOUCHBUTTON; 548 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE) 549 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE; 550 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE) 551 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE; 552 553 if (lradc->use_touchbutton) 554 rsvd_chans++; 555 if (lradc->touchscreen_wire) 556 rsvd_chans += 2; 557 558 /* Test for attempts to map channels with special mode of operation. */ 559 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS)) 560 return false; 561 562 /* Test for attempts to map more channels then available slots. */ 563 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS) 564 return false; 565 566 return true; 567 } 568 569 static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = { 570 .preenable = &mxs_lradc_adc_buffer_preenable, 571 .postenable = &iio_triggered_buffer_postenable, 572 .predisable = &iio_triggered_buffer_predisable, 573 .postdisable = &mxs_lradc_adc_buffer_postdisable, 574 .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask, 575 }; 576 577 /* Driver initialization */ 578 #define MXS_ADC_CHAN(idx, chan_type, name) { \ 579 .type = (chan_type), \ 580 .indexed = 1, \ 581 .scan_index = (idx), \ 582 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 583 BIT(IIO_CHAN_INFO_SCALE), \ 584 .channel = (idx), \ 585 .address = (idx), \ 586 .scan_type = { \ 587 .sign = 'u', \ 588 .realbits = LRADC_RESOLUTION, \ 589 .storagebits = 32, \ 590 }, \ 591 .datasheet_name = (name), \ 592 } 593 594 static const struct iio_chan_spec mx23_lradc_chan_spec[] = { 595 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"), 596 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"), 597 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"), 598 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"), 599 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"), 600 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"), 601 MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"), 602 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"), 603 /* Combined Temperature sensors */ 604 { 605 .type = IIO_TEMP, 606 .indexed = 1, 607 .scan_index = 8, 608 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 609 BIT(IIO_CHAN_INFO_OFFSET) | 610 BIT(IIO_CHAN_INFO_SCALE), 611 .channel = 8, 612 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,}, 613 .datasheet_name = "TEMP_DIE", 614 }, 615 /* Hidden channel to keep indexes */ 616 { 617 .type = IIO_TEMP, 618 .indexed = 1, 619 .scan_index = -1, 620 .channel = 9, 621 }, 622 MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL), 623 MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL), 624 MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"), 625 MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"), 626 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"), 627 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"), 628 }; 629 630 static const struct iio_chan_spec mx28_lradc_chan_spec[] = { 631 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"), 632 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"), 633 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"), 634 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"), 635 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"), 636 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"), 637 MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"), 638 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"), 639 /* Combined Temperature sensors */ 640 { 641 .type = IIO_TEMP, 642 .indexed = 1, 643 .scan_index = 8, 644 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 645 BIT(IIO_CHAN_INFO_OFFSET) | 646 BIT(IIO_CHAN_INFO_SCALE), 647 .channel = 8, 648 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,}, 649 .datasheet_name = "TEMP_DIE", 650 }, 651 /* Hidden channel to keep indexes */ 652 { 653 .type = IIO_TEMP, 654 .indexed = 1, 655 .scan_index = -1, 656 .channel = 9, 657 }, 658 MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"), 659 MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"), 660 MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"), 661 MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"), 662 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"), 663 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"), 664 }; 665 666 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc) 667 { 668 /* The ADC always uses DELAY CHANNEL 0. */ 669 const u32 adc_cfg = 670 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) | 671 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET); 672 673 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */ 674 writel(adc_cfg, adc->base + LRADC_DELAY(0)); 675 676 /* 677 * Start internal temperature sensing by clearing bit 678 * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared 679 * after power up. 680 */ 681 writel(0, adc->base + LRADC_CTRL2); 682 } 683 684 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc) 685 { 686 writel(0, adc->base + LRADC_DELAY(0)); 687 } 688 689 static int mxs_lradc_adc_probe(struct platform_device *pdev) 690 { 691 struct device *dev = &pdev->dev; 692 struct mxs_lradc *lradc = dev_get_drvdata(dev->parent); 693 struct mxs_lradc_adc *adc; 694 struct iio_dev *iio; 695 struct resource *iores; 696 int ret, irq, virq, i, s, n; 697 u64 scale_uv; 698 const char **irq_name; 699 700 /* Allocate the IIO device. */ 701 iio = devm_iio_device_alloc(dev, sizeof(*adc)); 702 if (!iio) { 703 dev_err(dev, "Failed to allocate IIO device\n"); 704 return -ENOMEM; 705 } 706 707 adc = iio_priv(iio); 708 adc->lradc = lradc; 709 adc->dev = dev; 710 711 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 712 if (!iores) 713 return -EINVAL; 714 715 adc->base = devm_ioremap(dev, iores->start, resource_size(iores)); 716 if (!adc->base) 717 return -ENOMEM; 718 719 init_completion(&adc->completion); 720 spin_lock_init(&adc->lock); 721 722 platform_set_drvdata(pdev, iio); 723 724 iio->name = pdev->name; 725 iio->dev.parent = dev; 726 iio->dev.of_node = dev->parent->of_node; 727 iio->info = &mxs_lradc_adc_iio_info; 728 iio->modes = INDIO_DIRECT_MODE; 729 iio->masklength = LRADC_MAX_TOTAL_CHANS; 730 731 if (lradc->soc == IMX23_LRADC) { 732 iio->channels = mx23_lradc_chan_spec; 733 iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec); 734 irq_name = mx23_lradc_adc_irq_names; 735 n = ARRAY_SIZE(mx23_lradc_adc_irq_names); 736 } else { 737 iio->channels = mx28_lradc_chan_spec; 738 iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec); 739 irq_name = mx28_lradc_adc_irq_names; 740 n = ARRAY_SIZE(mx28_lradc_adc_irq_names); 741 } 742 743 ret = stmp_reset_block(adc->base); 744 if (ret) 745 return ret; 746 747 for (i = 0; i < n; i++) { 748 irq = platform_get_irq_byname(pdev, irq_name[i]); 749 if (irq < 0) 750 return irq; 751 752 virq = irq_of_parse_and_map(dev->parent->of_node, irq); 753 754 ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq, 755 0, irq_name[i], iio); 756 if (ret) 757 return ret; 758 } 759 760 ret = mxs_lradc_adc_trigger_init(iio); 761 if (ret) 762 goto err_trig; 763 764 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time, 765 &mxs_lradc_adc_trigger_handler, 766 &mxs_lradc_adc_buffer_ops); 767 if (ret) 768 return ret; 769 770 adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc]; 771 772 /* Populate available ADC input ranges */ 773 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) { 774 for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) { 775 /* 776 * [s=0] = optional divider by two disabled (default) 777 * [s=1] = optional divider by two enabled 778 * 779 * The scale is calculated by doing: 780 * Vref >> (realbits - s) 781 * which multiplies by two on the second component 782 * of the array. 783 */ 784 scale_uv = ((u64)adc->vref_mv[i] * 100000000) >> 785 (LRADC_RESOLUTION - s); 786 adc->scale_avail[i][s].nano = 787 do_div(scale_uv, 100000000) * 10; 788 adc->scale_avail[i][s].integer = scale_uv; 789 } 790 } 791 792 /* Configure the hardware. */ 793 mxs_lradc_adc_hw_init(adc); 794 795 /* Register IIO device. */ 796 ret = iio_device_register(iio); 797 if (ret) { 798 dev_err(dev, "Failed to register IIO device\n"); 799 goto err_dev; 800 } 801 802 return 0; 803 804 err_dev: 805 mxs_lradc_adc_hw_stop(adc); 806 mxs_lradc_adc_trigger_remove(iio); 807 err_trig: 808 iio_triggered_buffer_cleanup(iio); 809 return ret; 810 } 811 812 static int mxs_lradc_adc_remove(struct platform_device *pdev) 813 { 814 struct iio_dev *iio = platform_get_drvdata(pdev); 815 struct mxs_lradc_adc *adc = iio_priv(iio); 816 817 iio_device_unregister(iio); 818 mxs_lradc_adc_hw_stop(adc); 819 mxs_lradc_adc_trigger_remove(iio); 820 iio_triggered_buffer_cleanup(iio); 821 822 return 0; 823 } 824 825 static struct platform_driver mxs_lradc_adc_driver = { 826 .driver = { 827 .name = "mxs-lradc-adc", 828 }, 829 .probe = mxs_lradc_adc_probe, 830 .remove = mxs_lradc_adc_remove, 831 }; 832 module_platform_driver(mxs_lradc_adc_driver); 833 834 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 835 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver"); 836 MODULE_LICENSE("GPL"); 837 MODULE_ALIAS("platform:mxs-lradc-adc"); 838