1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 MediaTek Inc. 4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/platform_device.h> 14 #include <linux/property.h> 15 #include <linux/iopoll.h> 16 #include <linux/io.h> 17 #include <linux/iio/iio.h> 18 19 /* Register definitions */ 20 #define MT6577_AUXADC_CON0 0x00 21 #define MT6577_AUXADC_CON1 0x04 22 #define MT6577_AUXADC_CON2 0x10 23 #define MT6577_AUXADC_STA BIT(0) 24 25 #define MT6577_AUXADC_DAT0 0x14 26 #define MT6577_AUXADC_RDY0 BIT(12) 27 28 #define MT6577_AUXADC_MISC 0x94 29 #define MT6577_AUXADC_PDN_EN BIT(14) 30 31 #define MT6577_AUXADC_DAT_MASK 0xfff 32 #define MT6577_AUXADC_SLEEP_US 1000 33 #define MT6577_AUXADC_TIMEOUT_US 10000 34 #define MT6577_AUXADC_POWER_READY_MS 1 35 #define MT6577_AUXADC_SAMPLE_READY_US 25 36 37 struct mtk_auxadc_compatible { 38 bool sample_data_cali; 39 bool check_global_idle; 40 }; 41 42 struct mt6577_auxadc_device { 43 void __iomem *reg_base; 44 struct clk *adc_clk; 45 struct mutex lock; 46 const struct mtk_auxadc_compatible *dev_comp; 47 }; 48 49 static const struct mtk_auxadc_compatible mt8173_compat = { 50 .sample_data_cali = false, 51 .check_global_idle = true, 52 }; 53 54 static const struct mtk_auxadc_compatible mt6765_compat = { 55 .sample_data_cali = true, 56 .check_global_idle = false, 57 }; 58 59 #define MT6577_AUXADC_CHANNEL(idx) { \ 60 .type = IIO_VOLTAGE, \ 61 .indexed = 1, \ 62 .channel = (idx), \ 63 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 64 } 65 66 static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = { 67 MT6577_AUXADC_CHANNEL(0), 68 MT6577_AUXADC_CHANNEL(1), 69 MT6577_AUXADC_CHANNEL(2), 70 MT6577_AUXADC_CHANNEL(3), 71 MT6577_AUXADC_CHANNEL(4), 72 MT6577_AUXADC_CHANNEL(5), 73 MT6577_AUXADC_CHANNEL(6), 74 MT6577_AUXADC_CHANNEL(7), 75 MT6577_AUXADC_CHANNEL(8), 76 MT6577_AUXADC_CHANNEL(9), 77 MT6577_AUXADC_CHANNEL(10), 78 MT6577_AUXADC_CHANNEL(11), 79 MT6577_AUXADC_CHANNEL(12), 80 MT6577_AUXADC_CHANNEL(13), 81 MT6577_AUXADC_CHANNEL(14), 82 MT6577_AUXADC_CHANNEL(15), 83 }; 84 85 /* For Voltage calculation */ 86 #define VOLTAGE_FULL_RANGE 1500 /* VA voltage */ 87 #define AUXADC_PRECISE 4096 /* 12 bits */ 88 89 static int mt_auxadc_get_cali_data(int rawdata, bool enable_cali) 90 { 91 return rawdata; 92 } 93 94 static inline void mt6577_auxadc_mod_reg(void __iomem *reg, 95 u32 or_mask, u32 and_mask) 96 { 97 u32 val; 98 99 val = readl(reg); 100 val |= or_mask; 101 val &= ~and_mask; 102 writel(val, reg); 103 } 104 105 static int mt6577_auxadc_read(struct iio_dev *indio_dev, 106 struct iio_chan_spec const *chan) 107 { 108 u32 val; 109 void __iomem *reg_channel; 110 int ret; 111 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 112 113 reg_channel = adc_dev->reg_base + MT6577_AUXADC_DAT0 + 114 chan->channel * 0x04; 115 116 mutex_lock(&adc_dev->lock); 117 118 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1, 119 0, 1 << chan->channel); 120 121 /* read channel and make sure old ready bit == 0 */ 122 ret = readl_poll_timeout(reg_channel, val, 123 ((val & MT6577_AUXADC_RDY0) == 0), 124 MT6577_AUXADC_SLEEP_US, 125 MT6577_AUXADC_TIMEOUT_US); 126 if (ret < 0) { 127 dev_err(indio_dev->dev.parent, 128 "wait for channel[%d] ready bit clear time out\n", 129 chan->channel); 130 goto err_timeout; 131 } 132 133 /* set bit to trigger sample */ 134 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1, 135 1 << chan->channel, 0); 136 137 /* we must delay here for hardware sample channel data */ 138 udelay(MT6577_AUXADC_SAMPLE_READY_US); 139 140 if (adc_dev->dev_comp->check_global_idle) { 141 /* check MTK_AUXADC_CON2 if auxadc is idle */ 142 ret = readl_poll_timeout(adc_dev->reg_base + MT6577_AUXADC_CON2, 143 val, ((val & MT6577_AUXADC_STA) == 0), 144 MT6577_AUXADC_SLEEP_US, 145 MT6577_AUXADC_TIMEOUT_US); 146 if (ret < 0) { 147 dev_err(indio_dev->dev.parent, 148 "wait for auxadc idle time out\n"); 149 goto err_timeout; 150 } 151 } 152 153 /* read channel and make sure ready bit == 1 */ 154 ret = readl_poll_timeout(reg_channel, val, 155 ((val & MT6577_AUXADC_RDY0) != 0), 156 MT6577_AUXADC_SLEEP_US, 157 MT6577_AUXADC_TIMEOUT_US); 158 if (ret < 0) { 159 dev_err(indio_dev->dev.parent, 160 "wait for channel[%d] data ready time out\n", 161 chan->channel); 162 goto err_timeout; 163 } 164 165 /* read data */ 166 val = readl(reg_channel) & MT6577_AUXADC_DAT_MASK; 167 168 mutex_unlock(&adc_dev->lock); 169 170 return val; 171 172 err_timeout: 173 174 mutex_unlock(&adc_dev->lock); 175 176 return -ETIMEDOUT; 177 } 178 179 static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev, 180 struct iio_chan_spec const *chan, 181 int *val, 182 int *val2, 183 long info) 184 { 185 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 186 187 switch (info) { 188 case IIO_CHAN_INFO_PROCESSED: 189 *val = mt6577_auxadc_read(indio_dev, chan); 190 if (*val < 0) { 191 dev_err(indio_dev->dev.parent, 192 "failed to sample data on channel[%d]\n", 193 chan->channel); 194 return *val; 195 } 196 if (adc_dev->dev_comp->sample_data_cali) 197 *val = mt_auxadc_get_cali_data(*val, true); 198 199 /* Convert adc raw data to voltage: 0 - 1500 mV */ 200 *val = *val * VOLTAGE_FULL_RANGE / AUXADC_PRECISE; 201 202 return IIO_VAL_INT; 203 204 default: 205 return -EINVAL; 206 } 207 } 208 209 static const struct iio_info mt6577_auxadc_info = { 210 .read_raw = &mt6577_auxadc_read_raw, 211 }; 212 213 static int __maybe_unused mt6577_auxadc_resume(struct device *dev) 214 { 215 struct iio_dev *indio_dev = dev_get_drvdata(dev); 216 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 217 int ret; 218 219 ret = clk_prepare_enable(adc_dev->adc_clk); 220 if (ret) { 221 pr_err("failed to enable auxadc clock\n"); 222 return ret; 223 } 224 225 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 226 MT6577_AUXADC_PDN_EN, 0); 227 mdelay(MT6577_AUXADC_POWER_READY_MS); 228 229 return 0; 230 } 231 232 static int __maybe_unused mt6577_auxadc_suspend(struct device *dev) 233 { 234 struct iio_dev *indio_dev = dev_get_drvdata(dev); 235 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 236 237 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 238 0, MT6577_AUXADC_PDN_EN); 239 clk_disable_unprepare(adc_dev->adc_clk); 240 241 return 0; 242 } 243 244 static int mt6577_auxadc_probe(struct platform_device *pdev) 245 { 246 struct mt6577_auxadc_device *adc_dev; 247 unsigned long adc_clk_rate; 248 struct iio_dev *indio_dev; 249 int ret; 250 251 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); 252 if (!indio_dev) 253 return -ENOMEM; 254 255 adc_dev = iio_priv(indio_dev); 256 indio_dev->name = dev_name(&pdev->dev); 257 indio_dev->info = &mt6577_auxadc_info; 258 indio_dev->modes = INDIO_DIRECT_MODE; 259 indio_dev->channels = mt6577_auxadc_iio_channels; 260 indio_dev->num_channels = ARRAY_SIZE(mt6577_auxadc_iio_channels); 261 262 adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0); 263 if (IS_ERR(adc_dev->reg_base)) { 264 dev_err(&pdev->dev, "failed to get auxadc base address\n"); 265 return PTR_ERR(adc_dev->reg_base); 266 } 267 268 adc_dev->adc_clk = devm_clk_get(&pdev->dev, "main"); 269 if (IS_ERR(adc_dev->adc_clk)) { 270 dev_err(&pdev->dev, "failed to get auxadc clock\n"); 271 return PTR_ERR(adc_dev->adc_clk); 272 } 273 274 ret = clk_prepare_enable(adc_dev->adc_clk); 275 if (ret) { 276 dev_err(&pdev->dev, "failed to enable auxadc clock\n"); 277 return ret; 278 } 279 280 adc_clk_rate = clk_get_rate(adc_dev->adc_clk); 281 if (!adc_clk_rate) { 282 ret = -EINVAL; 283 dev_err(&pdev->dev, "null clock rate\n"); 284 goto err_disable_clk; 285 } 286 287 adc_dev->dev_comp = device_get_match_data(&pdev->dev); 288 289 mutex_init(&adc_dev->lock); 290 291 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 292 MT6577_AUXADC_PDN_EN, 0); 293 mdelay(MT6577_AUXADC_POWER_READY_MS); 294 295 platform_set_drvdata(pdev, indio_dev); 296 297 ret = iio_device_register(indio_dev); 298 if (ret < 0) { 299 dev_err(&pdev->dev, "failed to register iio device\n"); 300 goto err_power_off; 301 } 302 303 return 0; 304 305 err_power_off: 306 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 307 0, MT6577_AUXADC_PDN_EN); 308 err_disable_clk: 309 clk_disable_unprepare(adc_dev->adc_clk); 310 return ret; 311 } 312 313 static int mt6577_auxadc_remove(struct platform_device *pdev) 314 { 315 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 316 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 317 318 iio_device_unregister(indio_dev); 319 320 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 321 0, MT6577_AUXADC_PDN_EN); 322 323 clk_disable_unprepare(adc_dev->adc_clk); 324 325 return 0; 326 } 327 328 static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops, 329 mt6577_auxadc_suspend, 330 mt6577_auxadc_resume); 331 332 static const struct of_device_id mt6577_auxadc_of_match[] = { 333 { .compatible = "mediatek,mt2701-auxadc", .data = &mt8173_compat}, 334 { .compatible = "mediatek,mt2712-auxadc", .data = &mt8173_compat}, 335 { .compatible = "mediatek,mt7622-auxadc", .data = &mt8173_compat}, 336 { .compatible = "mediatek,mt8173-auxadc", .data = &mt8173_compat}, 337 { .compatible = "mediatek,mt6765-auxadc", .data = &mt6765_compat}, 338 { } 339 }; 340 MODULE_DEVICE_TABLE(of, mt6577_auxadc_of_match); 341 342 static struct platform_driver mt6577_auxadc_driver = { 343 .driver = { 344 .name = "mt6577-auxadc", 345 .of_match_table = mt6577_auxadc_of_match, 346 .pm = &mt6577_auxadc_pm_ops, 347 }, 348 .probe = mt6577_auxadc_probe, 349 .remove = mt6577_auxadc_remove, 350 }; 351 module_platform_driver(mt6577_auxadc_driver); 352 353 MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>"); 354 MODULE_DESCRIPTION("MTK AUXADC Device Driver"); 355 MODULE_LICENSE("GPL v2"); 356