1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 MediaTek Inc. 4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/platform_device.h> 14 #include <linux/property.h> 15 #include <linux/iopoll.h> 16 #include <linux/io.h> 17 #include <linux/iio/iio.h> 18 19 /* Register definitions */ 20 #define MT6577_AUXADC_CON0 0x00 21 #define MT6577_AUXADC_CON1 0x04 22 #define MT6577_AUXADC_CON2 0x10 23 #define MT6577_AUXADC_STA BIT(0) 24 25 #define MT6577_AUXADC_DAT0 0x14 26 #define MT6577_AUXADC_RDY0 BIT(12) 27 28 #define MT6577_AUXADC_MISC 0x94 29 #define MT6577_AUXADC_PDN_EN BIT(14) 30 31 #define MT6577_AUXADC_DAT_MASK 0xfff 32 #define MT6577_AUXADC_SLEEP_US 1000 33 #define MT6577_AUXADC_TIMEOUT_US 10000 34 #define MT6577_AUXADC_POWER_READY_MS 1 35 #define MT6577_AUXADC_SAMPLE_READY_US 25 36 37 struct mtk_auxadc_compatible { 38 bool sample_data_cali; 39 bool check_global_idle; 40 }; 41 42 struct mt6577_auxadc_device { 43 void __iomem *reg_base; 44 struct clk *adc_clk; 45 struct mutex lock; 46 const struct mtk_auxadc_compatible *dev_comp; 47 }; 48 49 static const struct mtk_auxadc_compatible mt8173_compat = { 50 .sample_data_cali = false, 51 .check_global_idle = true, 52 }; 53 54 static const struct mtk_auxadc_compatible mt6765_compat = { 55 .sample_data_cali = true, 56 .check_global_idle = false, 57 }; 58 59 #define MT6577_AUXADC_CHANNEL(idx) { \ 60 .type = IIO_VOLTAGE, \ 61 .indexed = 1, \ 62 .channel = (idx), \ 63 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 64 } 65 66 static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = { 67 MT6577_AUXADC_CHANNEL(0), 68 MT6577_AUXADC_CHANNEL(1), 69 MT6577_AUXADC_CHANNEL(2), 70 MT6577_AUXADC_CHANNEL(3), 71 MT6577_AUXADC_CHANNEL(4), 72 MT6577_AUXADC_CHANNEL(5), 73 MT6577_AUXADC_CHANNEL(6), 74 MT6577_AUXADC_CHANNEL(7), 75 MT6577_AUXADC_CHANNEL(8), 76 MT6577_AUXADC_CHANNEL(9), 77 MT6577_AUXADC_CHANNEL(10), 78 MT6577_AUXADC_CHANNEL(11), 79 MT6577_AUXADC_CHANNEL(12), 80 MT6577_AUXADC_CHANNEL(13), 81 MT6577_AUXADC_CHANNEL(14), 82 MT6577_AUXADC_CHANNEL(15), 83 }; 84 85 static int mt_auxadc_get_cali_data(int rawdata, bool enable_cali) 86 { 87 return rawdata; 88 } 89 90 static inline void mt6577_auxadc_mod_reg(void __iomem *reg, 91 u32 or_mask, u32 and_mask) 92 { 93 u32 val; 94 95 val = readl(reg); 96 val |= or_mask; 97 val &= ~and_mask; 98 writel(val, reg); 99 } 100 101 static int mt6577_auxadc_read(struct iio_dev *indio_dev, 102 struct iio_chan_spec const *chan) 103 { 104 u32 val; 105 void __iomem *reg_channel; 106 int ret; 107 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 108 109 reg_channel = adc_dev->reg_base + MT6577_AUXADC_DAT0 + 110 chan->channel * 0x04; 111 112 mutex_lock(&adc_dev->lock); 113 114 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1, 115 0, 1 << chan->channel); 116 117 /* read channel and make sure old ready bit == 0 */ 118 ret = readl_poll_timeout(reg_channel, val, 119 ((val & MT6577_AUXADC_RDY0) == 0), 120 MT6577_AUXADC_SLEEP_US, 121 MT6577_AUXADC_TIMEOUT_US); 122 if (ret < 0) { 123 dev_err(indio_dev->dev.parent, 124 "wait for channel[%d] ready bit clear time out\n", 125 chan->channel); 126 goto err_timeout; 127 } 128 129 /* set bit to trigger sample */ 130 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1, 131 1 << chan->channel, 0); 132 133 /* we must delay here for hardware sample channel data */ 134 udelay(MT6577_AUXADC_SAMPLE_READY_US); 135 136 if (adc_dev->dev_comp->check_global_idle) { 137 /* check MTK_AUXADC_CON2 if auxadc is idle */ 138 ret = readl_poll_timeout(adc_dev->reg_base + MT6577_AUXADC_CON2, 139 val, ((val & MT6577_AUXADC_STA) == 0), 140 MT6577_AUXADC_SLEEP_US, 141 MT6577_AUXADC_TIMEOUT_US); 142 if (ret < 0) { 143 dev_err(indio_dev->dev.parent, 144 "wait for auxadc idle time out\n"); 145 goto err_timeout; 146 } 147 } 148 149 /* read channel and make sure ready bit == 1 */ 150 ret = readl_poll_timeout(reg_channel, val, 151 ((val & MT6577_AUXADC_RDY0) != 0), 152 MT6577_AUXADC_SLEEP_US, 153 MT6577_AUXADC_TIMEOUT_US); 154 if (ret < 0) { 155 dev_err(indio_dev->dev.parent, 156 "wait for channel[%d] data ready time out\n", 157 chan->channel); 158 goto err_timeout; 159 } 160 161 /* read data */ 162 val = readl(reg_channel) & MT6577_AUXADC_DAT_MASK; 163 164 mutex_unlock(&adc_dev->lock); 165 166 return val; 167 168 err_timeout: 169 170 mutex_unlock(&adc_dev->lock); 171 172 return -ETIMEDOUT; 173 } 174 175 static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev, 176 struct iio_chan_spec const *chan, 177 int *val, 178 int *val2, 179 long info) 180 { 181 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 182 183 switch (info) { 184 case IIO_CHAN_INFO_PROCESSED: 185 *val = mt6577_auxadc_read(indio_dev, chan); 186 if (*val < 0) { 187 dev_err(indio_dev->dev.parent, 188 "failed to sample data on channel[%d]\n", 189 chan->channel); 190 return *val; 191 } 192 if (adc_dev->dev_comp->sample_data_cali) 193 *val = mt_auxadc_get_cali_data(*val, true); 194 return IIO_VAL_INT; 195 196 default: 197 return -EINVAL; 198 } 199 } 200 201 static const struct iio_info mt6577_auxadc_info = { 202 .read_raw = &mt6577_auxadc_read_raw, 203 }; 204 205 static int __maybe_unused mt6577_auxadc_resume(struct device *dev) 206 { 207 struct iio_dev *indio_dev = dev_get_drvdata(dev); 208 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 209 int ret; 210 211 ret = clk_prepare_enable(adc_dev->adc_clk); 212 if (ret) { 213 pr_err("failed to enable auxadc clock\n"); 214 return ret; 215 } 216 217 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 218 MT6577_AUXADC_PDN_EN, 0); 219 mdelay(MT6577_AUXADC_POWER_READY_MS); 220 221 return 0; 222 } 223 224 static int __maybe_unused mt6577_auxadc_suspend(struct device *dev) 225 { 226 struct iio_dev *indio_dev = dev_get_drvdata(dev); 227 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 228 229 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 230 0, MT6577_AUXADC_PDN_EN); 231 clk_disable_unprepare(adc_dev->adc_clk); 232 233 return 0; 234 } 235 236 static int mt6577_auxadc_probe(struct platform_device *pdev) 237 { 238 struct mt6577_auxadc_device *adc_dev; 239 unsigned long adc_clk_rate; 240 struct iio_dev *indio_dev; 241 int ret; 242 243 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); 244 if (!indio_dev) 245 return -ENOMEM; 246 247 adc_dev = iio_priv(indio_dev); 248 indio_dev->name = dev_name(&pdev->dev); 249 indio_dev->info = &mt6577_auxadc_info; 250 indio_dev->modes = INDIO_DIRECT_MODE; 251 indio_dev->channels = mt6577_auxadc_iio_channels; 252 indio_dev->num_channels = ARRAY_SIZE(mt6577_auxadc_iio_channels); 253 254 adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0); 255 if (IS_ERR(adc_dev->reg_base)) { 256 dev_err(&pdev->dev, "failed to get auxadc base address\n"); 257 return PTR_ERR(adc_dev->reg_base); 258 } 259 260 adc_dev->adc_clk = devm_clk_get(&pdev->dev, "main"); 261 if (IS_ERR(adc_dev->adc_clk)) { 262 dev_err(&pdev->dev, "failed to get auxadc clock\n"); 263 return PTR_ERR(adc_dev->adc_clk); 264 } 265 266 ret = clk_prepare_enable(adc_dev->adc_clk); 267 if (ret) { 268 dev_err(&pdev->dev, "failed to enable auxadc clock\n"); 269 return ret; 270 } 271 272 adc_clk_rate = clk_get_rate(adc_dev->adc_clk); 273 if (!adc_clk_rate) { 274 ret = -EINVAL; 275 dev_err(&pdev->dev, "null clock rate\n"); 276 goto err_disable_clk; 277 } 278 279 adc_dev->dev_comp = device_get_match_data(&pdev->dev); 280 281 mutex_init(&adc_dev->lock); 282 283 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 284 MT6577_AUXADC_PDN_EN, 0); 285 mdelay(MT6577_AUXADC_POWER_READY_MS); 286 287 platform_set_drvdata(pdev, indio_dev); 288 289 ret = iio_device_register(indio_dev); 290 if (ret < 0) { 291 dev_err(&pdev->dev, "failed to register iio device\n"); 292 goto err_power_off; 293 } 294 295 return 0; 296 297 err_power_off: 298 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 299 0, MT6577_AUXADC_PDN_EN); 300 err_disable_clk: 301 clk_disable_unprepare(adc_dev->adc_clk); 302 return ret; 303 } 304 305 static int mt6577_auxadc_remove(struct platform_device *pdev) 306 { 307 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 308 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); 309 310 iio_device_unregister(indio_dev); 311 312 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 313 0, MT6577_AUXADC_PDN_EN); 314 315 clk_disable_unprepare(adc_dev->adc_clk); 316 317 return 0; 318 } 319 320 static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops, 321 mt6577_auxadc_suspend, 322 mt6577_auxadc_resume); 323 324 static const struct of_device_id mt6577_auxadc_of_match[] = { 325 { .compatible = "mediatek,mt2701-auxadc", .data = &mt8173_compat}, 326 { .compatible = "mediatek,mt2712-auxadc", .data = &mt8173_compat}, 327 { .compatible = "mediatek,mt7622-auxadc", .data = &mt8173_compat}, 328 { .compatible = "mediatek,mt8173-auxadc", .data = &mt8173_compat}, 329 { .compatible = "mediatek,mt6765-auxadc", .data = &mt6765_compat}, 330 { } 331 }; 332 MODULE_DEVICE_TABLE(of, mt6577_auxadc_of_match); 333 334 static struct platform_driver mt6577_auxadc_driver = { 335 .driver = { 336 .name = "mt6577-auxadc", 337 .of_match_table = mt6577_auxadc_of_match, 338 .pm = &mt6577_auxadc_pm_ops, 339 }, 340 .probe = mt6577_auxadc_probe, 341 .remove = mt6577_auxadc_remove, 342 }; 343 module_platform_driver(mt6577_auxadc_driver); 344 345 MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>"); 346 MODULE_DESCRIPTION("MTK AUXADC Device Driver"); 347 MODULE_LICENSE("GPL v2"); 348