1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/bits.h> 4 #include <linux/delay.h> 5 #include <linux/irq.h> 6 #include <linux/kernel.h> 7 #include <linux/ktime.h> 8 #include <linux/module.h> 9 #include <linux/mutex.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/unaligned/be_byteshift.h> 13 14 #include <linux/iio/buffer.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/trigger_consumer.h> 17 #include <linux/iio/triggered_buffer.h> 18 19 #define MT6360_REG_PMUCHGCTRL3 0x313 20 #define MT6360_REG_PMUADCCFG 0x356 21 #define MT6360_REG_PMUADCIDLET 0x358 22 #define MT6360_REG_PMUADCRPT1 0x35A 23 24 /* PMUCHGCTRL3 0x313 */ 25 #define MT6360_AICR_MASK GENMASK(7, 2) 26 #define MT6360_AICR_SHFT 2 27 #define MT6360_AICR_400MA 0x6 28 /* PMUADCCFG 0x356 */ 29 #define MT6360_ADCEN_MASK BIT(15) 30 /* PMUADCRPT1 0x35A */ 31 #define MT6360_PREFERCH_MASK GENMASK(7, 4) 32 #define MT6360_PREFERCH_SHFT 4 33 #define MT6360_RPTCH_MASK GENMASK(3, 0) 34 #define MT6360_NO_PREFER 15 35 36 /* Time in ms */ 37 #define ADC_WAIT_TIME_MS 25 38 #define ADC_CONV_TIMEOUT_MS 100 39 #define ADC_LOOP_TIME_US 2000 40 41 enum { 42 MT6360_CHAN_USBID = 0, 43 MT6360_CHAN_VBUSDIV5, 44 MT6360_CHAN_VBUSDIV2, 45 MT6360_CHAN_VSYS, 46 MT6360_CHAN_VBAT, 47 MT6360_CHAN_IBUS, 48 MT6360_CHAN_IBAT, 49 MT6360_CHAN_CHG_VDDP, 50 MT6360_CHAN_TEMP_JC, 51 MT6360_CHAN_VREF_TS, 52 MT6360_CHAN_TS, 53 MT6360_CHAN_MAX 54 }; 55 56 struct mt6360_adc_data { 57 struct device *dev; 58 struct regmap *regmap; 59 /* Due to only one set of ADC control, this lock is used to prevent the race condition */ 60 struct mutex adc_lock; 61 ktime_t last_off_timestamps[MT6360_CHAN_MAX]; 62 }; 63 64 static int mt6360_adc_read_channel(struct mt6360_adc_data *mad, int channel, int *val) 65 { 66 __be16 adc_enable; 67 u8 rpt[3]; 68 ktime_t predict_end_t, timeout; 69 unsigned int pre_wait_time; 70 int ret; 71 72 mutex_lock(&mad->adc_lock); 73 74 /* Select the preferred ADC channel */ 75 ret = regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK, 76 channel << MT6360_PREFERCH_SHFT); 77 if (ret) 78 goto out_adc_lock; 79 80 adc_enable = cpu_to_be16(MT6360_ADCEN_MASK | BIT(channel)); 81 ret = regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable)); 82 if (ret) 83 goto out_adc_lock; 84 85 predict_end_t = ktime_add_ms(mad->last_off_timestamps[channel], 2 * ADC_WAIT_TIME_MS); 86 87 if (ktime_after(ktime_get(), predict_end_t)) 88 pre_wait_time = ADC_WAIT_TIME_MS; 89 else 90 pre_wait_time = 3 * ADC_WAIT_TIME_MS; 91 92 if (msleep_interruptible(pre_wait_time)) { 93 ret = -ERESTARTSYS; 94 goto out_adc_conv; 95 } 96 97 timeout = ktime_add_ms(ktime_get(), ADC_CONV_TIMEOUT_MS); 98 while (true) { 99 ret = regmap_raw_read(mad->regmap, MT6360_REG_PMUADCRPT1, rpt, sizeof(rpt)); 100 if (ret) 101 goto out_adc_conv; 102 103 /* 104 * There are two functions, ZCV and TypeC OTP, running ADC VBAT and TS in 105 * background, and ADC samples are taken on a fixed frequency no matter read the 106 * previous one or not. 107 * To avoid conflict, We set minimum time threshold after enable ADC and 108 * check report channel is the same. 109 * The worst case is run the same ADC twice and background function is also running, 110 * ADC conversion sequence is desire channel before start ADC, background ADC, 111 * desire channel after start ADC. 112 * So the minimum correct data is three times of typical conversion time. 113 */ 114 if ((rpt[0] & MT6360_RPTCH_MASK) == channel) 115 break; 116 117 if (ktime_compare(ktime_get(), timeout) > 0) { 118 ret = -ETIMEDOUT; 119 goto out_adc_conv; 120 } 121 122 usleep_range(ADC_LOOP_TIME_US / 2, ADC_LOOP_TIME_US); 123 } 124 125 *val = rpt[1] << 8 | rpt[2]; 126 ret = IIO_VAL_INT; 127 128 out_adc_conv: 129 /* Only keep ADC enable */ 130 adc_enable = cpu_to_be16(MT6360_ADCEN_MASK); 131 regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable)); 132 mad->last_off_timestamps[channel] = ktime_get(); 133 /* Config prefer channel to NO_PREFER */ 134 regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK, 135 MT6360_NO_PREFER << MT6360_PREFERCH_SHFT); 136 out_adc_lock: 137 mutex_unlock(&mad->adc_lock); 138 139 return ret; 140 } 141 142 static int mt6360_adc_read_scale(struct mt6360_adc_data *mad, int channel, int *val, int *val2) 143 { 144 unsigned int regval; 145 int ret; 146 147 switch (channel) { 148 case MT6360_CHAN_USBID: 149 case MT6360_CHAN_VSYS: 150 case MT6360_CHAN_VBAT: 151 case MT6360_CHAN_CHG_VDDP: 152 case MT6360_CHAN_VREF_TS: 153 case MT6360_CHAN_TS: 154 *val = 1250; 155 return IIO_VAL_INT; 156 case MT6360_CHAN_VBUSDIV5: 157 *val = 6250; 158 return IIO_VAL_INT; 159 case MT6360_CHAN_VBUSDIV2: 160 case MT6360_CHAN_IBUS: 161 case MT6360_CHAN_IBAT: 162 *val = 2500; 163 164 if (channel == MT6360_CHAN_IBUS) { 165 /* IBUS will be affected by input current limit for the different Ron */ 166 /* Check whether the config is <400mA or not */ 167 ret = regmap_read(mad->regmap, MT6360_REG_PMUCHGCTRL3, ®val); 168 if (ret) 169 return ret; 170 171 regval = (regval & MT6360_AICR_MASK) >> MT6360_AICR_SHFT; 172 if (regval < MT6360_AICR_400MA) 173 *val = 1900; 174 } 175 176 return IIO_VAL_INT; 177 case MT6360_CHAN_TEMP_JC: 178 *val = 105; 179 *val2 = 100; 180 return IIO_VAL_FRACTIONAL; 181 } 182 183 return -EINVAL; 184 } 185 186 static int mt6360_adc_read_offset(struct mt6360_adc_data *mad, int channel, int *val) 187 { 188 *val = (channel == MT6360_CHAN_TEMP_JC) ? -80 : 0; 189 return IIO_VAL_INT; 190 } 191 192 static int mt6360_adc_read_raw(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, 193 int *val, int *val2, long mask) 194 { 195 struct mt6360_adc_data *mad = iio_priv(iio_dev); 196 197 switch (mask) { 198 case IIO_CHAN_INFO_RAW: 199 return mt6360_adc_read_channel(mad, chan->channel, val); 200 case IIO_CHAN_INFO_SCALE: 201 return mt6360_adc_read_scale(mad, chan->channel, val, val2); 202 case IIO_CHAN_INFO_OFFSET: 203 return mt6360_adc_read_offset(mad, chan->channel, val); 204 } 205 206 return -EINVAL; 207 } 208 209 static const char *mt6360_channel_labels[MT6360_CHAN_MAX] = { 210 "usbid", "vbusdiv5", "vbusdiv2", "vsys", "vbat", "ibus", "ibat", "chg_vddp", 211 "temp_jc", "vref_ts", "ts", 212 }; 213 214 static int mt6360_adc_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, 215 char *label) 216 { 217 return snprintf(label, PAGE_SIZE, "%s\n", mt6360_channel_labels[chan->channel]); 218 } 219 220 static const struct iio_info mt6360_adc_iio_info = { 221 .read_raw = mt6360_adc_read_raw, 222 .read_label = mt6360_adc_read_label, 223 }; 224 225 #define MT6360_ADC_CHAN(_idx, _type) { \ 226 .type = _type, \ 227 .channel = MT6360_CHAN_##_idx, \ 228 .scan_index = MT6360_CHAN_##_idx, \ 229 .datasheet_name = #_idx, \ 230 .scan_type = { \ 231 .sign = 'u', \ 232 .realbits = 16, \ 233 .storagebits = 16, \ 234 .endianness = IIO_CPU, \ 235 }, \ 236 .indexed = 1, \ 237 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 238 BIT(IIO_CHAN_INFO_SCALE) | \ 239 BIT(IIO_CHAN_INFO_OFFSET), \ 240 } 241 242 static const struct iio_chan_spec mt6360_adc_channels[] = { 243 MT6360_ADC_CHAN(USBID, IIO_VOLTAGE), 244 MT6360_ADC_CHAN(VBUSDIV5, IIO_VOLTAGE), 245 MT6360_ADC_CHAN(VBUSDIV2, IIO_VOLTAGE), 246 MT6360_ADC_CHAN(VSYS, IIO_VOLTAGE), 247 MT6360_ADC_CHAN(VBAT, IIO_VOLTAGE), 248 MT6360_ADC_CHAN(IBUS, IIO_CURRENT), 249 MT6360_ADC_CHAN(IBAT, IIO_CURRENT), 250 MT6360_ADC_CHAN(CHG_VDDP, IIO_VOLTAGE), 251 MT6360_ADC_CHAN(TEMP_JC, IIO_TEMP), 252 MT6360_ADC_CHAN(VREF_TS, IIO_VOLTAGE), 253 MT6360_ADC_CHAN(TS, IIO_VOLTAGE), 254 IIO_CHAN_SOFT_TIMESTAMP(MT6360_CHAN_MAX), 255 }; 256 257 static irqreturn_t mt6360_adc_trigger_handler(int irq, void *p) 258 { 259 struct iio_poll_func *pf = p; 260 struct iio_dev *indio_dev = pf->indio_dev; 261 struct mt6360_adc_data *mad = iio_priv(indio_dev); 262 struct { 263 u16 values[MT6360_CHAN_MAX]; 264 int64_t timestamp; 265 } data __aligned(8); 266 int i = 0, bit, val, ret; 267 268 memset(&data, 0, sizeof(data)); 269 for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) { 270 ret = mt6360_adc_read_channel(mad, bit, &val); 271 if (ret < 0) { 272 dev_warn(&indio_dev->dev, "Failed to get channel %d conversion val\n", bit); 273 goto out; 274 } 275 276 data.values[i++] = val; 277 } 278 iio_push_to_buffers_with_timestamp(indio_dev, &data, iio_get_time_ns(indio_dev)); 279 out: 280 iio_trigger_notify_done(indio_dev->trig); 281 282 return IRQ_HANDLED; 283 } 284 285 static inline int mt6360_adc_reset(struct mt6360_adc_data *info) 286 { 287 __be16 adc_enable; 288 ktime_t all_off_time; 289 int i, ret; 290 291 /* Clear ADC idle wait time to 0 */ 292 ret = regmap_write(info->regmap, MT6360_REG_PMUADCIDLET, 0); 293 if (ret) 294 return ret; 295 296 /* Only keep ADC enable, but keep all channels off */ 297 adc_enable = cpu_to_be16(MT6360_ADCEN_MASK); 298 ret = regmap_raw_write(info->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable)); 299 if (ret) 300 return ret; 301 302 /* Reset all channel off time to the current one */ 303 all_off_time = ktime_get(); 304 for (i = 0; i < MT6360_CHAN_MAX; i++) 305 info->last_off_timestamps[i] = all_off_time; 306 307 return 0; 308 } 309 310 static int mt6360_adc_probe(struct platform_device *pdev) 311 { 312 struct mt6360_adc_data *mad; 313 struct regmap *regmap; 314 struct iio_dev *indio_dev; 315 int ret; 316 317 regmap = dev_get_regmap(pdev->dev.parent, NULL); 318 if (!regmap) { 319 dev_err(&pdev->dev, "Failed to get parent regmap\n"); 320 return -ENODEV; 321 } 322 323 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*mad)); 324 if (!indio_dev) 325 return -ENOMEM; 326 327 mad = iio_priv(indio_dev); 328 mad->dev = &pdev->dev; 329 mad->regmap = regmap; 330 mutex_init(&mad->adc_lock); 331 332 ret = mt6360_adc_reset(mad); 333 if (ret < 0) { 334 dev_err(&pdev->dev, "Failed to reset adc\n"); 335 return ret; 336 } 337 338 indio_dev->name = dev_name(&pdev->dev); 339 indio_dev->dev.parent = &pdev->dev; 340 indio_dev->info = &mt6360_adc_iio_info; 341 indio_dev->modes = INDIO_DIRECT_MODE; 342 indio_dev->channels = mt6360_adc_channels; 343 indio_dev->num_channels = ARRAY_SIZE(mt6360_adc_channels); 344 345 ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, NULL, 346 mt6360_adc_trigger_handler, NULL); 347 if (ret) { 348 dev_err(&pdev->dev, "Failed to allocate iio trigger buffer\n"); 349 return ret; 350 } 351 352 return devm_iio_device_register(&pdev->dev, indio_dev); 353 } 354 355 static const struct of_device_id __maybe_unused mt6360_adc_of_id[] = { 356 { .compatible = "mediatek,mt6360-adc", }, 357 {} 358 }; 359 MODULE_DEVICE_TABLE(of, mt6360_adc_of_id); 360 361 static struct platform_driver mt6360_adc_driver = { 362 .driver = { 363 .name = "mt6360-adc", 364 .of_match_table = mt6360_adc_of_id, 365 }, 366 .probe = mt6360_adc_probe, 367 }; 368 module_platform_driver(mt6360_adc_driver); 369 370 MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>"); 371 MODULE_DESCRIPTION("MT6360 ADC Driver"); 372 MODULE_LICENSE("GPL v2"); 373