1 /* 2 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter 3 * 4 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/delay.h> 18 #include <linux/io.h> 19 #include <linux/iio/iio.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 27 #define MESON_SAR_ADC_REG0 0x00 28 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31) 29 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28) 30 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30) 31 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29) 32 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28) 33 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27) 34 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26) 35 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21) 36 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19) 37 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16) 38 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15) 39 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14) 40 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12) 41 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10) 42 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9) 43 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4) 44 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3) 45 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2) 46 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1) 47 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0) 48 49 #define MESON_SAR_ADC_CHAN_LIST 0x04 50 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24) 51 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ 52 (GENMASK(2, 0) << ((_chan) * 3)) 53 54 #define MESON_SAR_ADC_AVG_CNTL 0x08 55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ 56 (16 + ((_chan) * 2)) 57 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ 58 (GENMASK(17, 16) << ((_chan) * 2)) 59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ 60 (0 + ((_chan) * 2)) 61 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ 62 (GENMASK(1, 0) << ((_chan) * 2)) 63 64 #define MESON_SAR_ADC_REG3 0x0c 65 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31) 66 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30) 67 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28) 68 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27) 69 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26) 70 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23) 71 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22) 72 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21) 73 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) 74 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) 75 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 76 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 77 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) 78 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) 79 80 #define MESON_SAR_ADC_DELAY 0x10 81 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24) 82 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15) 83 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14) 84 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16) 85 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8) 86 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0) 87 88 #define MESON_SAR_ADC_LAST_RD 0x14 89 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16) 90 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0) 91 92 #define MESON_SAR_ADC_FIFO_RD 0x18 93 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12) 94 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0) 95 96 #define MESON_SAR_ADC_AUX_SW 0x1c 97 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \ 98 (GENMASK(10, 8) << (((_chan) - 2) * 2)) 99 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6) 100 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5) 101 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4) 102 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3) 103 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2) 104 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1) 105 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0) 106 107 #define MESON_SAR_ADC_CHAN_10_SW 0x20 108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23) 109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22) 110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21) 111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20) 112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19) 113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18) 114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17) 115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16) 116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7) 117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6) 118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5) 119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4) 120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3) 121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2) 122 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1) 123 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0) 124 125 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24 126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26) 127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23) 128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22) 129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21) 130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20) 131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19) 132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18) 133 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17) 134 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16) 135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7) 136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6) 137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5) 138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4) 139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3) 140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2) 141 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1) 142 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0) 143 144 #define MESON_SAR_ADC_DELTA_10 0x28 145 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27) 146 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26) 147 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16) 148 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15) 149 #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11 150 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11) 151 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10) 152 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0) 153 154 /* 155 * NOTE: registers from here are undocumented (the vendor Linux kernel driver 156 * and u-boot source served as reference). These only seem to be relevant on 157 * GXBB and newer. 158 */ 159 #define MESON_SAR_ADC_REG11 0x2c 160 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) 161 162 #define MESON_SAR_ADC_REG13 0x34 163 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8) 164 165 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32 166 167 #define MESON_SAR_ADC_CHAN(_chan) { \ 168 .type = IIO_VOLTAGE, \ 169 .indexed = 1, \ 170 .channel = _chan, \ 171 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 172 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 173 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 174 .datasheet_name = "SAR_ADC_CH"#_chan, \ 175 } 176 177 /* 178 * TODO: the hardware supports IIO_TEMP for channel 6 as well which is 179 * currently not supported by this driver. 180 */ 181 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = { 182 MESON_SAR_ADC_CHAN(0), 183 MESON_SAR_ADC_CHAN(1), 184 MESON_SAR_ADC_CHAN(2), 185 MESON_SAR_ADC_CHAN(3), 186 MESON_SAR_ADC_CHAN(4), 187 MESON_SAR_ADC_CHAN(5), 188 MESON_SAR_ADC_CHAN(6), 189 MESON_SAR_ADC_CHAN(7), 190 IIO_CHAN_SOFT_TIMESTAMP(8), 191 }; 192 193 enum meson_sar_adc_avg_mode { 194 NO_AVERAGING = 0x0, 195 MEAN_AVERAGING = 0x1, 196 MEDIAN_AVERAGING = 0x2, 197 }; 198 199 enum meson_sar_adc_num_samples { 200 ONE_SAMPLE = 0x0, 201 TWO_SAMPLES = 0x1, 202 FOUR_SAMPLES = 0x2, 203 EIGHT_SAMPLES = 0x3, 204 }; 205 206 enum meson_sar_adc_chan7_mux_sel { 207 CHAN7_MUX_VSS = 0x0, 208 CHAN7_MUX_VDD_DIV4 = 0x1, 209 CHAN7_MUX_VDD_DIV2 = 0x2, 210 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3, 211 CHAN7_MUX_VDD = 0x4, 212 CHAN7_MUX_CH7_INPUT = 0x7, 213 }; 214 215 struct meson_sar_adc_data { 216 unsigned int resolution; 217 const char *name; 218 }; 219 220 struct meson_sar_adc_priv { 221 struct regmap *regmap; 222 struct regulator *vref; 223 const struct meson_sar_adc_data *data; 224 struct clk *clkin; 225 struct clk *core_clk; 226 struct clk *sana_clk; 227 struct clk *adc_sel_clk; 228 struct clk *adc_clk; 229 struct clk_gate clk_gate; 230 struct clk *adc_div_clk; 231 struct clk_divider clk_div; 232 }; 233 234 static const struct regmap_config meson_sar_adc_regmap_config = { 235 .reg_bits = 8, 236 .val_bits = 32, 237 .reg_stride = 4, 238 .max_register = MESON_SAR_ADC_REG13, 239 }; 240 241 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev) 242 { 243 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 244 u32 regval; 245 246 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 247 248 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); 249 } 250 251 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev) 252 { 253 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 254 int regval, timeout = 10000; 255 256 /* 257 * NOTE: we need a small delay before reading the status, otherwise 258 * the sample engine may not have started internally (which would 259 * seem to us that sampling is already finished). 260 */ 261 do { 262 udelay(1); 263 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 264 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); 265 266 if (timeout < 0) 267 return -ETIMEDOUT; 268 269 return 0; 270 } 271 272 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, 273 const struct iio_chan_spec *chan, 274 int *val) 275 { 276 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 277 int ret, regval, fifo_chan, fifo_val, sum = 0, count = 0; 278 279 ret = meson_sar_adc_wait_busy_clear(indio_dev); 280 if (ret) 281 return ret; 282 283 while (meson_sar_adc_get_fifo_count(indio_dev) > 0 && 284 count < MESON_SAR_ADC_MAX_FIFO_SIZE) { 285 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); 286 287 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, 288 regval); 289 if (fifo_chan != chan->channel) 290 continue; 291 292 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, 293 regval); 294 fifo_val &= (BIT(priv->data->resolution) - 1); 295 296 sum += fifo_val; 297 count++; 298 } 299 300 if (!count) 301 return -ENOENT; 302 303 *val = sum / count; 304 305 return 0; 306 } 307 308 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev, 309 const struct iio_chan_spec *chan, 310 enum meson_sar_adc_avg_mode mode, 311 enum meson_sar_adc_num_samples samples) 312 { 313 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 314 int val, channel = chan->channel; 315 316 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel); 317 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, 318 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel), 319 val); 320 321 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel); 322 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, 323 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val); 324 } 325 326 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev, 327 const struct iio_chan_spec *chan) 328 { 329 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 330 u32 regval; 331 332 /* 333 * the SAR ADC engine allows sampling multiple channels at the same 334 * time. to keep it simple we're only working with one *internal* 335 * channel, which starts counting at index 0 (which means: count = 1). 336 */ 337 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0); 338 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 339 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval); 340 341 /* map channel index 0 to the channel which we want to read */ 342 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), 343 chan->channel); 344 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 345 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval); 346 347 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, 348 chan->channel); 349 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, 350 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, 351 regval); 352 353 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, 354 chan->channel); 355 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, 356 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, 357 regval); 358 359 if (chan->channel == 6) 360 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 361 MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0); 362 } 363 364 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev, 365 enum meson_sar_adc_chan7_mux_sel sel) 366 { 367 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 368 u32 regval; 369 370 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); 371 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 372 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); 373 374 usleep_range(10, 20); 375 } 376 377 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev) 378 { 379 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 380 381 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 382 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 383 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE); 384 385 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 386 MESON_SAR_ADC_REG0_SAMPLING_START, 387 MESON_SAR_ADC_REG0_SAMPLING_START); 388 } 389 390 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev) 391 { 392 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 393 394 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 395 MESON_SAR_ADC_REG0_SAMPLING_STOP, 396 MESON_SAR_ADC_REG0_SAMPLING_STOP); 397 398 /* wait until all modules are stopped */ 399 meson_sar_adc_wait_busy_clear(indio_dev); 400 401 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 402 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0); 403 } 404 405 static int meson_sar_adc_lock(struct iio_dev *indio_dev) 406 { 407 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 408 int val, timeout = 10000; 409 410 mutex_lock(&indio_dev->mlock); 411 412 /* prevent BL30 from using the SAR ADC while we are using it */ 413 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 414 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 415 MESON_SAR_ADC_DELAY_KERNEL_BUSY); 416 417 /* wait until BL30 releases it's lock (so we can use the SAR ADC) */ 418 do { 419 udelay(1); 420 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); 421 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); 422 423 if (timeout < 0) 424 return -ETIMEDOUT; 425 426 return 0; 427 } 428 429 static void meson_sar_adc_unlock(struct iio_dev *indio_dev) 430 { 431 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 432 433 /* allow BL30 to use the SAR ADC again */ 434 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 435 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0); 436 437 mutex_unlock(&indio_dev->mlock); 438 } 439 440 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev) 441 { 442 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 443 int count; 444 445 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) { 446 if (!meson_sar_adc_get_fifo_count(indio_dev)) 447 break; 448 449 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0); 450 } 451 } 452 453 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, 454 const struct iio_chan_spec *chan, 455 enum meson_sar_adc_avg_mode avg_mode, 456 enum meson_sar_adc_num_samples avg_samples, 457 int *val) 458 { 459 int ret; 460 461 ret = meson_sar_adc_lock(indio_dev); 462 if (ret) 463 return ret; 464 465 /* clear the FIFO to make sure we're not reading old values */ 466 meson_sar_adc_clear_fifo(indio_dev); 467 468 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples); 469 470 meson_sar_adc_enable_channel(indio_dev, chan); 471 472 meson_sar_adc_start_sample_engine(indio_dev); 473 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val); 474 meson_sar_adc_stop_sample_engine(indio_dev); 475 476 meson_sar_adc_unlock(indio_dev); 477 478 if (ret) { 479 dev_warn(indio_dev->dev.parent, 480 "failed to read sample for channel %d: %d\n", 481 chan->channel, ret); 482 return ret; 483 } 484 485 return IIO_VAL_INT; 486 } 487 488 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, 489 const struct iio_chan_spec *chan, 490 int *val, int *val2, long mask) 491 { 492 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 493 int ret; 494 495 switch (mask) { 496 case IIO_CHAN_INFO_RAW: 497 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING, 498 ONE_SAMPLE, val); 499 break; 500 501 case IIO_CHAN_INFO_AVERAGE_RAW: 502 return meson_sar_adc_get_sample(indio_dev, chan, 503 MEAN_AVERAGING, EIGHT_SAMPLES, 504 val); 505 break; 506 507 case IIO_CHAN_INFO_SCALE: 508 ret = regulator_get_voltage(priv->vref); 509 if (ret < 0) { 510 dev_err(indio_dev->dev.parent, 511 "failed to get vref voltage: %d\n", ret); 512 return ret; 513 } 514 515 *val = ret / 1000; 516 *val2 = priv->data->resolution; 517 return IIO_VAL_FRACTIONAL_LOG2; 518 519 default: 520 return -EINVAL; 521 } 522 } 523 524 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, 525 void __iomem *base) 526 { 527 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 528 struct clk_init_data init; 529 const char *clk_parents[1]; 530 531 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div", 532 of_node_full_name(indio_dev->dev.of_node)); 533 init.flags = 0; 534 init.ops = &clk_divider_ops; 535 clk_parents[0] = __clk_get_name(priv->clkin); 536 init.parent_names = clk_parents; 537 init.num_parents = 1; 538 539 priv->clk_div.reg = base + MESON_SAR_ADC_REG3; 540 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT; 541 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH; 542 priv->clk_div.hw.init = &init; 543 priv->clk_div.flags = 0; 544 545 priv->adc_div_clk = devm_clk_register(&indio_dev->dev, 546 &priv->clk_div.hw); 547 if (WARN_ON(IS_ERR(priv->adc_div_clk))) 548 return PTR_ERR(priv->adc_div_clk); 549 550 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en", 551 of_node_full_name(indio_dev->dev.of_node)); 552 init.flags = CLK_SET_RATE_PARENT; 553 init.ops = &clk_gate_ops; 554 clk_parents[0] = __clk_get_name(priv->adc_div_clk); 555 init.parent_names = clk_parents; 556 init.num_parents = 1; 557 558 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; 559 priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN); 560 priv->clk_gate.hw.init = &init; 561 562 priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw); 563 if (WARN_ON(IS_ERR(priv->adc_clk))) 564 return PTR_ERR(priv->adc_clk); 565 566 return 0; 567 } 568 569 static int meson_sar_adc_init(struct iio_dev *indio_dev) 570 { 571 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 572 int regval, ret; 573 574 /* 575 * make sure we start at CH7 input since the other muxes are only used 576 * for internal calibration. 577 */ 578 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT); 579 580 /* 581 * leave sampling delay and the input clocks as configured by BL30 to 582 * make sure BL30 gets the values it expects when reading the 583 * temperature sensor. 584 */ 585 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); 586 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) 587 return 0; 588 589 meson_sar_adc_stop_sample_engine(indio_dev); 590 591 /* update the channel 6 MUX to select the temperature sensor */ 592 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 593 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 594 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL); 595 596 /* disable all channels by default */ 597 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); 598 599 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 600 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0); 601 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 602 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY, 603 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY); 604 605 /* delay between two samples = (10+1) * 1uS */ 606 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 607 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 608 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 609 10)); 610 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 611 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 612 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 613 0)); 614 615 /* delay between two samples = (10+1) * 1uS */ 616 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 617 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 618 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 619 10)); 620 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 621 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 622 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 623 1)); 624 625 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); 626 if (ret) { 627 dev_err(indio_dev->dev.parent, 628 "failed to set adc parent to clkin\n"); 629 return ret; 630 } 631 632 ret = clk_set_rate(priv->adc_clk, 1200000); 633 if (ret) { 634 dev_err(indio_dev->dev.parent, 635 "failed to set adc clock rate\n"); 636 return ret; 637 } 638 639 return 0; 640 } 641 642 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) 643 { 644 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 645 int ret; 646 647 ret = meson_sar_adc_lock(indio_dev); 648 if (ret) 649 goto err_lock; 650 651 ret = regulator_enable(priv->vref); 652 if (ret < 0) { 653 dev_err(indio_dev->dev.parent, 654 "failed to enable vref regulator\n"); 655 goto err_vref; 656 } 657 658 ret = clk_prepare_enable(priv->core_clk); 659 if (ret) { 660 dev_err(indio_dev->dev.parent, "failed to enable core clk\n"); 661 goto err_core_clk; 662 } 663 664 ret = clk_prepare_enable(priv->sana_clk); 665 if (ret) { 666 dev_err(indio_dev->dev.parent, "failed to enable sana clk\n"); 667 goto err_sana_clk; 668 } 669 670 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 671 MESON_SAR_ADC_REG11_BANDGAP_EN, 672 MESON_SAR_ADC_REG11_BANDGAP_EN); 673 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 674 MESON_SAR_ADC_REG3_ADC_EN, 675 MESON_SAR_ADC_REG3_ADC_EN); 676 677 udelay(5); 678 679 ret = clk_prepare_enable(priv->adc_clk); 680 if (ret) { 681 dev_err(indio_dev->dev.parent, "failed to enable adc clk\n"); 682 goto err_adc_clk; 683 } 684 685 meson_sar_adc_unlock(indio_dev); 686 687 return 0; 688 689 err_adc_clk: 690 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 691 MESON_SAR_ADC_REG3_ADC_EN, 0); 692 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 693 MESON_SAR_ADC_REG11_BANDGAP_EN, 0); 694 clk_disable_unprepare(priv->sana_clk); 695 err_sana_clk: 696 clk_disable_unprepare(priv->core_clk); 697 err_core_clk: 698 regulator_disable(priv->vref); 699 err_vref: 700 meson_sar_adc_unlock(indio_dev); 701 err_lock: 702 return ret; 703 } 704 705 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev) 706 { 707 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 708 int ret; 709 710 ret = meson_sar_adc_lock(indio_dev); 711 if (ret) 712 return ret; 713 714 clk_disable_unprepare(priv->adc_clk); 715 716 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 717 MESON_SAR_ADC_REG3_ADC_EN, 0); 718 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 719 MESON_SAR_ADC_REG11_BANDGAP_EN, 0); 720 721 clk_disable_unprepare(priv->sana_clk); 722 clk_disable_unprepare(priv->core_clk); 723 724 regulator_disable(priv->vref); 725 726 meson_sar_adc_unlock(indio_dev); 727 728 return 0; 729 } 730 731 static const struct iio_info meson_sar_adc_iio_info = { 732 .read_raw = meson_sar_adc_iio_info_read_raw, 733 .driver_module = THIS_MODULE, 734 }; 735 736 struct meson_sar_adc_data meson_sar_adc_gxbb_data = { 737 .resolution = 10, 738 .name = "meson-gxbb-saradc", 739 }; 740 741 struct meson_sar_adc_data meson_sar_adc_gxl_data = { 742 .resolution = 12, 743 .name = "meson-gxl-saradc", 744 }; 745 746 struct meson_sar_adc_data meson_sar_adc_gxm_data = { 747 .resolution = 12, 748 .name = "meson-gxm-saradc", 749 }; 750 751 static const struct of_device_id meson_sar_adc_of_match[] = { 752 { 753 .compatible = "amlogic,meson-gxbb-saradc", 754 .data = &meson_sar_adc_gxbb_data, 755 }, { 756 .compatible = "amlogic,meson-gxl-saradc", 757 .data = &meson_sar_adc_gxl_data, 758 }, { 759 .compatible = "amlogic,meson-gxm-saradc", 760 .data = &meson_sar_adc_gxm_data, 761 }, 762 {}, 763 }; 764 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match); 765 766 static int meson_sar_adc_probe(struct platform_device *pdev) 767 { 768 struct meson_sar_adc_priv *priv; 769 struct iio_dev *indio_dev; 770 struct resource *res; 771 void __iomem *base; 772 const struct of_device_id *match; 773 int ret; 774 775 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); 776 if (!indio_dev) { 777 dev_err(&pdev->dev, "failed allocating iio device\n"); 778 return -ENOMEM; 779 } 780 781 priv = iio_priv(indio_dev); 782 783 match = of_match_device(meson_sar_adc_of_match, &pdev->dev); 784 priv->data = match->data; 785 786 indio_dev->name = priv->data->name; 787 indio_dev->dev.parent = &pdev->dev; 788 indio_dev->dev.of_node = pdev->dev.of_node; 789 indio_dev->modes = INDIO_DIRECT_MODE; 790 indio_dev->info = &meson_sar_adc_iio_info; 791 792 indio_dev->channels = meson_sar_adc_iio_channels; 793 indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels); 794 795 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 796 base = devm_ioremap_resource(&pdev->dev, res); 797 if (IS_ERR(base)) 798 return PTR_ERR(base); 799 800 priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, 801 &meson_sar_adc_regmap_config); 802 if (IS_ERR(priv->regmap)) 803 return PTR_ERR(priv->regmap); 804 805 priv->clkin = devm_clk_get(&pdev->dev, "clkin"); 806 if (IS_ERR(priv->clkin)) { 807 dev_err(&pdev->dev, "failed to get clkin\n"); 808 return PTR_ERR(priv->clkin); 809 } 810 811 priv->core_clk = devm_clk_get(&pdev->dev, "core"); 812 if (IS_ERR(priv->core_clk)) { 813 dev_err(&pdev->dev, "failed to get core clk\n"); 814 return PTR_ERR(priv->core_clk); 815 } 816 817 priv->sana_clk = devm_clk_get(&pdev->dev, "sana"); 818 if (IS_ERR(priv->sana_clk)) { 819 if (PTR_ERR(priv->sana_clk) == -ENOENT) { 820 priv->sana_clk = NULL; 821 } else { 822 dev_err(&pdev->dev, "failed to get sana clk\n"); 823 return PTR_ERR(priv->sana_clk); 824 } 825 } 826 827 priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk"); 828 if (IS_ERR(priv->adc_clk)) { 829 if (PTR_ERR(priv->adc_clk) == -ENOENT) { 830 priv->adc_clk = NULL; 831 } else { 832 dev_err(&pdev->dev, "failed to get adc clk\n"); 833 return PTR_ERR(priv->adc_clk); 834 } 835 } 836 837 priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel"); 838 if (IS_ERR(priv->adc_sel_clk)) { 839 if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) { 840 priv->adc_sel_clk = NULL; 841 } else { 842 dev_err(&pdev->dev, "failed to get adc_sel clk\n"); 843 return PTR_ERR(priv->adc_sel_clk); 844 } 845 } 846 847 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ 848 if (!priv->adc_clk) { 849 ret = meson_sar_adc_clk_init(indio_dev, base); 850 if (ret) 851 return ret; 852 } 853 854 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 855 if (IS_ERR(priv->vref)) { 856 dev_err(&pdev->dev, "failed to get vref regulator\n"); 857 return PTR_ERR(priv->vref); 858 } 859 860 ret = meson_sar_adc_init(indio_dev); 861 if (ret) 862 goto err; 863 864 ret = meson_sar_adc_hw_enable(indio_dev); 865 if (ret) 866 goto err; 867 868 platform_set_drvdata(pdev, indio_dev); 869 870 ret = iio_device_register(indio_dev); 871 if (ret) 872 goto err_hw; 873 874 return 0; 875 876 err_hw: 877 meson_sar_adc_hw_disable(indio_dev); 878 err: 879 return ret; 880 } 881 882 static int meson_sar_adc_remove(struct platform_device *pdev) 883 { 884 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 885 886 iio_device_unregister(indio_dev); 887 888 return meson_sar_adc_hw_disable(indio_dev); 889 } 890 891 static int __maybe_unused meson_sar_adc_suspend(struct device *dev) 892 { 893 struct iio_dev *indio_dev = dev_get_drvdata(dev); 894 895 return meson_sar_adc_hw_disable(indio_dev); 896 } 897 898 static int __maybe_unused meson_sar_adc_resume(struct device *dev) 899 { 900 struct iio_dev *indio_dev = dev_get_drvdata(dev); 901 902 return meson_sar_adc_hw_enable(indio_dev); 903 } 904 905 static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops, 906 meson_sar_adc_suspend, meson_sar_adc_resume); 907 908 static struct platform_driver meson_sar_adc_driver = { 909 .probe = meson_sar_adc_probe, 910 .remove = meson_sar_adc_remove, 911 .driver = { 912 .name = "meson-saradc", 913 .of_match_table = meson_sar_adc_of_match, 914 .pm = &meson_sar_adc_pm_ops, 915 }, 916 }; 917 918 module_platform_driver(meson_sar_adc_driver); 919 920 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 921 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver"); 922 MODULE_LICENSE("GPL v2"); 923