1 /* 2 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter 3 * 4 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/delay.h> 18 #include <linux/io.h> 19 #include <linux/iio/iio.h> 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 #include <linux/regmap.h> 27 #include <linux/regulator/consumer.h> 28 29 #define MESON_SAR_ADC_REG0 0x00 30 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31) 31 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28) 32 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30) 33 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29) 34 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28) 35 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27) 36 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26) 37 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21) 38 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19) 39 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16) 40 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15) 41 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14) 42 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12) 43 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10) 44 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9) 45 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4) 46 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3) 47 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2) 48 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1) 49 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0) 50 51 #define MESON_SAR_ADC_CHAN_LIST 0x04 52 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24) 53 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ 54 (GENMASK(2, 0) << ((_chan) * 3)) 55 56 #define MESON_SAR_ADC_AVG_CNTL 0x08 57 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ 58 (16 + ((_chan) * 2)) 59 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ 60 (GENMASK(17, 16) << ((_chan) * 2)) 61 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ 62 (0 + ((_chan) * 2)) 63 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ 64 (GENMASK(1, 0) << ((_chan) * 2)) 65 66 #define MESON_SAR_ADC_REG3 0x0c 67 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31) 68 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30) 69 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28) 70 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27) 71 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26) 72 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23) 73 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22) 74 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21) 75 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) 76 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) 77 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 78 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 79 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) 80 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) 81 82 #define MESON_SAR_ADC_DELAY 0x10 83 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24) 84 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15) 85 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14) 86 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16) 87 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8) 88 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0) 89 90 #define MESON_SAR_ADC_LAST_RD 0x14 91 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16) 92 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0) 93 94 #define MESON_SAR_ADC_FIFO_RD 0x18 95 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12) 96 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0) 97 98 #define MESON_SAR_ADC_AUX_SW 0x1c 99 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \ 100 (GENMASK(10, 8) << (((_chan) - 2) * 2)) 101 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6) 102 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5) 103 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4) 104 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3) 105 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2) 106 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1) 107 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0) 108 109 #define MESON_SAR_ADC_CHAN_10_SW 0x20 110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23) 111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22) 112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21) 113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20) 114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19) 115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18) 116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17) 117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16) 118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7) 119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6) 120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5) 121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4) 122 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3) 123 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2) 124 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1) 125 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0) 126 127 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24 128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26) 129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23) 130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22) 131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21) 132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20) 133 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19) 134 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18) 135 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17) 136 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16) 137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7) 138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6) 139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5) 140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4) 141 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3) 142 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2) 143 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1) 144 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0) 145 146 #define MESON_SAR_ADC_DELTA_10 0x28 147 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27) 148 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26) 149 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16) 150 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15) 151 #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11 152 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11) 153 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10) 154 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0) 155 156 /* 157 * NOTE: registers from here are undocumented (the vendor Linux kernel driver 158 * and u-boot source served as reference). These only seem to be relevant on 159 * GXBB and newer. 160 */ 161 #define MESON_SAR_ADC_REG11 0x2c 162 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) 163 164 #define MESON_SAR_ADC_REG13 0x34 165 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8) 166 167 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32 168 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */ 169 /* for use with IIO_VAL_INT_PLUS_MICRO */ 170 #define MILLION 1000000 171 172 #define MESON_SAR_ADC_CHAN(_chan) { \ 173 .type = IIO_VOLTAGE, \ 174 .indexed = 1, \ 175 .channel = _chan, \ 176 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 177 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 178 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 179 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 180 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 181 .datasheet_name = "SAR_ADC_CH"#_chan, \ 182 } 183 184 /* 185 * TODO: the hardware supports IIO_TEMP for channel 6 as well which is 186 * currently not supported by this driver. 187 */ 188 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = { 189 MESON_SAR_ADC_CHAN(0), 190 MESON_SAR_ADC_CHAN(1), 191 MESON_SAR_ADC_CHAN(2), 192 MESON_SAR_ADC_CHAN(3), 193 MESON_SAR_ADC_CHAN(4), 194 MESON_SAR_ADC_CHAN(5), 195 MESON_SAR_ADC_CHAN(6), 196 MESON_SAR_ADC_CHAN(7), 197 IIO_CHAN_SOFT_TIMESTAMP(8), 198 }; 199 200 enum meson_sar_adc_avg_mode { 201 NO_AVERAGING = 0x0, 202 MEAN_AVERAGING = 0x1, 203 MEDIAN_AVERAGING = 0x2, 204 }; 205 206 enum meson_sar_adc_num_samples { 207 ONE_SAMPLE = 0x0, 208 TWO_SAMPLES = 0x1, 209 FOUR_SAMPLES = 0x2, 210 EIGHT_SAMPLES = 0x3, 211 }; 212 213 enum meson_sar_adc_chan7_mux_sel { 214 CHAN7_MUX_VSS = 0x0, 215 CHAN7_MUX_VDD_DIV4 = 0x1, 216 CHAN7_MUX_VDD_DIV2 = 0x2, 217 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3, 218 CHAN7_MUX_VDD = 0x4, 219 CHAN7_MUX_CH7_INPUT = 0x7, 220 }; 221 222 struct meson_sar_adc_data { 223 unsigned int resolution; 224 const char *name; 225 }; 226 227 struct meson_sar_adc_priv { 228 struct regmap *regmap; 229 struct regulator *vref; 230 const struct meson_sar_adc_data *data; 231 struct clk *clkin; 232 struct clk *core_clk; 233 struct clk *sana_clk; 234 struct clk *adc_sel_clk; 235 struct clk *adc_clk; 236 struct clk_gate clk_gate; 237 struct clk *adc_div_clk; 238 struct clk_divider clk_div; 239 struct completion done; 240 int calibbias; 241 int calibscale; 242 }; 243 244 static const struct regmap_config meson_sar_adc_regmap_config = { 245 .reg_bits = 8, 246 .val_bits = 32, 247 .reg_stride = 4, 248 .max_register = MESON_SAR_ADC_REG13, 249 }; 250 251 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev) 252 { 253 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 254 u32 regval; 255 256 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 257 258 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); 259 } 260 261 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val) 262 { 263 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 264 int tmp; 265 266 /* use val_calib = scale * val_raw + offset calibration function */ 267 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; 268 269 return clamp(tmp, 0, (1 << priv->data->resolution) - 1); 270 } 271 272 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev) 273 { 274 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 275 int regval, timeout = 10000; 276 277 /* 278 * NOTE: we need a small delay before reading the status, otherwise 279 * the sample engine may not have started internally (which would 280 * seem to us that sampling is already finished). 281 */ 282 do { 283 udelay(1); 284 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 285 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); 286 287 if (timeout < 0) 288 return -ETIMEDOUT; 289 290 return 0; 291 } 292 293 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, 294 const struct iio_chan_spec *chan, 295 int *val) 296 { 297 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 298 int regval, fifo_chan, fifo_val, count; 299 300 if(!wait_for_completion_timeout(&priv->done, 301 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT))) 302 return -ETIMEDOUT; 303 304 count = meson_sar_adc_get_fifo_count(indio_dev); 305 if (count != 1) { 306 dev_err(&indio_dev->dev, 307 "ADC FIFO has %d element(s) instead of one\n", count); 308 return -EINVAL; 309 } 310 311 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); 312 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); 313 if (fifo_chan != chan->channel) { 314 dev_err(&indio_dev->dev, 315 "ADC FIFO entry belongs to channel %d instead of %d\n", 316 fifo_chan, chan->channel); 317 return -EINVAL; 318 } 319 320 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval); 321 fifo_val &= GENMASK(priv->data->resolution - 1, 0); 322 *val = meson_sar_adc_calib_val(indio_dev, fifo_val); 323 324 return 0; 325 } 326 327 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev, 328 const struct iio_chan_spec *chan, 329 enum meson_sar_adc_avg_mode mode, 330 enum meson_sar_adc_num_samples samples) 331 { 332 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 333 int val, channel = chan->channel; 334 335 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel); 336 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, 337 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel), 338 val); 339 340 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel); 341 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, 342 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val); 343 } 344 345 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev, 346 const struct iio_chan_spec *chan) 347 { 348 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 349 u32 regval; 350 351 /* 352 * the SAR ADC engine allows sampling multiple channels at the same 353 * time. to keep it simple we're only working with one *internal* 354 * channel, which starts counting at index 0 (which means: count = 1). 355 */ 356 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0); 357 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 358 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval); 359 360 /* map channel index 0 to the channel which we want to read */ 361 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), 362 chan->channel); 363 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 364 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval); 365 366 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, 367 chan->channel); 368 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, 369 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, 370 regval); 371 372 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, 373 chan->channel); 374 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, 375 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, 376 regval); 377 378 if (chan->channel == 6) 379 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 380 MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0); 381 } 382 383 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev, 384 enum meson_sar_adc_chan7_mux_sel sel) 385 { 386 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 387 u32 regval; 388 389 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); 390 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 391 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); 392 393 usleep_range(10, 20); 394 } 395 396 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev) 397 { 398 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 399 400 reinit_completion(&priv->done); 401 402 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 403 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 404 MESON_SAR_ADC_REG0_FIFO_IRQ_EN); 405 406 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 407 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 408 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE); 409 410 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 411 MESON_SAR_ADC_REG0_SAMPLING_START, 412 MESON_SAR_ADC_REG0_SAMPLING_START); 413 } 414 415 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev) 416 { 417 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 418 419 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 420 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0); 421 422 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 423 MESON_SAR_ADC_REG0_SAMPLING_STOP, 424 MESON_SAR_ADC_REG0_SAMPLING_STOP); 425 426 /* wait until all modules are stopped */ 427 meson_sar_adc_wait_busy_clear(indio_dev); 428 429 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 430 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0); 431 } 432 433 static int meson_sar_adc_lock(struct iio_dev *indio_dev) 434 { 435 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 436 int val, timeout = 10000; 437 438 mutex_lock(&indio_dev->mlock); 439 440 /* prevent BL30 from using the SAR ADC while we are using it */ 441 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 442 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 443 MESON_SAR_ADC_DELAY_KERNEL_BUSY); 444 445 /* wait until BL30 releases it's lock (so we can use the SAR ADC) */ 446 do { 447 udelay(1); 448 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); 449 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); 450 451 if (timeout < 0) 452 return -ETIMEDOUT; 453 454 return 0; 455 } 456 457 static void meson_sar_adc_unlock(struct iio_dev *indio_dev) 458 { 459 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 460 461 /* allow BL30 to use the SAR ADC again */ 462 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 463 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0); 464 465 mutex_unlock(&indio_dev->mlock); 466 } 467 468 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev) 469 { 470 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 471 int count; 472 473 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) { 474 if (!meson_sar_adc_get_fifo_count(indio_dev)) 475 break; 476 477 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, 0); 478 } 479 } 480 481 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, 482 const struct iio_chan_spec *chan, 483 enum meson_sar_adc_avg_mode avg_mode, 484 enum meson_sar_adc_num_samples avg_samples, 485 int *val) 486 { 487 int ret; 488 489 ret = meson_sar_adc_lock(indio_dev); 490 if (ret) 491 return ret; 492 493 /* clear the FIFO to make sure we're not reading old values */ 494 meson_sar_adc_clear_fifo(indio_dev); 495 496 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples); 497 498 meson_sar_adc_enable_channel(indio_dev, chan); 499 500 meson_sar_adc_start_sample_engine(indio_dev); 501 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val); 502 meson_sar_adc_stop_sample_engine(indio_dev); 503 504 meson_sar_adc_unlock(indio_dev); 505 506 if (ret) { 507 dev_warn(indio_dev->dev.parent, 508 "failed to read sample for channel %d: %d\n", 509 chan->channel, ret); 510 return ret; 511 } 512 513 return IIO_VAL_INT; 514 } 515 516 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, 517 const struct iio_chan_spec *chan, 518 int *val, int *val2, long mask) 519 { 520 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 521 int ret; 522 523 switch (mask) { 524 case IIO_CHAN_INFO_RAW: 525 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING, 526 ONE_SAMPLE, val); 527 break; 528 529 case IIO_CHAN_INFO_AVERAGE_RAW: 530 return meson_sar_adc_get_sample(indio_dev, chan, 531 MEAN_AVERAGING, EIGHT_SAMPLES, 532 val); 533 break; 534 535 case IIO_CHAN_INFO_SCALE: 536 ret = regulator_get_voltage(priv->vref); 537 if (ret < 0) { 538 dev_err(indio_dev->dev.parent, 539 "failed to get vref voltage: %d\n", ret); 540 return ret; 541 } 542 543 *val = ret / 1000; 544 *val2 = priv->data->resolution; 545 return IIO_VAL_FRACTIONAL_LOG2; 546 547 case IIO_CHAN_INFO_CALIBBIAS: 548 *val = priv->calibbias; 549 return IIO_VAL_INT; 550 551 case IIO_CHAN_INFO_CALIBSCALE: 552 *val = priv->calibscale / MILLION; 553 *val2 = priv->calibscale % MILLION; 554 return IIO_VAL_INT_PLUS_MICRO; 555 556 default: 557 return -EINVAL; 558 } 559 } 560 561 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, 562 void __iomem *base) 563 { 564 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 565 struct clk_init_data init; 566 const char *clk_parents[1]; 567 568 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div", 569 of_node_full_name(indio_dev->dev.of_node)); 570 init.flags = 0; 571 init.ops = &clk_divider_ops; 572 clk_parents[0] = __clk_get_name(priv->clkin); 573 init.parent_names = clk_parents; 574 init.num_parents = 1; 575 576 priv->clk_div.reg = base + MESON_SAR_ADC_REG3; 577 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT; 578 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH; 579 priv->clk_div.hw.init = &init; 580 priv->clk_div.flags = 0; 581 582 priv->adc_div_clk = devm_clk_register(&indio_dev->dev, 583 &priv->clk_div.hw); 584 if (WARN_ON(IS_ERR(priv->adc_div_clk))) 585 return PTR_ERR(priv->adc_div_clk); 586 587 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en", 588 of_node_full_name(indio_dev->dev.of_node)); 589 init.flags = CLK_SET_RATE_PARENT; 590 init.ops = &clk_gate_ops; 591 clk_parents[0] = __clk_get_name(priv->adc_div_clk); 592 init.parent_names = clk_parents; 593 init.num_parents = 1; 594 595 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; 596 priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN); 597 priv->clk_gate.hw.init = &init; 598 599 priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw); 600 if (WARN_ON(IS_ERR(priv->adc_clk))) 601 return PTR_ERR(priv->adc_clk); 602 603 return 0; 604 } 605 606 static int meson_sar_adc_init(struct iio_dev *indio_dev) 607 { 608 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 609 int regval, ret; 610 611 /* 612 * make sure we start at CH7 input since the other muxes are only used 613 * for internal calibration. 614 */ 615 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT); 616 617 /* 618 * leave sampling delay and the input clocks as configured by BL30 to 619 * make sure BL30 gets the values it expects when reading the 620 * temperature sensor. 621 */ 622 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); 623 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) 624 return 0; 625 626 meson_sar_adc_stop_sample_engine(indio_dev); 627 628 /* update the channel 6 MUX to select the temperature sensor */ 629 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 630 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 631 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL); 632 633 /* disable all channels by default */ 634 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); 635 636 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 637 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0); 638 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 639 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY, 640 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY); 641 642 /* delay between two samples = (10+1) * 1uS */ 643 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 644 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 645 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 646 10)); 647 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 648 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 649 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 650 0)); 651 652 /* delay between two samples = (10+1) * 1uS */ 653 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 654 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 655 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 656 10)); 657 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 658 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 659 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 660 1)); 661 662 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); 663 if (ret) { 664 dev_err(indio_dev->dev.parent, 665 "failed to set adc parent to clkin\n"); 666 return ret; 667 } 668 669 ret = clk_set_rate(priv->adc_clk, 1200000); 670 if (ret) { 671 dev_err(indio_dev->dev.parent, 672 "failed to set adc clock rate\n"); 673 return ret; 674 } 675 676 return 0; 677 } 678 679 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) 680 { 681 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 682 int ret; 683 u32 regval; 684 685 ret = meson_sar_adc_lock(indio_dev); 686 if (ret) 687 goto err_lock; 688 689 ret = regulator_enable(priv->vref); 690 if (ret < 0) { 691 dev_err(indio_dev->dev.parent, 692 "failed to enable vref regulator\n"); 693 goto err_vref; 694 } 695 696 ret = clk_prepare_enable(priv->core_clk); 697 if (ret) { 698 dev_err(indio_dev->dev.parent, "failed to enable core clk\n"); 699 goto err_core_clk; 700 } 701 702 ret = clk_prepare_enable(priv->sana_clk); 703 if (ret) { 704 dev_err(indio_dev->dev.parent, "failed to enable sana clk\n"); 705 goto err_sana_clk; 706 } 707 708 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1); 709 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 710 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); 711 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 712 MESON_SAR_ADC_REG11_BANDGAP_EN, 713 MESON_SAR_ADC_REG11_BANDGAP_EN); 714 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 715 MESON_SAR_ADC_REG3_ADC_EN, 716 MESON_SAR_ADC_REG3_ADC_EN); 717 718 udelay(5); 719 720 ret = clk_prepare_enable(priv->adc_clk); 721 if (ret) { 722 dev_err(indio_dev->dev.parent, "failed to enable adc clk\n"); 723 goto err_adc_clk; 724 } 725 726 meson_sar_adc_unlock(indio_dev); 727 728 return 0; 729 730 err_adc_clk: 731 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 732 MESON_SAR_ADC_REG3_ADC_EN, 0); 733 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 734 MESON_SAR_ADC_REG11_BANDGAP_EN, 0); 735 clk_disable_unprepare(priv->sana_clk); 736 err_sana_clk: 737 clk_disable_unprepare(priv->core_clk); 738 err_core_clk: 739 regulator_disable(priv->vref); 740 err_vref: 741 meson_sar_adc_unlock(indio_dev); 742 err_lock: 743 return ret; 744 } 745 746 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev) 747 { 748 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 749 int ret; 750 751 ret = meson_sar_adc_lock(indio_dev); 752 if (ret) 753 return ret; 754 755 clk_disable_unprepare(priv->adc_clk); 756 757 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 758 MESON_SAR_ADC_REG3_ADC_EN, 0); 759 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 760 MESON_SAR_ADC_REG11_BANDGAP_EN, 0); 761 762 clk_disable_unprepare(priv->sana_clk); 763 clk_disable_unprepare(priv->core_clk); 764 765 regulator_disable(priv->vref); 766 767 meson_sar_adc_unlock(indio_dev); 768 769 return 0; 770 } 771 772 static irqreturn_t meson_sar_adc_irq(int irq, void *data) 773 { 774 struct iio_dev *indio_dev = data; 775 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 776 unsigned int cnt, threshold; 777 u32 regval; 778 779 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 780 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); 781 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); 782 783 if (cnt < threshold) 784 return IRQ_NONE; 785 786 complete(&priv->done); 787 788 return IRQ_HANDLED; 789 } 790 791 static int meson_sar_adc_calib(struct iio_dev *indio_dev) 792 { 793 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 794 int ret, nominal0, nominal1, value0, value1; 795 796 /* use points 25% and 75% for calibration */ 797 nominal0 = (1 << priv->data->resolution) / 4; 798 nominal1 = (1 << priv->data->resolution) * 3 / 4; 799 800 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4); 801 usleep_range(10, 20); 802 ret = meson_sar_adc_get_sample(indio_dev, 803 &meson_sar_adc_iio_channels[7], 804 MEAN_AVERAGING, EIGHT_SAMPLES, &value0); 805 if (ret < 0) 806 goto out; 807 808 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4); 809 usleep_range(10, 20); 810 ret = meson_sar_adc_get_sample(indio_dev, 811 &meson_sar_adc_iio_channels[7], 812 MEAN_AVERAGING, EIGHT_SAMPLES, &value1); 813 if (ret < 0) 814 goto out; 815 816 if (value1 <= value0) { 817 ret = -EINVAL; 818 goto out; 819 } 820 821 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION, 822 value1 - value0); 823 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, 824 MILLION); 825 ret = 0; 826 out: 827 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT); 828 829 return ret; 830 } 831 832 static const struct iio_info meson_sar_adc_iio_info = { 833 .read_raw = meson_sar_adc_iio_info_read_raw, 834 .driver_module = THIS_MODULE, 835 }; 836 837 struct meson_sar_adc_data meson_sar_adc_gxbb_data = { 838 .resolution = 10, 839 .name = "meson-gxbb-saradc", 840 }; 841 842 struct meson_sar_adc_data meson_sar_adc_gxl_data = { 843 .resolution = 12, 844 .name = "meson-gxl-saradc", 845 }; 846 847 struct meson_sar_adc_data meson_sar_adc_gxm_data = { 848 .resolution = 12, 849 .name = "meson-gxm-saradc", 850 }; 851 852 static const struct of_device_id meson_sar_adc_of_match[] = { 853 { 854 .compatible = "amlogic,meson-gxbb-saradc", 855 .data = &meson_sar_adc_gxbb_data, 856 }, { 857 .compatible = "amlogic,meson-gxl-saradc", 858 .data = &meson_sar_adc_gxl_data, 859 }, { 860 .compatible = "amlogic,meson-gxm-saradc", 861 .data = &meson_sar_adc_gxm_data, 862 }, 863 {}, 864 }; 865 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match); 866 867 static int meson_sar_adc_probe(struct platform_device *pdev) 868 { 869 struct meson_sar_adc_priv *priv; 870 struct iio_dev *indio_dev; 871 struct resource *res; 872 void __iomem *base; 873 const struct of_device_id *match; 874 int irq, ret; 875 876 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); 877 if (!indio_dev) { 878 dev_err(&pdev->dev, "failed allocating iio device\n"); 879 return -ENOMEM; 880 } 881 882 priv = iio_priv(indio_dev); 883 init_completion(&priv->done); 884 885 match = of_match_device(meson_sar_adc_of_match, &pdev->dev); 886 priv->data = match->data; 887 888 indio_dev->name = priv->data->name; 889 indio_dev->dev.parent = &pdev->dev; 890 indio_dev->dev.of_node = pdev->dev.of_node; 891 indio_dev->modes = INDIO_DIRECT_MODE; 892 indio_dev->info = &meson_sar_adc_iio_info; 893 894 indio_dev->channels = meson_sar_adc_iio_channels; 895 indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels); 896 897 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 898 base = devm_ioremap_resource(&pdev->dev, res); 899 if (IS_ERR(base)) 900 return PTR_ERR(base); 901 902 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 903 if (!irq) 904 return -EINVAL; 905 906 ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED, 907 dev_name(&pdev->dev), indio_dev); 908 if (ret) 909 return ret; 910 911 priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, 912 &meson_sar_adc_regmap_config); 913 if (IS_ERR(priv->regmap)) 914 return PTR_ERR(priv->regmap); 915 916 priv->clkin = devm_clk_get(&pdev->dev, "clkin"); 917 if (IS_ERR(priv->clkin)) { 918 dev_err(&pdev->dev, "failed to get clkin\n"); 919 return PTR_ERR(priv->clkin); 920 } 921 922 priv->core_clk = devm_clk_get(&pdev->dev, "core"); 923 if (IS_ERR(priv->core_clk)) { 924 dev_err(&pdev->dev, "failed to get core clk\n"); 925 return PTR_ERR(priv->core_clk); 926 } 927 928 priv->sana_clk = devm_clk_get(&pdev->dev, "sana"); 929 if (IS_ERR(priv->sana_clk)) { 930 if (PTR_ERR(priv->sana_clk) == -ENOENT) { 931 priv->sana_clk = NULL; 932 } else { 933 dev_err(&pdev->dev, "failed to get sana clk\n"); 934 return PTR_ERR(priv->sana_clk); 935 } 936 } 937 938 priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk"); 939 if (IS_ERR(priv->adc_clk)) { 940 if (PTR_ERR(priv->adc_clk) == -ENOENT) { 941 priv->adc_clk = NULL; 942 } else { 943 dev_err(&pdev->dev, "failed to get adc clk\n"); 944 return PTR_ERR(priv->adc_clk); 945 } 946 } 947 948 priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel"); 949 if (IS_ERR(priv->adc_sel_clk)) { 950 if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) { 951 priv->adc_sel_clk = NULL; 952 } else { 953 dev_err(&pdev->dev, "failed to get adc_sel clk\n"); 954 return PTR_ERR(priv->adc_sel_clk); 955 } 956 } 957 958 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ 959 if (!priv->adc_clk) { 960 ret = meson_sar_adc_clk_init(indio_dev, base); 961 if (ret) 962 return ret; 963 } 964 965 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 966 if (IS_ERR(priv->vref)) { 967 dev_err(&pdev->dev, "failed to get vref regulator\n"); 968 return PTR_ERR(priv->vref); 969 } 970 971 priv->calibscale = MILLION; 972 973 ret = meson_sar_adc_init(indio_dev); 974 if (ret) 975 goto err; 976 977 ret = meson_sar_adc_hw_enable(indio_dev); 978 if (ret) 979 goto err; 980 981 ret = meson_sar_adc_calib(indio_dev); 982 if (ret) 983 dev_warn(&pdev->dev, "calibration failed\n"); 984 985 platform_set_drvdata(pdev, indio_dev); 986 987 ret = iio_device_register(indio_dev); 988 if (ret) 989 goto err_hw; 990 991 return 0; 992 993 err_hw: 994 meson_sar_adc_hw_disable(indio_dev); 995 err: 996 return ret; 997 } 998 999 static int meson_sar_adc_remove(struct platform_device *pdev) 1000 { 1001 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1002 1003 iio_device_unregister(indio_dev); 1004 1005 return meson_sar_adc_hw_disable(indio_dev); 1006 } 1007 1008 static int __maybe_unused meson_sar_adc_suspend(struct device *dev) 1009 { 1010 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1011 1012 return meson_sar_adc_hw_disable(indio_dev); 1013 } 1014 1015 static int __maybe_unused meson_sar_adc_resume(struct device *dev) 1016 { 1017 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1018 1019 return meson_sar_adc_hw_enable(indio_dev); 1020 } 1021 1022 static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops, 1023 meson_sar_adc_suspend, meson_sar_adc_resume); 1024 1025 static struct platform_driver meson_sar_adc_driver = { 1026 .probe = meson_sar_adc_probe, 1027 .remove = meson_sar_adc_remove, 1028 .driver = { 1029 .name = "meson-saradc", 1030 .of_match_table = meson_sar_adc_of_match, 1031 .pm = &meson_sar_adc_pm_ops, 1032 }, 1033 }; 1034 1035 module_platform_driver(meson_sar_adc_driver); 1036 1037 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 1038 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver"); 1039 MODULE_LICENSE("GPL v2"); 1040