1 /* 2 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter 3 * 4 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/delay.h> 18 #include <linux/io.h> 19 #include <linux/iio/iio.h> 20 #include <linux/module.h> 21 #include <linux/nvmem-consumer.h> 22 #include <linux/interrupt.h> 23 #include <linux/of.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/mfd/syscon.h> 30 31 #define MESON_SAR_ADC_REG0 0x00 32 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31) 33 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28) 34 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30) 35 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29) 36 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28) 37 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27) 38 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26) 39 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21) 40 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19) 41 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16) 42 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15) 43 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14) 44 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12) 45 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10) 46 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9) 47 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4) 48 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3) 49 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2) 50 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1) 51 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0) 52 53 #define MESON_SAR_ADC_CHAN_LIST 0x04 54 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24) 55 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ 56 (GENMASK(2, 0) << ((_chan) * 3)) 57 58 #define MESON_SAR_ADC_AVG_CNTL 0x08 59 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ 60 (16 + ((_chan) * 2)) 61 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ 62 (GENMASK(17, 16) << ((_chan) * 2)) 63 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ 64 (0 + ((_chan) * 2)) 65 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ 66 (GENMASK(1, 0) << ((_chan) * 2)) 67 68 #define MESON_SAR_ADC_REG3 0x0c 69 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31) 70 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30) 71 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28) 72 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27) 73 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26) 74 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23) 75 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22) 76 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21) 77 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) 78 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) 79 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 80 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 81 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) 82 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) 83 84 #define MESON_SAR_ADC_DELAY 0x10 85 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24) 86 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15) 87 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14) 88 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16) 89 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8) 90 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0) 91 92 #define MESON_SAR_ADC_LAST_RD 0x14 93 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16) 94 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0) 95 96 #define MESON_SAR_ADC_FIFO_RD 0x18 97 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12) 98 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0) 99 100 #define MESON_SAR_ADC_AUX_SW 0x1c 101 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \ 102 (8 + (((_chan) - 2) * 3)) 103 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6) 104 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5) 105 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4) 106 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3) 107 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2) 108 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1) 109 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0) 110 111 #define MESON_SAR_ADC_CHAN_10_SW 0x20 112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23) 113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22) 114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21) 115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20) 116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19) 117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18) 118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17) 119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16) 120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7) 121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6) 122 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5) 123 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4) 124 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3) 125 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2) 126 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1) 127 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0) 128 129 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24 130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26) 131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23) 132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22) 133 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21) 134 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20) 135 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19) 136 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18) 137 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17) 138 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16) 139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7) 140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6) 141 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5) 142 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4) 143 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3) 144 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2) 145 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1) 146 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0) 147 148 #define MESON_SAR_ADC_DELTA_10 0x28 149 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27) 150 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26) 151 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16) 152 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15) 153 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11) 154 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10) 155 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0) 156 157 /* 158 * NOTE: registers from here are undocumented (the vendor Linux kernel driver 159 * and u-boot source served as reference). These only seem to be relevant on 160 * GXBB and newer. 161 */ 162 #define MESON_SAR_ADC_REG11 0x2c 163 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) 164 165 #define MESON_SAR_ADC_REG13 0x34 166 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8) 167 168 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32 169 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */ 170 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6 171 #define MESON_SAR_ADC_TEMP_OFFSET 27 172 173 /* temperature sensor calibration information in eFuse */ 174 #define MESON_SAR_ADC_EFUSE_BYTES 4 175 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0) 176 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7) 177 178 #define MESON_HHI_DPLL_TOP_0 0x318 179 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9) 180 181 /* for use with IIO_VAL_INT_PLUS_MICRO */ 182 #define MILLION 1000000 183 184 #define MESON_SAR_ADC_CHAN(_chan) { \ 185 .type = IIO_VOLTAGE, \ 186 .indexed = 1, \ 187 .channel = _chan, \ 188 .address = _chan, \ 189 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 190 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 191 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 192 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 193 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 194 .datasheet_name = "SAR_ADC_CH"#_chan, \ 195 } 196 197 #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \ 198 .type = IIO_TEMP, \ 199 .channel = _chan, \ 200 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \ 201 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 202 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 203 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \ 204 BIT(IIO_CHAN_INFO_SCALE), \ 205 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 206 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 207 .datasheet_name = "TEMP_SENSOR", \ 208 } 209 210 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = { 211 MESON_SAR_ADC_CHAN(0), 212 MESON_SAR_ADC_CHAN(1), 213 MESON_SAR_ADC_CHAN(2), 214 MESON_SAR_ADC_CHAN(3), 215 MESON_SAR_ADC_CHAN(4), 216 MESON_SAR_ADC_CHAN(5), 217 MESON_SAR_ADC_CHAN(6), 218 MESON_SAR_ADC_CHAN(7), 219 IIO_CHAN_SOFT_TIMESTAMP(8), 220 }; 221 222 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = { 223 MESON_SAR_ADC_CHAN(0), 224 MESON_SAR_ADC_CHAN(1), 225 MESON_SAR_ADC_CHAN(2), 226 MESON_SAR_ADC_CHAN(3), 227 MESON_SAR_ADC_CHAN(4), 228 MESON_SAR_ADC_CHAN(5), 229 MESON_SAR_ADC_CHAN(6), 230 MESON_SAR_ADC_CHAN(7), 231 MESON_SAR_ADC_TEMP_CHAN(8), 232 IIO_CHAN_SOFT_TIMESTAMP(9), 233 }; 234 235 enum meson_sar_adc_avg_mode { 236 NO_AVERAGING = 0x0, 237 MEAN_AVERAGING = 0x1, 238 MEDIAN_AVERAGING = 0x2, 239 }; 240 241 enum meson_sar_adc_num_samples { 242 ONE_SAMPLE = 0x0, 243 TWO_SAMPLES = 0x1, 244 FOUR_SAMPLES = 0x2, 245 EIGHT_SAMPLES = 0x3, 246 }; 247 248 enum meson_sar_adc_chan7_mux_sel { 249 CHAN7_MUX_VSS = 0x0, 250 CHAN7_MUX_VDD_DIV4 = 0x1, 251 CHAN7_MUX_VDD_DIV2 = 0x2, 252 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3, 253 CHAN7_MUX_VDD = 0x4, 254 CHAN7_MUX_CH7_INPUT = 0x7, 255 }; 256 257 struct meson_sar_adc_param { 258 bool has_bl30_integration; 259 unsigned long clock_rate; 260 u32 bandgap_reg; 261 unsigned int resolution; 262 const struct regmap_config *regmap_config; 263 u8 temperature_trimming_bits; 264 unsigned int temperature_multiplier; 265 unsigned int temperature_divider; 266 }; 267 268 struct meson_sar_adc_data { 269 const struct meson_sar_adc_param *param; 270 const char *name; 271 }; 272 273 struct meson_sar_adc_priv { 274 struct regmap *regmap; 275 struct regulator *vref; 276 const struct meson_sar_adc_param *param; 277 struct clk *clkin; 278 struct clk *core_clk; 279 struct clk *adc_sel_clk; 280 struct clk *adc_clk; 281 struct clk_gate clk_gate; 282 struct clk *adc_div_clk; 283 struct clk_divider clk_div; 284 struct completion done; 285 int calibbias; 286 int calibscale; 287 struct regmap *tsc_regmap; 288 bool temperature_sensor_calibrated; 289 u8 temperature_sensor_coefficient; 290 u16 temperature_sensor_adc_val; 291 }; 292 293 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = { 294 .reg_bits = 8, 295 .val_bits = 32, 296 .reg_stride = 4, 297 .max_register = MESON_SAR_ADC_REG13, 298 }; 299 300 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = { 301 .reg_bits = 8, 302 .val_bits = 32, 303 .reg_stride = 4, 304 .max_register = MESON_SAR_ADC_DELTA_10, 305 }; 306 307 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev) 308 { 309 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 310 u32 regval; 311 312 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 313 314 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); 315 } 316 317 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val) 318 { 319 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 320 int tmp; 321 322 /* use val_calib = scale * val_raw + offset calibration function */ 323 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; 324 325 return clamp(tmp, 0, (1 << priv->param->resolution) - 1); 326 } 327 328 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev) 329 { 330 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 331 int regval, timeout = 10000; 332 333 /* 334 * NOTE: we need a small delay before reading the status, otherwise 335 * the sample engine may not have started internally (which would 336 * seem to us that sampling is already finished). 337 */ 338 do { 339 udelay(1); 340 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 341 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); 342 343 if (timeout < 0) 344 return -ETIMEDOUT; 345 346 return 0; 347 } 348 349 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, 350 const struct iio_chan_spec *chan, 351 int *val) 352 { 353 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 354 int regval, fifo_chan, fifo_val, count; 355 356 if(!wait_for_completion_timeout(&priv->done, 357 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT))) 358 return -ETIMEDOUT; 359 360 count = meson_sar_adc_get_fifo_count(indio_dev); 361 if (count != 1) { 362 dev_err(&indio_dev->dev, 363 "ADC FIFO has %d element(s) instead of one\n", count); 364 return -EINVAL; 365 } 366 367 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); 368 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); 369 if (fifo_chan != chan->address) { 370 dev_err(&indio_dev->dev, 371 "ADC FIFO entry belongs to channel %d instead of %lu\n", 372 fifo_chan, chan->address); 373 return -EINVAL; 374 } 375 376 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval); 377 fifo_val &= GENMASK(priv->param->resolution - 1, 0); 378 *val = meson_sar_adc_calib_val(indio_dev, fifo_val); 379 380 return 0; 381 } 382 383 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev, 384 const struct iio_chan_spec *chan, 385 enum meson_sar_adc_avg_mode mode, 386 enum meson_sar_adc_num_samples samples) 387 { 388 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 389 int val, address = chan->address; 390 391 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address); 392 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, 393 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address), 394 val); 395 396 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address); 397 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, 398 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val); 399 } 400 401 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev, 402 const struct iio_chan_spec *chan) 403 { 404 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 405 u32 regval; 406 407 /* 408 * the SAR ADC engine allows sampling multiple channels at the same 409 * time. to keep it simple we're only working with one *internal* 410 * channel, which starts counting at index 0 (which means: count = 1). 411 */ 412 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0); 413 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 414 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval); 415 416 /* map channel index 0 to the channel which we want to read */ 417 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), 418 chan->address); 419 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 420 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval); 421 422 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, 423 chan->address); 424 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, 425 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, 426 regval); 427 428 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, 429 chan->address); 430 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, 431 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, 432 regval); 433 434 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) { 435 if (chan->type == IIO_TEMP) 436 regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL; 437 else 438 regval = 0; 439 440 regmap_update_bits(priv->regmap, 441 MESON_SAR_ADC_DELTA_10, 442 MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval); 443 } 444 } 445 446 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev, 447 enum meson_sar_adc_chan7_mux_sel sel) 448 { 449 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 450 u32 regval; 451 452 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); 453 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 454 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); 455 456 usleep_range(10, 20); 457 } 458 459 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev) 460 { 461 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 462 463 reinit_completion(&priv->done); 464 465 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 466 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 467 MESON_SAR_ADC_REG0_FIFO_IRQ_EN); 468 469 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 470 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 471 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE); 472 473 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 474 MESON_SAR_ADC_REG0_SAMPLING_START, 475 MESON_SAR_ADC_REG0_SAMPLING_START); 476 } 477 478 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev) 479 { 480 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 481 482 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 483 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0); 484 485 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 486 MESON_SAR_ADC_REG0_SAMPLING_STOP, 487 MESON_SAR_ADC_REG0_SAMPLING_STOP); 488 489 /* wait until all modules are stopped */ 490 meson_sar_adc_wait_busy_clear(indio_dev); 491 492 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 493 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0); 494 } 495 496 static int meson_sar_adc_lock(struct iio_dev *indio_dev) 497 { 498 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 499 int val, timeout = 10000; 500 501 mutex_lock(&indio_dev->mlock); 502 503 if (priv->param->has_bl30_integration) { 504 /* prevent BL30 from using the SAR ADC while we are using it */ 505 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 506 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 507 MESON_SAR_ADC_DELAY_KERNEL_BUSY); 508 509 /* 510 * wait until BL30 releases it's lock (so we can use the SAR 511 * ADC) 512 */ 513 do { 514 udelay(1); 515 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); 516 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); 517 518 if (timeout < 0) { 519 mutex_unlock(&indio_dev->mlock); 520 return -ETIMEDOUT; 521 } 522 } 523 524 return 0; 525 } 526 527 static void meson_sar_adc_unlock(struct iio_dev *indio_dev) 528 { 529 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 530 531 if (priv->param->has_bl30_integration) 532 /* allow BL30 to use the SAR ADC again */ 533 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 534 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0); 535 536 mutex_unlock(&indio_dev->mlock); 537 } 538 539 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev) 540 { 541 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 542 unsigned int count, tmp; 543 544 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) { 545 if (!meson_sar_adc_get_fifo_count(indio_dev)) 546 break; 547 548 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp); 549 } 550 } 551 552 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, 553 const struct iio_chan_spec *chan, 554 enum meson_sar_adc_avg_mode avg_mode, 555 enum meson_sar_adc_num_samples avg_samples, 556 int *val) 557 { 558 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 559 int ret; 560 561 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) 562 return -ENOTSUPP; 563 564 ret = meson_sar_adc_lock(indio_dev); 565 if (ret) 566 return ret; 567 568 /* clear the FIFO to make sure we're not reading old values */ 569 meson_sar_adc_clear_fifo(indio_dev); 570 571 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples); 572 573 meson_sar_adc_enable_channel(indio_dev, chan); 574 575 meson_sar_adc_start_sample_engine(indio_dev); 576 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val); 577 meson_sar_adc_stop_sample_engine(indio_dev); 578 579 meson_sar_adc_unlock(indio_dev); 580 581 if (ret) { 582 dev_warn(indio_dev->dev.parent, 583 "failed to read sample for channel %lu: %d\n", 584 chan->address, ret); 585 return ret; 586 } 587 588 return IIO_VAL_INT; 589 } 590 591 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, 592 const struct iio_chan_spec *chan, 593 int *val, int *val2, long mask) 594 { 595 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 596 int ret; 597 598 switch (mask) { 599 case IIO_CHAN_INFO_RAW: 600 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING, 601 ONE_SAMPLE, val); 602 break; 603 604 case IIO_CHAN_INFO_AVERAGE_RAW: 605 return meson_sar_adc_get_sample(indio_dev, chan, 606 MEAN_AVERAGING, EIGHT_SAMPLES, 607 val); 608 break; 609 610 case IIO_CHAN_INFO_SCALE: 611 if (chan->type == IIO_VOLTAGE) { 612 ret = regulator_get_voltage(priv->vref); 613 if (ret < 0) { 614 dev_err(indio_dev->dev.parent, 615 "failed to get vref voltage: %d\n", 616 ret); 617 return ret; 618 } 619 620 *val = ret / 1000; 621 *val2 = priv->param->resolution; 622 return IIO_VAL_FRACTIONAL_LOG2; 623 } else if (chan->type == IIO_TEMP) { 624 /* SoC specific multiplier and divider */ 625 *val = priv->param->temperature_multiplier; 626 *val2 = priv->param->temperature_divider; 627 628 /* celsius to millicelsius */ 629 *val *= 1000; 630 631 return IIO_VAL_FRACTIONAL; 632 } else { 633 return -EINVAL; 634 } 635 636 case IIO_CHAN_INFO_CALIBBIAS: 637 *val = priv->calibbias; 638 return IIO_VAL_INT; 639 640 case IIO_CHAN_INFO_CALIBSCALE: 641 *val = priv->calibscale / MILLION; 642 *val2 = priv->calibscale % MILLION; 643 return IIO_VAL_INT_PLUS_MICRO; 644 645 case IIO_CHAN_INFO_OFFSET: 646 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET * 647 priv->param->temperature_divider, 648 priv->param->temperature_multiplier); 649 *val -= priv->temperature_sensor_adc_val; 650 return IIO_VAL_INT; 651 652 default: 653 return -EINVAL; 654 } 655 } 656 657 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, 658 void __iomem *base) 659 { 660 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 661 struct clk_init_data init; 662 const char *clk_parents[1]; 663 664 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div", 665 dev_name(indio_dev->dev.parent)); 666 if (!init.name) 667 return -ENOMEM; 668 669 init.flags = 0; 670 init.ops = &clk_divider_ops; 671 clk_parents[0] = __clk_get_name(priv->clkin); 672 init.parent_names = clk_parents; 673 init.num_parents = 1; 674 675 priv->clk_div.reg = base + MESON_SAR_ADC_REG3; 676 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT; 677 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH; 678 priv->clk_div.hw.init = &init; 679 priv->clk_div.flags = 0; 680 681 priv->adc_div_clk = devm_clk_register(&indio_dev->dev, 682 &priv->clk_div.hw); 683 if (WARN_ON(IS_ERR(priv->adc_div_clk))) 684 return PTR_ERR(priv->adc_div_clk); 685 686 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en", 687 dev_name(indio_dev->dev.parent)); 688 if (!init.name) 689 return -ENOMEM; 690 691 init.flags = CLK_SET_RATE_PARENT; 692 init.ops = &clk_gate_ops; 693 clk_parents[0] = __clk_get_name(priv->adc_div_clk); 694 init.parent_names = clk_parents; 695 init.num_parents = 1; 696 697 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; 698 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); 699 priv->clk_gate.hw.init = &init; 700 701 priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw); 702 if (WARN_ON(IS_ERR(priv->adc_clk))) 703 return PTR_ERR(priv->adc_clk); 704 705 return 0; 706 } 707 708 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) 709 { 710 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 711 u8 *buf, trimming_bits, trimming_mask, upper_adc_val; 712 struct nvmem_cell *temperature_calib; 713 size_t read_len; 714 int ret; 715 716 temperature_calib = devm_nvmem_cell_get(&indio_dev->dev, 717 "temperature_calib"); 718 if (IS_ERR(temperature_calib)) { 719 ret = PTR_ERR(temperature_calib); 720 721 /* 722 * leave the temperature sensor disabled if no calibration data 723 * was passed via nvmem-cells. 724 */ 725 if (ret == -ENODEV) 726 return 0; 727 728 if (ret != -EPROBE_DEFER) 729 dev_err(indio_dev->dev.parent, 730 "failed to get temperature_calib cell\n"); 731 732 return ret; 733 } 734 735 priv->tsc_regmap = 736 syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node, 737 "amlogic,hhi-sysctrl"); 738 if (IS_ERR(priv->tsc_regmap)) { 739 dev_err(indio_dev->dev.parent, 740 "failed to get amlogic,hhi-sysctrl regmap\n"); 741 return PTR_ERR(priv->tsc_regmap); 742 } 743 744 read_len = MESON_SAR_ADC_EFUSE_BYTES; 745 buf = nvmem_cell_read(temperature_calib, &read_len); 746 if (IS_ERR(buf)) { 747 dev_err(indio_dev->dev.parent, 748 "failed to read temperature_calib cell\n"); 749 return PTR_ERR(buf); 750 } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) { 751 kfree(buf); 752 dev_err(indio_dev->dev.parent, 753 "invalid read size of temperature_calib cell\n"); 754 return -EINVAL; 755 } 756 757 trimming_bits = priv->param->temperature_trimming_bits; 758 trimming_mask = BIT(trimming_bits) - 1; 759 760 priv->temperature_sensor_calibrated = 761 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED; 762 priv->temperature_sensor_coefficient = buf[2] & trimming_mask; 763 764 upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL, 765 buf[3]); 766 767 priv->temperature_sensor_adc_val = buf[2]; 768 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE; 769 priv->temperature_sensor_adc_val >>= trimming_bits; 770 771 kfree(buf); 772 773 return 0; 774 } 775 776 static int meson_sar_adc_init(struct iio_dev *indio_dev) 777 { 778 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 779 int regval, i, ret; 780 781 /* 782 * make sure we start at CH7 input since the other muxes are only used 783 * for internal calibration. 784 */ 785 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT); 786 787 if (priv->param->has_bl30_integration) { 788 /* 789 * leave sampling delay and the input clocks as configured by 790 * BL30 to make sure BL30 gets the values it expects when 791 * reading the temperature sensor. 792 */ 793 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); 794 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) 795 return 0; 796 } 797 798 meson_sar_adc_stop_sample_engine(indio_dev); 799 800 /* 801 * disable this bit as seems to be only relevant for Meson6 (based 802 * on the vendor driver), which we don't support at the moment. 803 */ 804 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 805 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0); 806 807 /* disable all channels by default */ 808 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); 809 810 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 811 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0); 812 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 813 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY, 814 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY); 815 816 /* delay between two samples = (10+1) * 1uS */ 817 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 818 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 819 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 820 10)); 821 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 822 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 823 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 824 0)); 825 826 /* delay between two samples = (10+1) * 1uS */ 827 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 828 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 829 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 830 10)); 831 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 832 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 833 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 834 1)); 835 836 /* 837 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW 838 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1) 839 */ 840 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0); 841 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, 842 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 843 regval); 844 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1); 845 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, 846 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 847 regval); 848 849 /* 850 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW 851 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable 852 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and 853 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver. 854 */ 855 regval = 0; 856 for (i = 2; i <= 7; i++) 857 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i); 858 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW; 859 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW; 860 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); 861 862 if (priv->temperature_sensor_calibrated) { 863 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 864 MESON_SAR_ADC_DELTA_10_TS_REVE1, 865 MESON_SAR_ADC_DELTA_10_TS_REVE1); 866 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 867 MESON_SAR_ADC_DELTA_10_TS_REVE0, 868 MESON_SAR_ADC_DELTA_10_TS_REVE0); 869 870 /* 871 * set bits [3:0] of the TSC (temperature sensor coefficient) 872 * to get the correct values when reading the temperature. 873 */ 874 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK, 875 priv->temperature_sensor_coefficient); 876 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 877 MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval); 878 879 if (priv->param->temperature_trimming_bits == 5) { 880 if (priv->temperature_sensor_coefficient & BIT(4)) 881 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4; 882 else 883 regval = 0; 884 885 /* 886 * bit [4] (the 5th bit when starting to count at 1) 887 * of the TSC is located in the HHI register area. 888 */ 889 regmap_update_bits(priv->tsc_regmap, 890 MESON_HHI_DPLL_TOP_0, 891 MESON_HHI_DPLL_TOP_0_TSC_BIT4, 892 regval); 893 } 894 } else { 895 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 896 MESON_SAR_ADC_DELTA_10_TS_REVE1, 0); 897 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 898 MESON_SAR_ADC_DELTA_10_TS_REVE0, 0); 899 } 900 901 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); 902 if (ret) { 903 dev_err(indio_dev->dev.parent, 904 "failed to set adc parent to clkin\n"); 905 return ret; 906 } 907 908 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate); 909 if (ret) { 910 dev_err(indio_dev->dev.parent, 911 "failed to set adc clock rate\n"); 912 return ret; 913 } 914 915 return 0; 916 } 917 918 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off) 919 { 920 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 921 const struct meson_sar_adc_param *param = priv->param; 922 u32 enable_mask; 923 924 if (param->bandgap_reg == MESON_SAR_ADC_REG11) 925 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN; 926 else 927 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN; 928 929 regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask, 930 on_off ? enable_mask : 0); 931 } 932 933 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) 934 { 935 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 936 int ret; 937 u32 regval; 938 939 ret = meson_sar_adc_lock(indio_dev); 940 if (ret) 941 goto err_lock; 942 943 ret = regulator_enable(priv->vref); 944 if (ret < 0) { 945 dev_err(indio_dev->dev.parent, 946 "failed to enable vref regulator\n"); 947 goto err_vref; 948 } 949 950 ret = clk_prepare_enable(priv->core_clk); 951 if (ret) { 952 dev_err(indio_dev->dev.parent, "failed to enable core clk\n"); 953 goto err_core_clk; 954 } 955 956 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1); 957 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 958 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); 959 960 meson_sar_adc_set_bandgap(indio_dev, true); 961 962 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 963 MESON_SAR_ADC_REG3_ADC_EN, 964 MESON_SAR_ADC_REG3_ADC_EN); 965 966 udelay(5); 967 968 ret = clk_prepare_enable(priv->adc_clk); 969 if (ret) { 970 dev_err(indio_dev->dev.parent, "failed to enable adc clk\n"); 971 goto err_adc_clk; 972 } 973 974 meson_sar_adc_unlock(indio_dev); 975 976 return 0; 977 978 err_adc_clk: 979 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 980 MESON_SAR_ADC_REG3_ADC_EN, 0); 981 meson_sar_adc_set_bandgap(indio_dev, false); 982 clk_disable_unprepare(priv->core_clk); 983 err_core_clk: 984 regulator_disable(priv->vref); 985 err_vref: 986 meson_sar_adc_unlock(indio_dev); 987 err_lock: 988 return ret; 989 } 990 991 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev) 992 { 993 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 994 int ret; 995 996 ret = meson_sar_adc_lock(indio_dev); 997 if (ret) 998 return ret; 999 1000 clk_disable_unprepare(priv->adc_clk); 1001 1002 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 1003 MESON_SAR_ADC_REG3_ADC_EN, 0); 1004 1005 meson_sar_adc_set_bandgap(indio_dev, false); 1006 1007 clk_disable_unprepare(priv->core_clk); 1008 1009 regulator_disable(priv->vref); 1010 1011 meson_sar_adc_unlock(indio_dev); 1012 1013 return 0; 1014 } 1015 1016 static irqreturn_t meson_sar_adc_irq(int irq, void *data) 1017 { 1018 struct iio_dev *indio_dev = data; 1019 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1020 unsigned int cnt, threshold; 1021 u32 regval; 1022 1023 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 1024 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); 1025 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); 1026 1027 if (cnt < threshold) 1028 return IRQ_NONE; 1029 1030 complete(&priv->done); 1031 1032 return IRQ_HANDLED; 1033 } 1034 1035 static int meson_sar_adc_calib(struct iio_dev *indio_dev) 1036 { 1037 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1038 int ret, nominal0, nominal1, value0, value1; 1039 1040 /* use points 25% and 75% for calibration */ 1041 nominal0 = (1 << priv->param->resolution) / 4; 1042 nominal1 = (1 << priv->param->resolution) * 3 / 4; 1043 1044 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4); 1045 usleep_range(10, 20); 1046 ret = meson_sar_adc_get_sample(indio_dev, 1047 &indio_dev->channels[7], 1048 MEAN_AVERAGING, EIGHT_SAMPLES, &value0); 1049 if (ret < 0) 1050 goto out; 1051 1052 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4); 1053 usleep_range(10, 20); 1054 ret = meson_sar_adc_get_sample(indio_dev, 1055 &indio_dev->channels[7], 1056 MEAN_AVERAGING, EIGHT_SAMPLES, &value1); 1057 if (ret < 0) 1058 goto out; 1059 1060 if (value1 <= value0) { 1061 ret = -EINVAL; 1062 goto out; 1063 } 1064 1065 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION, 1066 value1 - value0); 1067 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, 1068 MILLION); 1069 ret = 0; 1070 out: 1071 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT); 1072 1073 return ret; 1074 } 1075 1076 static const struct iio_info meson_sar_adc_iio_info = { 1077 .read_raw = meson_sar_adc_iio_info_read_raw, 1078 }; 1079 1080 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = { 1081 .has_bl30_integration = false, 1082 .clock_rate = 1150000, 1083 .bandgap_reg = MESON_SAR_ADC_DELTA_10, 1084 .regmap_config = &meson_sar_adc_regmap_config_meson8, 1085 .resolution = 10, 1086 .temperature_trimming_bits = 4, 1087 .temperature_multiplier = 18 * 10000, 1088 .temperature_divider = 1024 * 10 * 85, 1089 }; 1090 1091 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = { 1092 .has_bl30_integration = false, 1093 .clock_rate = 1150000, 1094 .bandgap_reg = MESON_SAR_ADC_DELTA_10, 1095 .regmap_config = &meson_sar_adc_regmap_config_meson8, 1096 .resolution = 10, 1097 .temperature_trimming_bits = 5, 1098 .temperature_multiplier = 10, 1099 .temperature_divider = 32, 1100 }; 1101 1102 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = { 1103 .has_bl30_integration = true, 1104 .clock_rate = 1200000, 1105 .bandgap_reg = MESON_SAR_ADC_REG11, 1106 .regmap_config = &meson_sar_adc_regmap_config_gxbb, 1107 .resolution = 10, 1108 }; 1109 1110 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = { 1111 .has_bl30_integration = true, 1112 .clock_rate = 1200000, 1113 .bandgap_reg = MESON_SAR_ADC_REG11, 1114 .regmap_config = &meson_sar_adc_regmap_config_gxbb, 1115 .resolution = 12, 1116 }; 1117 1118 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { 1119 .param = &meson_sar_adc_meson8_param, 1120 .name = "meson-meson8-saradc", 1121 }; 1122 1123 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = { 1124 .param = &meson_sar_adc_meson8b_param, 1125 .name = "meson-meson8b-saradc", 1126 }; 1127 1128 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = { 1129 .param = &meson_sar_adc_meson8b_param, 1130 .name = "meson-meson8m2-saradc", 1131 }; 1132 1133 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = { 1134 .param = &meson_sar_adc_gxbb_param, 1135 .name = "meson-gxbb-saradc", 1136 }; 1137 1138 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = { 1139 .param = &meson_sar_adc_gxl_param, 1140 .name = "meson-gxl-saradc", 1141 }; 1142 1143 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = { 1144 .param = &meson_sar_adc_gxl_param, 1145 .name = "meson-gxm-saradc", 1146 }; 1147 1148 static const struct meson_sar_adc_data meson_sar_adc_axg_data = { 1149 .param = &meson_sar_adc_gxl_param, 1150 .name = "meson-axg-saradc", 1151 }; 1152 1153 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = { 1154 .param = &meson_sar_adc_gxl_param, 1155 .name = "meson-g12a-saradc", 1156 }; 1157 1158 static const struct of_device_id meson_sar_adc_of_match[] = { 1159 { 1160 .compatible = "amlogic,meson8-saradc", 1161 .data = &meson_sar_adc_meson8_data, 1162 }, 1163 { 1164 .compatible = "amlogic,meson8b-saradc", 1165 .data = &meson_sar_adc_meson8b_data, 1166 }, 1167 { 1168 .compatible = "amlogic,meson8m2-saradc", 1169 .data = &meson_sar_adc_meson8m2_data, 1170 }, 1171 { 1172 .compatible = "amlogic,meson-gxbb-saradc", 1173 .data = &meson_sar_adc_gxbb_data, 1174 }, { 1175 .compatible = "amlogic,meson-gxl-saradc", 1176 .data = &meson_sar_adc_gxl_data, 1177 }, { 1178 .compatible = "amlogic,meson-gxm-saradc", 1179 .data = &meson_sar_adc_gxm_data, 1180 }, { 1181 .compatible = "amlogic,meson-axg-saradc", 1182 .data = &meson_sar_adc_axg_data, 1183 }, { 1184 .compatible = "amlogic,meson-g12a-saradc", 1185 .data = &meson_sar_adc_g12a_data, 1186 }, 1187 {}, 1188 }; 1189 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match); 1190 1191 static int meson_sar_adc_probe(struct platform_device *pdev) 1192 { 1193 const struct meson_sar_adc_data *match_data; 1194 struct meson_sar_adc_priv *priv; 1195 struct iio_dev *indio_dev; 1196 struct resource *res; 1197 void __iomem *base; 1198 int irq, ret; 1199 1200 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); 1201 if (!indio_dev) { 1202 dev_err(&pdev->dev, "failed allocating iio device\n"); 1203 return -ENOMEM; 1204 } 1205 1206 priv = iio_priv(indio_dev); 1207 init_completion(&priv->done); 1208 1209 match_data = of_device_get_match_data(&pdev->dev); 1210 if (!match_data) { 1211 dev_err(&pdev->dev, "failed to get match data\n"); 1212 return -ENODEV; 1213 } 1214 1215 priv->param = match_data->param; 1216 1217 indio_dev->name = match_data->name; 1218 indio_dev->dev.parent = &pdev->dev; 1219 indio_dev->dev.of_node = pdev->dev.of_node; 1220 indio_dev->modes = INDIO_DIRECT_MODE; 1221 indio_dev->info = &meson_sar_adc_iio_info; 1222 1223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1224 base = devm_ioremap_resource(&pdev->dev, res); 1225 if (IS_ERR(base)) 1226 return PTR_ERR(base); 1227 1228 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1229 if (!irq) 1230 return -EINVAL; 1231 1232 ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED, 1233 dev_name(&pdev->dev), indio_dev); 1234 if (ret) 1235 return ret; 1236 1237 priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1238 priv->param->regmap_config); 1239 if (IS_ERR(priv->regmap)) 1240 return PTR_ERR(priv->regmap); 1241 1242 priv->clkin = devm_clk_get(&pdev->dev, "clkin"); 1243 if (IS_ERR(priv->clkin)) { 1244 dev_err(&pdev->dev, "failed to get clkin\n"); 1245 return PTR_ERR(priv->clkin); 1246 } 1247 1248 priv->core_clk = devm_clk_get(&pdev->dev, "core"); 1249 if (IS_ERR(priv->core_clk)) { 1250 dev_err(&pdev->dev, "failed to get core clk\n"); 1251 return PTR_ERR(priv->core_clk); 1252 } 1253 1254 priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk"); 1255 if (IS_ERR(priv->adc_clk)) { 1256 if (PTR_ERR(priv->adc_clk) == -ENOENT) { 1257 priv->adc_clk = NULL; 1258 } else { 1259 dev_err(&pdev->dev, "failed to get adc clk\n"); 1260 return PTR_ERR(priv->adc_clk); 1261 } 1262 } 1263 1264 priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel"); 1265 if (IS_ERR(priv->adc_sel_clk)) { 1266 if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) { 1267 priv->adc_sel_clk = NULL; 1268 } else { 1269 dev_err(&pdev->dev, "failed to get adc_sel clk\n"); 1270 return PTR_ERR(priv->adc_sel_clk); 1271 } 1272 } 1273 1274 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ 1275 if (!priv->adc_clk) { 1276 ret = meson_sar_adc_clk_init(indio_dev, base); 1277 if (ret) 1278 return ret; 1279 } 1280 1281 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 1282 if (IS_ERR(priv->vref)) { 1283 dev_err(&pdev->dev, "failed to get vref regulator\n"); 1284 return PTR_ERR(priv->vref); 1285 } 1286 1287 priv->calibscale = MILLION; 1288 1289 if (priv->param->temperature_trimming_bits) { 1290 ret = meson_sar_adc_temp_sensor_init(indio_dev); 1291 if (ret) 1292 return ret; 1293 } 1294 1295 if (priv->temperature_sensor_calibrated) { 1296 indio_dev->channels = meson_sar_adc_and_temp_iio_channels; 1297 indio_dev->num_channels = 1298 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels); 1299 } else { 1300 indio_dev->channels = meson_sar_adc_iio_channels; 1301 indio_dev->num_channels = 1302 ARRAY_SIZE(meson_sar_adc_iio_channels); 1303 } 1304 1305 ret = meson_sar_adc_init(indio_dev); 1306 if (ret) 1307 goto err; 1308 1309 ret = meson_sar_adc_hw_enable(indio_dev); 1310 if (ret) 1311 goto err; 1312 1313 ret = meson_sar_adc_calib(indio_dev); 1314 if (ret) 1315 dev_warn(&pdev->dev, "calibration failed\n"); 1316 1317 platform_set_drvdata(pdev, indio_dev); 1318 1319 ret = iio_device_register(indio_dev); 1320 if (ret) 1321 goto err_hw; 1322 1323 return 0; 1324 1325 err_hw: 1326 meson_sar_adc_hw_disable(indio_dev); 1327 err: 1328 return ret; 1329 } 1330 1331 static int meson_sar_adc_remove(struct platform_device *pdev) 1332 { 1333 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1334 1335 iio_device_unregister(indio_dev); 1336 1337 return meson_sar_adc_hw_disable(indio_dev); 1338 } 1339 1340 static int __maybe_unused meson_sar_adc_suspend(struct device *dev) 1341 { 1342 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1343 1344 return meson_sar_adc_hw_disable(indio_dev); 1345 } 1346 1347 static int __maybe_unused meson_sar_adc_resume(struct device *dev) 1348 { 1349 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1350 1351 return meson_sar_adc_hw_enable(indio_dev); 1352 } 1353 1354 static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops, 1355 meson_sar_adc_suspend, meson_sar_adc_resume); 1356 1357 static struct platform_driver meson_sar_adc_driver = { 1358 .probe = meson_sar_adc_probe, 1359 .remove = meson_sar_adc_remove, 1360 .driver = { 1361 .name = "meson-saradc", 1362 .of_match_table = meson_sar_adc_of_match, 1363 .pm = &meson_sar_adc_pm_ops, 1364 }, 1365 }; 1366 1367 module_platform_driver(meson_sar_adc_driver); 1368 1369 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 1370 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver"); 1371 MODULE_LICENSE("GPL v2"); 1372