1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Microchip MCP3911, Two-channel Analog Front End 4 * 5 * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com> 6 * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se> 7 */ 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/property.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/spi/spi.h> 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/triggered_buffer.h> 22 #include <linux/iio/trigger_consumer.h> 23 #include <linux/iio/trigger.h> 24 25 #include <asm/unaligned.h> 26 27 #define MCP3911_REG_CHANNEL0 0x00 28 #define MCP3911_REG_CHANNEL1 0x03 29 #define MCP3911_REG_MOD 0x06 30 #define MCP3911_REG_PHASE 0x07 31 #define MCP3911_REG_GAIN 0x09 32 33 #define MCP3911_REG_STATUSCOM 0x0a 34 #define MCP3911_STATUSCOM_DRHIZ BIT(12) 35 #define MCP3911_STATUSCOM_READ GENMASK(7, 6) 36 #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4) 37 #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3) 38 #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2) 39 #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1) 40 41 #define MCP3911_REG_CONFIG 0x0c 42 #define MCP3911_CONFIG_CLKEXT BIT(1) 43 #define MCP3911_CONFIG_VREFEXT BIT(2) 44 #define MCP3911_CONFIG_OSR GENMASK(13, 11) 45 46 #define MCP3911_REG_OFFCAL_CH0 0x0e 47 #define MCP3911_REG_GAINCAL_CH0 0x11 48 #define MCP3911_REG_OFFCAL_CH1 0x14 49 #define MCP3911_REG_GAINCAL_CH1 0x17 50 #define MCP3911_REG_VREFCAL 0x1a 51 52 #define MCP3911_CHANNEL(x) (MCP3911_REG_CHANNEL0 + x * 3) 53 #define MCP3911_OFFCAL(x) (MCP3911_REG_OFFCAL_CH0 + x * 6) 54 55 /* Internal voltage reference in mV */ 56 #define MCP3911_INT_VREF_MV 1200 57 58 #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 5) | (1 << 0)) & 0xff) 59 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 5) | (0 << 0)) & 0xff) 60 61 #define MCP3911_NUM_CHANNELS 2 62 63 static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 }; 64 65 struct mcp3911 { 66 struct spi_device *spi; 67 struct mutex lock; 68 struct regulator *vref; 69 struct clk *clki; 70 u32 dev_addr; 71 struct iio_trigger *trig; 72 struct { 73 u32 channels[MCP3911_NUM_CHANNELS]; 74 s64 ts __aligned(8); 75 } scan; 76 77 u8 tx_buf __aligned(IIO_DMA_MINALIGN); 78 u8 rx_buf[MCP3911_NUM_CHANNELS * 3]; 79 }; 80 81 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) 82 { 83 int ret; 84 85 reg = MCP3911_REG_READ(reg, adc->dev_addr); 86 ret = spi_write_then_read(adc->spi, ®, 1, val, len); 87 if (ret < 0) 88 return ret; 89 90 be32_to_cpus(val); 91 *val >>= ((4 - len) * 8); 92 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%x\n", *val, 93 reg >> 1); 94 return ret; 95 } 96 97 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) 98 { 99 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); 100 101 val <<= (3 - len) * 8; 102 cpu_to_be32s(&val); 103 val |= MCP3911_REG_WRITE(reg, adc->dev_addr); 104 105 return spi_write(adc->spi, &val, len + 1); 106 } 107 108 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, 109 u32 val, u8 len) 110 { 111 u32 tmp; 112 int ret; 113 114 ret = mcp3911_read(adc, reg, &tmp, len); 115 if (ret) 116 return ret; 117 118 val &= mask; 119 val |= tmp & ~mask; 120 return mcp3911_write(adc, reg, val, len); 121 } 122 123 static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev, 124 struct iio_chan_spec const *chan, 125 long mask) 126 { 127 switch (mask) { 128 case IIO_CHAN_INFO_SCALE: 129 return IIO_VAL_INT_PLUS_NANO; 130 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 131 return IIO_VAL_INT; 132 default: 133 return IIO_VAL_INT_PLUS_NANO; 134 } 135 } 136 137 static int mcp3911_read_avail(struct iio_dev *indio_dev, 138 struct iio_chan_spec const *chan, 139 const int **vals, int *type, int *length, 140 long info) 141 { 142 switch (info) { 143 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 144 *type = IIO_VAL_INT; 145 *vals = mcp3911_osr_table; 146 *length = ARRAY_SIZE(mcp3911_osr_table); 147 return IIO_AVAIL_LIST; 148 default: 149 return -EINVAL; 150 } 151 } 152 153 static int mcp3911_read_raw(struct iio_dev *indio_dev, 154 struct iio_chan_spec const *channel, int *val, 155 int *val2, long mask) 156 { 157 struct mcp3911 *adc = iio_priv(indio_dev); 158 int ret = -EINVAL; 159 160 mutex_lock(&adc->lock); 161 switch (mask) { 162 case IIO_CHAN_INFO_RAW: 163 ret = mcp3911_read(adc, 164 MCP3911_CHANNEL(channel->channel), val, 3); 165 if (ret) 166 goto out; 167 168 *val = sign_extend32(*val, 23); 169 170 ret = IIO_VAL_INT; 171 break; 172 173 case IIO_CHAN_INFO_OFFSET: 174 ret = mcp3911_read(adc, 175 MCP3911_OFFCAL(channel->channel), val, 3); 176 if (ret) 177 goto out; 178 179 ret = IIO_VAL_INT; 180 break; 181 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 182 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); 183 if (ret) 184 goto out; 185 186 *val = FIELD_GET(MCP3911_CONFIG_OSR, *val); 187 *val = 32 << *val; 188 ret = IIO_VAL_INT; 189 break; 190 191 case IIO_CHAN_INFO_SCALE: 192 if (adc->vref) { 193 ret = regulator_get_voltage(adc->vref); 194 if (ret < 0) { 195 dev_err(indio_dev->dev.parent, 196 "failed to get vref voltage: %d\n", 197 ret); 198 goto out; 199 } 200 201 *val = ret / 1000; 202 } else { 203 *val = MCP3911_INT_VREF_MV; 204 } 205 206 /* 207 * For 24bit Conversion 208 * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5 209 * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5) 210 */ 211 212 /* val2 = (2^23 * 1.5) */ 213 *val2 = 12582912; 214 ret = IIO_VAL_FRACTIONAL; 215 break; 216 } 217 218 out: 219 mutex_unlock(&adc->lock); 220 return ret; 221 } 222 223 static int mcp3911_write_raw(struct iio_dev *indio_dev, 224 struct iio_chan_spec const *channel, int val, 225 int val2, long mask) 226 { 227 struct mcp3911 *adc = iio_priv(indio_dev); 228 int ret = -EINVAL; 229 230 mutex_lock(&adc->lock); 231 switch (mask) { 232 case IIO_CHAN_INFO_OFFSET: 233 if (val2 != 0) { 234 ret = -EINVAL; 235 goto out; 236 } 237 238 /* Write offset */ 239 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val, 240 3); 241 if (ret) 242 goto out; 243 244 /* Enable offset*/ 245 ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, 246 MCP3911_STATUSCOM_EN_OFFCAL, 247 MCP3911_STATUSCOM_EN_OFFCAL, 2); 248 break; 249 250 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 251 for (int i = 0; i < sizeof(mcp3911_osr_table); i++) { 252 if (val == mcp3911_osr_table[i]) { 253 val = FIELD_PREP(MCP3911_CONFIG_OSR, i); 254 ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR, 255 val, 2); 256 break; 257 } 258 } 259 break; 260 } 261 262 out: 263 mutex_unlock(&adc->lock); 264 return ret; 265 } 266 267 #define MCP3911_CHAN(idx) { \ 268 .type = IIO_VOLTAGE, \ 269 .indexed = 1, \ 270 .channel = idx, \ 271 .scan_index = idx, \ 272 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 273 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 274 BIT(IIO_CHAN_INFO_OFFSET) | \ 275 BIT(IIO_CHAN_INFO_SCALE), \ 276 .info_mask_shared_by_type_available = \ 277 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 278 .scan_type = { \ 279 .sign = 's', \ 280 .realbits = 24, \ 281 .storagebits = 32, \ 282 .endianness = IIO_BE, \ 283 }, \ 284 } 285 286 static const struct iio_chan_spec mcp3911_channels[] = { 287 MCP3911_CHAN(0), 288 MCP3911_CHAN(1), 289 IIO_CHAN_SOFT_TIMESTAMP(2), 290 }; 291 292 static irqreturn_t mcp3911_trigger_handler(int irq, void *p) 293 { 294 struct iio_poll_func *pf = p; 295 struct iio_dev *indio_dev = pf->indio_dev; 296 struct mcp3911 *adc = iio_priv(indio_dev); 297 struct spi_transfer xfer[] = { 298 { 299 .tx_buf = &adc->tx_buf, 300 .len = 1, 301 }, { 302 .rx_buf = adc->rx_buf, 303 .len = sizeof(adc->rx_buf), 304 }, 305 }; 306 int scan_index; 307 int i = 0; 308 int ret; 309 310 mutex_lock(&adc->lock); 311 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr); 312 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer)); 313 if (ret < 0) { 314 dev_warn(&adc->spi->dev, 315 "failed to get conversion data\n"); 316 goto out; 317 } 318 319 for_each_set_bit(scan_index, indio_dev->active_scan_mask, indio_dev->masklength) { 320 const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index]; 321 322 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]); 323 i++; 324 } 325 iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan, 326 iio_get_time_ns(indio_dev)); 327 out: 328 mutex_unlock(&adc->lock); 329 iio_trigger_notify_done(indio_dev->trig); 330 331 return IRQ_HANDLED; 332 } 333 334 static const struct iio_info mcp3911_info = { 335 .read_raw = mcp3911_read_raw, 336 .write_raw = mcp3911_write_raw, 337 .read_avail = mcp3911_read_avail, 338 .write_raw_get_fmt = mcp3911_write_raw_get_fmt, 339 }; 340 341 static int mcp3911_config(struct mcp3911 *adc) 342 { 343 struct device *dev = &adc->spi->dev; 344 u32 regval; 345 int ret; 346 347 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); 348 349 /* 350 * Fallback to "device-addr" due to historical mismatch between 351 * dt-bindings and implementation 352 */ 353 if (ret) 354 device_property_read_u32(dev, "device-addr", &adc->dev_addr); 355 if (adc->dev_addr > 3) { 356 dev_err(&adc->spi->dev, 357 "invalid device address (%i). Must be in range 0-3.\n", 358 adc->dev_addr); 359 return -EINVAL; 360 } 361 dev_dbg(&adc->spi->dev, "use device address %i\n", adc->dev_addr); 362 363 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2); 364 if (ret) 365 return ret; 366 367 regval &= ~MCP3911_CONFIG_VREFEXT; 368 if (adc->vref) { 369 dev_dbg(&adc->spi->dev, "use external voltage reference\n"); 370 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1); 371 } else { 372 dev_dbg(&adc->spi->dev, 373 "use internal voltage reference (1.2V)\n"); 374 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0); 375 } 376 377 regval &= ~MCP3911_CONFIG_CLKEXT; 378 if (adc->clki) { 379 dev_dbg(&adc->spi->dev, "use external clock as clocksource\n"); 380 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1); 381 } else { 382 dev_dbg(&adc->spi->dev, 383 "use crystal oscillator as clocksource\n"); 384 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0); 385 } 386 387 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2); 388 if (ret) 389 return ret; 390 391 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2); 392 if (ret) 393 return ret; 394 395 /* Address counter incremented, cycle through register types */ 396 regval &= ~MCP3911_STATUSCOM_READ; 397 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02); 398 399 return mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); 400 } 401 402 static void mcp3911_cleanup_regulator(void *vref) 403 { 404 regulator_disable(vref); 405 } 406 407 static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable) 408 { 409 struct mcp3911 *adc = iio_trigger_get_drvdata(trig); 410 411 if (enable) 412 enable_irq(adc->spi->irq); 413 else 414 disable_irq(adc->spi->irq); 415 416 return 0; 417 } 418 419 static const struct iio_trigger_ops mcp3911_trigger_ops = { 420 .validate_device = iio_trigger_validate_own_device, 421 .set_trigger_state = mcp3911_set_trigger_state, 422 }; 423 424 static int mcp3911_probe(struct spi_device *spi) 425 { 426 struct iio_dev *indio_dev; 427 struct mcp3911 *adc; 428 int ret; 429 430 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); 431 if (!indio_dev) 432 return -ENOMEM; 433 434 adc = iio_priv(indio_dev); 435 adc->spi = spi; 436 437 adc->vref = devm_regulator_get_optional(&adc->spi->dev, "vref"); 438 if (IS_ERR(adc->vref)) { 439 if (PTR_ERR(adc->vref) == -ENODEV) { 440 adc->vref = NULL; 441 } else { 442 dev_err(&adc->spi->dev, 443 "failed to get regulator (%ld)\n", 444 PTR_ERR(adc->vref)); 445 return PTR_ERR(adc->vref); 446 } 447 448 } else { 449 ret = regulator_enable(adc->vref); 450 if (ret) 451 return ret; 452 453 ret = devm_add_action_or_reset(&spi->dev, 454 mcp3911_cleanup_regulator, adc->vref); 455 if (ret) 456 return ret; 457 } 458 459 adc->clki = devm_clk_get_enabled(&adc->spi->dev, NULL); 460 if (IS_ERR(adc->clki)) { 461 if (PTR_ERR(adc->clki) == -ENOENT) { 462 adc->clki = NULL; 463 } else { 464 dev_err(&adc->spi->dev, 465 "failed to get adc clk (%ld)\n", 466 PTR_ERR(adc->clki)); 467 return PTR_ERR(adc->clki); 468 } 469 } 470 471 ret = mcp3911_config(adc); 472 if (ret) 473 return ret; 474 475 if (device_property_read_bool(&adc->spi->dev, "microchip,data-ready-hiz")) 476 ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ, 477 0, 2); 478 else 479 ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ, 480 MCP3911_STATUSCOM_DRHIZ, 2); 481 if (ret) 482 return ret; 483 484 indio_dev->name = spi_get_device_id(spi)->name; 485 indio_dev->modes = INDIO_DIRECT_MODE; 486 indio_dev->info = &mcp3911_info; 487 spi_set_drvdata(spi, indio_dev); 488 489 indio_dev->channels = mcp3911_channels; 490 indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels); 491 492 mutex_init(&adc->lock); 493 494 if (spi->irq > 0) { 495 adc->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", 496 indio_dev->name, 497 iio_device_id(indio_dev)); 498 if (!adc->trig) 499 return PTR_ERR(adc->trig); 500 501 adc->trig->ops = &mcp3911_trigger_ops; 502 iio_trigger_set_drvdata(adc->trig, adc); 503 ret = devm_iio_trigger_register(&spi->dev, adc->trig); 504 if (ret) 505 return ret; 506 507 /* 508 * The device generates interrupts as long as it is powered up. 509 * Some platforms might not allow the option to power it down so 510 * don't enable the interrupt to avoid extra load on the system. 511 */ 512 ret = devm_request_irq(&spi->dev, spi->irq, 513 &iio_trigger_generic_data_rdy_poll, IRQF_NO_AUTOEN | IRQF_ONESHOT, 514 indio_dev->name, adc->trig); 515 if (ret) 516 return ret; 517 } 518 519 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 520 NULL, 521 mcp3911_trigger_handler, NULL); 522 if (ret) 523 return ret; 524 525 return devm_iio_device_register(&adc->spi->dev, indio_dev); 526 } 527 528 static const struct of_device_id mcp3911_dt_ids[] = { 529 { .compatible = "microchip,mcp3911" }, 530 { } 531 }; 532 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids); 533 534 static const struct spi_device_id mcp3911_id[] = { 535 { "mcp3911", 0 }, 536 { } 537 }; 538 MODULE_DEVICE_TABLE(spi, mcp3911_id); 539 540 static struct spi_driver mcp3911_driver = { 541 .driver = { 542 .name = "mcp3911", 543 .of_match_table = mcp3911_dt_ids, 544 }, 545 .probe = mcp3911_probe, 546 .id_table = mcp3911_id, 547 }; 548 module_spi_driver(mcp3911_driver); 549 550 MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>"); 551 MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>"); 552 MODULE_DESCRIPTION("Microchip Technology MCP3911"); 553 MODULE_LICENSE("GPL v2"); 554