1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Microchip MCP3911, Two-channel Analog Front End 4 * 5 * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com> 6 * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se> 7 */ 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/iio/iio.h> 12 #include <linux/module.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/property.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/spi/spi.h> 17 18 #define MCP3911_REG_CHANNEL0 0x00 19 #define MCP3911_REG_CHANNEL1 0x03 20 #define MCP3911_REG_MOD 0x06 21 #define MCP3911_REG_PHASE 0x07 22 #define MCP3911_REG_GAIN 0x09 23 24 #define MCP3911_REG_STATUSCOM 0x0a 25 #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4) 26 #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3) 27 #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2) 28 #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1) 29 30 #define MCP3911_REG_CONFIG 0x0c 31 #define MCP3911_CONFIG_CLKEXT BIT(1) 32 #define MCP3911_CONFIG_VREFEXT BIT(2) 33 34 #define MCP3911_REG_OFFCAL_CH0 0x0e 35 #define MCP3911_REG_GAINCAL_CH0 0x11 36 #define MCP3911_REG_OFFCAL_CH1 0x14 37 #define MCP3911_REG_GAINCAL_CH1 0x17 38 #define MCP3911_REG_VREFCAL 0x1a 39 40 #define MCP3911_CHANNEL(x) (MCP3911_REG_CHANNEL0 + x * 3) 41 #define MCP3911_OFFCAL(x) (MCP3911_REG_OFFCAL_CH0 + x * 6) 42 43 /* Internal voltage reference in mV */ 44 #define MCP3911_INT_VREF_MV 1200 45 46 #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 5) | (1 << 0)) & 0xff) 47 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 5) | (0 << 0)) & 0xff) 48 49 #define MCP3911_NUM_CHANNELS 2 50 51 struct mcp3911 { 52 struct spi_device *spi; 53 struct mutex lock; 54 struct regulator *vref; 55 struct clk *clki; 56 u32 dev_addr; 57 }; 58 59 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) 60 { 61 int ret; 62 63 reg = MCP3911_REG_READ(reg, adc->dev_addr); 64 ret = spi_write_then_read(adc->spi, ®, 1, val, len); 65 if (ret < 0) 66 return ret; 67 68 be32_to_cpus(val); 69 *val >>= ((4 - len) * 8); 70 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%x\n", *val, 71 reg >> 1); 72 return ret; 73 } 74 75 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) 76 { 77 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); 78 79 val <<= (3 - len) * 8; 80 cpu_to_be32s(&val); 81 val |= MCP3911_REG_WRITE(reg, adc->dev_addr); 82 83 return spi_write(adc->spi, &val, len + 1); 84 } 85 86 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, 87 u32 val, u8 len) 88 { 89 u32 tmp; 90 int ret; 91 92 ret = mcp3911_read(adc, reg, &tmp, len); 93 if (ret) 94 return ret; 95 96 val &= mask; 97 val |= tmp & ~mask; 98 return mcp3911_write(adc, reg, val, len); 99 } 100 101 static int mcp3911_read_raw(struct iio_dev *indio_dev, 102 struct iio_chan_spec const *channel, int *val, 103 int *val2, long mask) 104 { 105 struct mcp3911 *adc = iio_priv(indio_dev); 106 int ret = -EINVAL; 107 108 mutex_lock(&adc->lock); 109 switch (mask) { 110 case IIO_CHAN_INFO_RAW: 111 ret = mcp3911_read(adc, 112 MCP3911_CHANNEL(channel->channel), val, 3); 113 if (ret) 114 goto out; 115 116 *val = sign_extend32(*val, 23); 117 118 ret = IIO_VAL_INT; 119 break; 120 121 case IIO_CHAN_INFO_OFFSET: 122 ret = mcp3911_read(adc, 123 MCP3911_OFFCAL(channel->channel), val, 3); 124 if (ret) 125 goto out; 126 127 ret = IIO_VAL_INT; 128 break; 129 130 case IIO_CHAN_INFO_SCALE: 131 if (adc->vref) { 132 ret = regulator_get_voltage(adc->vref); 133 if (ret < 0) { 134 dev_err(indio_dev->dev.parent, 135 "failed to get vref voltage: %d\n", 136 ret); 137 goto out; 138 } 139 140 *val = ret / 1000; 141 } else { 142 *val = MCP3911_INT_VREF_MV; 143 } 144 145 /* 146 * For 24bit Conversion 147 * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5 148 * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5) 149 */ 150 151 /* val2 = (2^23 * 1.5) */ 152 *val2 = 12582912; 153 ret = IIO_VAL_FRACTIONAL; 154 break; 155 } 156 157 out: 158 mutex_unlock(&adc->lock); 159 return ret; 160 } 161 162 static int mcp3911_write_raw(struct iio_dev *indio_dev, 163 struct iio_chan_spec const *channel, int val, 164 int val2, long mask) 165 { 166 struct mcp3911 *adc = iio_priv(indio_dev); 167 int ret = -EINVAL; 168 169 mutex_lock(&adc->lock); 170 switch (mask) { 171 case IIO_CHAN_INFO_OFFSET: 172 if (val2 != 0) { 173 ret = -EINVAL; 174 goto out; 175 } 176 177 /* Write offset */ 178 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val, 179 3); 180 if (ret) 181 goto out; 182 183 /* Enable offset*/ 184 ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, 185 MCP3911_STATUSCOM_EN_OFFCAL, 186 MCP3911_STATUSCOM_EN_OFFCAL, 2); 187 break; 188 } 189 190 out: 191 mutex_unlock(&adc->lock); 192 return ret; 193 } 194 195 #define MCP3911_CHAN(idx) { \ 196 .type = IIO_VOLTAGE, \ 197 .indexed = 1, \ 198 .channel = idx, \ 199 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 200 BIT(IIO_CHAN_INFO_OFFSET) | \ 201 BIT(IIO_CHAN_INFO_SCALE), \ 202 } 203 204 static const struct iio_chan_spec mcp3911_channels[] = { 205 MCP3911_CHAN(0), 206 MCP3911_CHAN(1), 207 }; 208 209 static const struct iio_info mcp3911_info = { 210 .read_raw = mcp3911_read_raw, 211 .write_raw = mcp3911_write_raw, 212 }; 213 214 static int mcp3911_config(struct mcp3911 *adc) 215 { 216 struct device *dev = &adc->spi->dev; 217 u32 configreg; 218 int ret; 219 220 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); 221 222 /* 223 * Fallback to "device-addr" due to historical mismatch between 224 * dt-bindings and implementation 225 */ 226 if (ret) 227 device_property_read_u32(dev, "device-addr", &adc->dev_addr); 228 if (adc->dev_addr > 3) { 229 dev_err(&adc->spi->dev, 230 "invalid device address (%i). Must be in range 0-3.\n", 231 adc->dev_addr); 232 return -EINVAL; 233 } 234 dev_dbg(&adc->spi->dev, "use device address %i\n", adc->dev_addr); 235 236 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, &configreg, 2); 237 if (ret) 238 return ret; 239 240 if (adc->vref) { 241 dev_dbg(&adc->spi->dev, "use external voltage reference\n"); 242 configreg |= MCP3911_CONFIG_VREFEXT; 243 } else { 244 dev_dbg(&adc->spi->dev, 245 "use internal voltage reference (1.2V)\n"); 246 configreg &= ~MCP3911_CONFIG_VREFEXT; 247 } 248 249 if (adc->clki) { 250 dev_dbg(&adc->spi->dev, "use external clock as clocksource\n"); 251 configreg |= MCP3911_CONFIG_CLKEXT; 252 } else { 253 dev_dbg(&adc->spi->dev, 254 "use crystal oscillator as clocksource\n"); 255 configreg &= ~MCP3911_CONFIG_CLKEXT; 256 } 257 258 return mcp3911_write(adc, MCP3911_REG_CONFIG, configreg, 2); 259 } 260 261 static int mcp3911_probe(struct spi_device *spi) 262 { 263 struct iio_dev *indio_dev; 264 struct mcp3911 *adc; 265 int ret; 266 267 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); 268 if (!indio_dev) 269 return -ENOMEM; 270 271 adc = iio_priv(indio_dev); 272 adc->spi = spi; 273 274 adc->vref = devm_regulator_get_optional(&adc->spi->dev, "vref"); 275 if (IS_ERR(adc->vref)) { 276 if (PTR_ERR(adc->vref) == -ENODEV) { 277 adc->vref = NULL; 278 } else { 279 dev_err(&adc->spi->dev, 280 "failed to get regulator (%ld)\n", 281 PTR_ERR(adc->vref)); 282 return PTR_ERR(adc->vref); 283 } 284 285 } else { 286 ret = regulator_enable(adc->vref); 287 if (ret) 288 return ret; 289 } 290 291 adc->clki = devm_clk_get(&adc->spi->dev, NULL); 292 if (IS_ERR(adc->clki)) { 293 if (PTR_ERR(adc->clki) == -ENOENT) { 294 adc->clki = NULL; 295 } else { 296 dev_err(&adc->spi->dev, 297 "failed to get adc clk (%ld)\n", 298 PTR_ERR(adc->clki)); 299 ret = PTR_ERR(adc->clki); 300 goto reg_disable; 301 } 302 } else { 303 ret = clk_prepare_enable(adc->clki); 304 if (ret < 0) { 305 dev_err(&adc->spi->dev, 306 "Failed to enable clki: %d\n", ret); 307 goto reg_disable; 308 } 309 } 310 311 ret = mcp3911_config(adc); 312 if (ret) 313 goto clk_disable; 314 315 indio_dev->name = spi_get_device_id(spi)->name; 316 indio_dev->modes = INDIO_DIRECT_MODE; 317 indio_dev->info = &mcp3911_info; 318 spi_set_drvdata(spi, indio_dev); 319 320 indio_dev->channels = mcp3911_channels; 321 indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels); 322 323 mutex_init(&adc->lock); 324 325 ret = iio_device_register(indio_dev); 326 if (ret) 327 goto clk_disable; 328 329 return ret; 330 331 clk_disable: 332 clk_disable_unprepare(adc->clki); 333 reg_disable: 334 if (adc->vref) 335 regulator_disable(adc->vref); 336 337 return ret; 338 } 339 340 static void mcp3911_remove(struct spi_device *spi) 341 { 342 struct iio_dev *indio_dev = spi_get_drvdata(spi); 343 struct mcp3911 *adc = iio_priv(indio_dev); 344 345 iio_device_unregister(indio_dev); 346 347 clk_disable_unprepare(adc->clki); 348 if (adc->vref) 349 regulator_disable(adc->vref); 350 } 351 352 static const struct of_device_id mcp3911_dt_ids[] = { 353 { .compatible = "microchip,mcp3911" }, 354 { } 355 }; 356 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids); 357 358 static const struct spi_device_id mcp3911_id[] = { 359 { "mcp3911", 0 }, 360 { } 361 }; 362 MODULE_DEVICE_TABLE(spi, mcp3911_id); 363 364 static struct spi_driver mcp3911_driver = { 365 .driver = { 366 .name = "mcp3911", 367 .of_match_table = mcp3911_dt_ids, 368 }, 369 .probe = mcp3911_probe, 370 .remove = mcp3911_remove, 371 .id_table = mcp3911_id, 372 }; 373 module_spi_driver(mcp3911_driver); 374 375 MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>"); 376 MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>"); 377 MODULE_DESCRIPTION("Microchip Technology MCP3911"); 378 MODULE_LICENSE("GPL v2"); 379