1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Oskar Andero <oskar.andero@gmail.com> 4 * Copyright (C) 2014 Rose Technology 5 * Allan Bendorff Jensen <abj@rosetechnology.dk> 6 * Soren Andersen <san@rosetechnology.dk> 7 * 8 * Driver for following ADC chips from Microchip Technology's: 9 * 10 Bit converter 10 * MCP3001 11 * MCP3002 12 * MCP3004 13 * MCP3008 14 * ------------ 15 * 12 bit converter 16 * MCP3201 17 * MCP3202 18 * MCP3204 19 * MCP3208 20 * ------------ 21 * 13 bit converter 22 * MCP3301 23 * ------------ 24 * 22 bit converter 25 * MCP3550 26 * MCP3551 27 * MCP3553 28 * 29 * Datasheet can be found here: 30 * https://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001 31 * https://ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf mcp3002 32 * https://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf mcp3004/08 33 * http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf mcp3201 34 * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202 35 * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08 36 * https://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301 37 * http://ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf mcp3550/1/3 38 */ 39 40 #include <linux/err.h> 41 #include <linux/delay.h> 42 #include <linux/spi/spi.h> 43 #include <linux/module.h> 44 #include <linux/mod_devicetable.h> 45 #include <linux/iio/iio.h> 46 #include <linux/regulator/consumer.h> 47 48 enum { 49 mcp3001, 50 mcp3002, 51 mcp3004, 52 mcp3008, 53 mcp3201, 54 mcp3202, 55 mcp3204, 56 mcp3208, 57 mcp3301, 58 mcp3550_50, 59 mcp3550_60, 60 mcp3551, 61 mcp3553, 62 }; 63 64 struct mcp320x_chip_info { 65 const struct iio_chan_spec *channels; 66 unsigned int num_channels; 67 unsigned int resolution; 68 unsigned int conv_time; /* usec */ 69 }; 70 71 /** 72 * struct mcp320x - Microchip SPI ADC instance 73 * @spi: SPI slave (parent of the IIO device) 74 * @msg: SPI message to select a channel and receive a value from the ADC 75 * @transfer: SPI transfers used by @msg 76 * @start_conv_msg: SPI message to start a conversion by briefly asserting CS 77 * @start_conv_transfer: SPI transfer used by @start_conv_msg 78 * @reg: regulator generating Vref 79 * @lock: protects read sequences 80 * @chip_info: ADC properties 81 * @tx_buf: buffer for @transfer[0] (not used on single-channel converters) 82 * @rx_buf: buffer for @transfer[1] 83 */ 84 struct mcp320x { 85 struct spi_device *spi; 86 struct spi_message msg; 87 struct spi_transfer transfer[2]; 88 struct spi_message start_conv_msg; 89 struct spi_transfer start_conv_transfer; 90 91 struct regulator *reg; 92 struct mutex lock; 93 const struct mcp320x_chip_info *chip_info; 94 95 u8 tx_buf ____cacheline_aligned; 96 u8 rx_buf[4]; 97 }; 98 99 static int mcp320x_channel_to_tx_data(int device_index, 100 const unsigned int channel, bool differential) 101 { 102 int start_bit = 1; 103 104 switch (device_index) { 105 case mcp3002: 106 case mcp3202: 107 return ((start_bit << 4) | (!differential << 3) | 108 (channel << 2)); 109 case mcp3004: 110 case mcp3204: 111 case mcp3008: 112 case mcp3208: 113 return ((start_bit << 6) | (!differential << 5) | 114 (channel << 2)); 115 default: 116 return -EINVAL; 117 } 118 } 119 120 static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel, 121 bool differential, int device_index, int *val) 122 { 123 int ret; 124 125 if (adc->chip_info->conv_time) { 126 ret = spi_sync(adc->spi, &adc->start_conv_msg); 127 if (ret < 0) 128 return ret; 129 130 usleep_range(adc->chip_info->conv_time, 131 adc->chip_info->conv_time + 100); 132 } 133 134 memset(&adc->rx_buf, 0, sizeof(adc->rx_buf)); 135 if (adc->chip_info->num_channels > 1) 136 adc->tx_buf = mcp320x_channel_to_tx_data(device_index, channel, 137 differential); 138 139 ret = spi_sync(adc->spi, &adc->msg); 140 if (ret < 0) 141 return ret; 142 143 switch (device_index) { 144 case mcp3001: 145 *val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3); 146 return 0; 147 case mcp3002: 148 case mcp3004: 149 case mcp3008: 150 *val = (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6); 151 return 0; 152 case mcp3201: 153 *val = (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1); 154 return 0; 155 case mcp3202: 156 case mcp3204: 157 case mcp3208: 158 *val = (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4); 159 return 0; 160 case mcp3301: 161 *val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8 162 | adc->rx_buf[1], 12); 163 return 0; 164 case mcp3550_50: 165 case mcp3550_60: 166 case mcp3551: 167 case mcp3553: { 168 u32 raw = be32_to_cpup((__be32 *)adc->rx_buf); 169 170 if (!(adc->spi->mode & SPI_CPOL)) 171 raw <<= 1; /* strip Data Ready bit in SPI mode 0,0 */ 172 173 /* 174 * If the input is within -vref and vref, bit 21 is the sign. 175 * Up to 12% overrange or underrange are allowed, in which case 176 * bit 23 is the sign and bit 0 to 21 is the value. 177 */ 178 raw >>= 8; 179 if (raw & BIT(22) && raw & BIT(23)) 180 return -EIO; /* cannot have overrange AND underrange */ 181 else if (raw & BIT(22)) 182 raw &= ~BIT(22); /* overrange */ 183 else if (raw & BIT(23) || raw & BIT(21)) 184 raw |= GENMASK(31, 22); /* underrange or negative */ 185 186 *val = (s32)raw; 187 return 0; 188 } 189 default: 190 return -EINVAL; 191 } 192 } 193 194 static int mcp320x_read_raw(struct iio_dev *indio_dev, 195 struct iio_chan_spec const *channel, int *val, 196 int *val2, long mask) 197 { 198 struct mcp320x *adc = iio_priv(indio_dev); 199 int ret = -EINVAL; 200 int device_index = 0; 201 202 mutex_lock(&adc->lock); 203 204 device_index = spi_get_device_id(adc->spi)->driver_data; 205 206 switch (mask) { 207 case IIO_CHAN_INFO_RAW: 208 ret = mcp320x_adc_conversion(adc, channel->address, 209 channel->differential, device_index, val); 210 if (ret < 0) 211 goto out; 212 213 ret = IIO_VAL_INT; 214 break; 215 216 case IIO_CHAN_INFO_SCALE: 217 ret = regulator_get_voltage(adc->reg); 218 if (ret < 0) 219 goto out; 220 221 /* convert regulator output voltage to mV */ 222 *val = ret / 1000; 223 *val2 = adc->chip_info->resolution; 224 ret = IIO_VAL_FRACTIONAL_LOG2; 225 break; 226 } 227 228 out: 229 mutex_unlock(&adc->lock); 230 231 return ret; 232 } 233 234 #define MCP320X_VOLTAGE_CHANNEL(num) \ 235 { \ 236 .type = IIO_VOLTAGE, \ 237 .indexed = 1, \ 238 .channel = (num), \ 239 .address = (num), \ 240 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 241 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ 242 } 243 244 #define MCP320X_VOLTAGE_CHANNEL_DIFF(chan1, chan2) \ 245 { \ 246 .type = IIO_VOLTAGE, \ 247 .indexed = 1, \ 248 .channel = (chan1), \ 249 .channel2 = (chan2), \ 250 .address = (chan1), \ 251 .differential = 1, \ 252 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 253 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ 254 } 255 256 static const struct iio_chan_spec mcp3201_channels[] = { 257 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1), 258 }; 259 260 static const struct iio_chan_spec mcp3202_channels[] = { 261 MCP320X_VOLTAGE_CHANNEL(0), 262 MCP320X_VOLTAGE_CHANNEL(1), 263 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1), 264 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0), 265 }; 266 267 static const struct iio_chan_spec mcp3204_channels[] = { 268 MCP320X_VOLTAGE_CHANNEL(0), 269 MCP320X_VOLTAGE_CHANNEL(1), 270 MCP320X_VOLTAGE_CHANNEL(2), 271 MCP320X_VOLTAGE_CHANNEL(3), 272 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1), 273 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0), 274 MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3), 275 MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2), 276 }; 277 278 static const struct iio_chan_spec mcp3208_channels[] = { 279 MCP320X_VOLTAGE_CHANNEL(0), 280 MCP320X_VOLTAGE_CHANNEL(1), 281 MCP320X_VOLTAGE_CHANNEL(2), 282 MCP320X_VOLTAGE_CHANNEL(3), 283 MCP320X_VOLTAGE_CHANNEL(4), 284 MCP320X_VOLTAGE_CHANNEL(5), 285 MCP320X_VOLTAGE_CHANNEL(6), 286 MCP320X_VOLTAGE_CHANNEL(7), 287 MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1), 288 MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0), 289 MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3), 290 MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2), 291 MCP320X_VOLTAGE_CHANNEL_DIFF(4, 5), 292 MCP320X_VOLTAGE_CHANNEL_DIFF(5, 4), 293 MCP320X_VOLTAGE_CHANNEL_DIFF(6, 7), 294 MCP320X_VOLTAGE_CHANNEL_DIFF(7, 6), 295 }; 296 297 static const struct iio_info mcp320x_info = { 298 .read_raw = mcp320x_read_raw, 299 }; 300 301 static const struct mcp320x_chip_info mcp320x_chip_infos[] = { 302 [mcp3001] = { 303 .channels = mcp3201_channels, 304 .num_channels = ARRAY_SIZE(mcp3201_channels), 305 .resolution = 10 306 }, 307 [mcp3002] = { 308 .channels = mcp3202_channels, 309 .num_channels = ARRAY_SIZE(mcp3202_channels), 310 .resolution = 10 311 }, 312 [mcp3004] = { 313 .channels = mcp3204_channels, 314 .num_channels = ARRAY_SIZE(mcp3204_channels), 315 .resolution = 10 316 }, 317 [mcp3008] = { 318 .channels = mcp3208_channels, 319 .num_channels = ARRAY_SIZE(mcp3208_channels), 320 .resolution = 10 321 }, 322 [mcp3201] = { 323 .channels = mcp3201_channels, 324 .num_channels = ARRAY_SIZE(mcp3201_channels), 325 .resolution = 12 326 }, 327 [mcp3202] = { 328 .channels = mcp3202_channels, 329 .num_channels = ARRAY_SIZE(mcp3202_channels), 330 .resolution = 12 331 }, 332 [mcp3204] = { 333 .channels = mcp3204_channels, 334 .num_channels = ARRAY_SIZE(mcp3204_channels), 335 .resolution = 12 336 }, 337 [mcp3208] = { 338 .channels = mcp3208_channels, 339 .num_channels = ARRAY_SIZE(mcp3208_channels), 340 .resolution = 12 341 }, 342 [mcp3301] = { 343 .channels = mcp3201_channels, 344 .num_channels = ARRAY_SIZE(mcp3201_channels), 345 .resolution = 13 346 }, 347 [mcp3550_50] = { 348 .channels = mcp3201_channels, 349 .num_channels = ARRAY_SIZE(mcp3201_channels), 350 .resolution = 21, 351 /* 2% max deviation + 144 clock periods to exit shutdown */ 352 .conv_time = 80000 * 1.02 + 144000 / 102.4, 353 }, 354 [mcp3550_60] = { 355 .channels = mcp3201_channels, 356 .num_channels = ARRAY_SIZE(mcp3201_channels), 357 .resolution = 21, 358 .conv_time = 66670 * 1.02 + 144000 / 122.88, 359 }, 360 [mcp3551] = { 361 .channels = mcp3201_channels, 362 .num_channels = ARRAY_SIZE(mcp3201_channels), 363 .resolution = 21, 364 .conv_time = 73100 * 1.02 + 144000 / 112.64, 365 }, 366 [mcp3553] = { 367 .channels = mcp3201_channels, 368 .num_channels = ARRAY_SIZE(mcp3201_channels), 369 .resolution = 21, 370 .conv_time = 16670 * 1.02 + 144000 / 122.88, 371 }, 372 }; 373 374 static int mcp320x_probe(struct spi_device *spi) 375 { 376 struct iio_dev *indio_dev; 377 struct mcp320x *adc; 378 const struct mcp320x_chip_info *chip_info; 379 int ret, device_index; 380 381 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); 382 if (!indio_dev) 383 return -ENOMEM; 384 385 adc = iio_priv(indio_dev); 386 adc->spi = spi; 387 388 indio_dev->name = spi_get_device_id(spi)->name; 389 indio_dev->modes = INDIO_DIRECT_MODE; 390 indio_dev->info = &mcp320x_info; 391 spi_set_drvdata(spi, indio_dev); 392 393 device_index = spi_get_device_id(spi)->driver_data; 394 chip_info = &mcp320x_chip_infos[device_index]; 395 indio_dev->channels = chip_info->channels; 396 indio_dev->num_channels = chip_info->num_channels; 397 398 adc->chip_info = chip_info; 399 400 adc->transfer[0].tx_buf = &adc->tx_buf; 401 adc->transfer[0].len = sizeof(adc->tx_buf); 402 adc->transfer[1].rx_buf = adc->rx_buf; 403 adc->transfer[1].len = DIV_ROUND_UP(chip_info->resolution, 8); 404 405 if (chip_info->num_channels == 1) 406 /* single-channel converters are rx only (no MOSI pin) */ 407 spi_message_init_with_transfers(&adc->msg, 408 &adc->transfer[1], 1); 409 else 410 spi_message_init_with_transfers(&adc->msg, adc->transfer, 411 ARRAY_SIZE(adc->transfer)); 412 413 switch (device_index) { 414 case mcp3550_50: 415 case mcp3550_60: 416 case mcp3551: 417 case mcp3553: 418 /* rx len increases from 24 to 25 bit in SPI mode 0,0 */ 419 if (!(spi->mode & SPI_CPOL)) 420 adc->transfer[1].len++; 421 422 /* conversions are started by asserting CS pin for 8 usec */ 423 adc->start_conv_transfer.delay.value = 8; 424 adc->start_conv_transfer.delay.unit = SPI_DELAY_UNIT_USECS; 425 spi_message_init_with_transfers(&adc->start_conv_msg, 426 &adc->start_conv_transfer, 1); 427 428 /* 429 * If CS was previously kept low (continuous conversion mode) 430 * and then changed to high, the chip is in shutdown. 431 * Sometimes it fails to wake from shutdown and clocks out 432 * only 0xffffff. The magic sequence of performing two 433 * conversions without delay between them resets the chip 434 * and ensures all subsequent conversions succeed. 435 */ 436 mcp320x_adc_conversion(adc, 0, 1, device_index, &ret); 437 mcp320x_adc_conversion(adc, 0, 1, device_index, &ret); 438 } 439 440 adc->reg = devm_regulator_get(&spi->dev, "vref"); 441 if (IS_ERR(adc->reg)) 442 return PTR_ERR(adc->reg); 443 444 ret = regulator_enable(adc->reg); 445 if (ret < 0) 446 return ret; 447 448 mutex_init(&adc->lock); 449 450 ret = iio_device_register(indio_dev); 451 if (ret < 0) 452 goto reg_disable; 453 454 return 0; 455 456 reg_disable: 457 regulator_disable(adc->reg); 458 459 return ret; 460 } 461 462 static void mcp320x_remove(struct spi_device *spi) 463 { 464 struct iio_dev *indio_dev = spi_get_drvdata(spi); 465 struct mcp320x *adc = iio_priv(indio_dev); 466 467 iio_device_unregister(indio_dev); 468 regulator_disable(adc->reg); 469 } 470 471 static const struct of_device_id mcp320x_dt_ids[] = { 472 /* NOTE: The use of compatibles with no vendor prefix is deprecated. */ 473 { .compatible = "mcp3001" }, 474 { .compatible = "mcp3002" }, 475 { .compatible = "mcp3004" }, 476 { .compatible = "mcp3008" }, 477 { .compatible = "mcp3201" }, 478 { .compatible = "mcp3202" }, 479 { .compatible = "mcp3204" }, 480 { .compatible = "mcp3208" }, 481 { .compatible = "mcp3301" }, 482 { .compatible = "microchip,mcp3001" }, 483 { .compatible = "microchip,mcp3002" }, 484 { .compatible = "microchip,mcp3004" }, 485 { .compatible = "microchip,mcp3008" }, 486 { .compatible = "microchip,mcp3201" }, 487 { .compatible = "microchip,mcp3202" }, 488 { .compatible = "microchip,mcp3204" }, 489 { .compatible = "microchip,mcp3208" }, 490 { .compatible = "microchip,mcp3301" }, 491 { .compatible = "microchip,mcp3550-50" }, 492 { .compatible = "microchip,mcp3550-60" }, 493 { .compatible = "microchip,mcp3551" }, 494 { .compatible = "microchip,mcp3553" }, 495 { } 496 }; 497 MODULE_DEVICE_TABLE(of, mcp320x_dt_ids); 498 499 static const struct spi_device_id mcp320x_id[] = { 500 { "mcp3001", mcp3001 }, 501 { "mcp3002", mcp3002 }, 502 { "mcp3004", mcp3004 }, 503 { "mcp3008", mcp3008 }, 504 { "mcp3201", mcp3201 }, 505 { "mcp3202", mcp3202 }, 506 { "mcp3204", mcp3204 }, 507 { "mcp3208", mcp3208 }, 508 { "mcp3301", mcp3301 }, 509 { "mcp3550-50", mcp3550_50 }, 510 { "mcp3550-60", mcp3550_60 }, 511 { "mcp3551", mcp3551 }, 512 { "mcp3553", mcp3553 }, 513 { } 514 }; 515 MODULE_DEVICE_TABLE(spi, mcp320x_id); 516 517 static struct spi_driver mcp320x_driver = { 518 .driver = { 519 .name = "mcp320x", 520 .of_match_table = mcp320x_dt_ids, 521 }, 522 .probe = mcp320x_probe, 523 .remove = mcp320x_remove, 524 .id_table = mcp320x_id, 525 }; 526 module_spi_driver(mcp320x_driver); 527 528 MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>"); 529 MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3"); 530 MODULE_LICENSE("GPL v2"); 531