1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * iio/adc/max1363.c 4 * Copyright (C) 2008-2010 Jonathan Cameron 5 * 6 * based on linux/drivers/i2c/chips/max123x 7 * Copyright (C) 2002-2004 Stefan Eletzhofer 8 * 9 * based on linux/drivers/acron/char/pcf8583.c 10 * Copyright (C) 2000 Russell King 11 * 12 * Driver for max1363 and similar chips. 13 */ 14 15 #include <linux/interrupt.h> 16 #include <linux/device.h> 17 #include <linux/kernel.h> 18 #include <linux/sysfs.h> 19 #include <linux/list.h> 20 #include <linux/i2c.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/err.h> 24 #include <linux/module.h> 25 #include <linux/mod_devicetable.h> 26 #include <linux/property.h> 27 28 #include <linux/iio/iio.h> 29 #include <linux/iio/sysfs.h> 30 #include <linux/iio/events.h> 31 #include <linux/iio/buffer.h> 32 #include <linux/iio/kfifo_buf.h> 33 #include <linux/iio/trigger_consumer.h> 34 #include <linux/iio/triggered_buffer.h> 35 36 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80) 37 38 /* There is a fair bit more defined here than currently 39 * used, but the intention is to support everything these 40 * chips do in the long run */ 41 42 /* see data sheets */ 43 /* max1363 and max1236, max1237, max1238, max1239 */ 44 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00 45 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20 46 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40 47 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60 48 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10 49 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00 50 51 /* think about including max11600 etc - more settings */ 52 #define MAX1363_SETUP_EXT_CLOCK 0x08 53 #define MAX1363_SETUP_INT_CLOCK 0x00 54 #define MAX1363_SETUP_UNIPOLAR 0x00 55 #define MAX1363_SETUP_BIPOLAR 0x04 56 #define MAX1363_SETUP_RESET 0x00 57 #define MAX1363_SETUP_NORESET 0x02 58 /* max1363 only - though don't care on others. 59 * For now monitor modes are not implemented as the relevant 60 * line is not connected on my test board. 61 * The definitions are here as I intend to add this soon. 62 */ 63 #define MAX1363_SETUP_MONITOR_SETUP 0x01 64 65 /* Specific to the max1363 */ 66 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4)) 67 #define MAX1363_MON_INT_ENABLE 0x01 68 69 /* defined for readability reasons */ 70 /* All chips */ 71 #define MAX1363_CONFIG_BYTE(a) ((a)) 72 73 #define MAX1363_CONFIG_SE 0x01 74 #define MAX1363_CONFIG_DE 0x00 75 #define MAX1363_CONFIG_SCAN_TO_CS 0x00 76 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20 77 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40 78 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60 79 /* max123{6-9} only */ 80 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40 81 82 /* max1363 only - merely part of channel selects or don't care for others */ 83 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18 84 85 #define MAX1363_CHANNEL_SEL(a) ((a) << 1) 86 87 /* max1363 strictly 0x06 - but doesn't matter */ 88 #define MAX1363_CHANNEL_SEL_MASK 0x1E 89 #define MAX1363_SCAN_MASK 0x60 90 #define MAX1363_SE_DE_MASK 0x01 91 92 #define MAX1363_MAX_CHANNELS 25 93 /** 94 * struct max1363_mode - scan mode information 95 * @conf: The corresponding value of the configuration register 96 * @modemask: Bit mask corresponding to channels enabled in this mode 97 */ 98 struct max1363_mode { 99 int8_t conf; 100 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS); 101 }; 102 103 /* This must be maintained along side the max1363_mode_table in max1363_core */ 104 enum max1363_modes { 105 /* Single read of a single channel */ 106 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 107 /* Differential single read */ 108 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 109 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 110 /* Scan to channel and mid to channel where overlapping */ 111 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6, 112 s6to7, s0to7, s6to8, s0to8, s6to9, 113 s0to9, s6to10, s0to10, s6to11, s0to11, 114 /* Differential scan to channel and mid to channel where overlapping */ 115 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9, 116 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2, 117 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8, 118 d7m6to11m10, d1m0to11m10, 119 }; 120 121 /** 122 * struct max1363_chip_info - chip specifc information 123 * @info: iio core function callbacks structure 124 * @channels: channel specification 125 * @num_channels: number of channels 126 * @mode_list: array of available scan modes 127 * @default_mode: the scan mode in which the chip starts up 128 * @int_vref_mv: the internal reference voltage 129 * @num_modes: number of modes 130 * @bits: accuracy of the adc in bits 131 */ 132 struct max1363_chip_info { 133 const struct iio_info *info; 134 const struct iio_chan_spec *channels; 135 int num_channels; 136 const enum max1363_modes *mode_list; 137 enum max1363_modes default_mode; 138 u16 int_vref_mv; 139 u8 num_modes; 140 u8 bits; 141 }; 142 143 /** 144 * struct max1363_state - driver instance specific data 145 * @client: i2c_client 146 * @setupbyte: cache of current device setup byte 147 * @configbyte: cache of current device config byte 148 * @chip_info: chip model specific constants, available modes, etc. 149 * @current_mode: the scan mode of this chip 150 * @requestedmask: a valid requested set of channels 151 * @reg: supply regulator 152 * @lock: lock to ensure state is consistent 153 * @monitor_on: whether monitor mode is enabled 154 * @monitor_speed: parameter corresponding to device monitor speed setting 155 * @mask_high: bitmask for enabled high thresholds 156 * @mask_low: bitmask for enabled low thresholds 157 * @thresh_high: high threshold values 158 * @thresh_low: low threshold values 159 * @vref: Reference voltage regulator 160 * @vref_uv: Actual (external or internal) reference voltage 161 * @send: function used to send data to the chip 162 * @recv: function used to receive data from the chip 163 */ 164 struct max1363_state { 165 struct i2c_client *client; 166 u8 setupbyte; 167 u8 configbyte; 168 const struct max1363_chip_info *chip_info; 169 const struct max1363_mode *current_mode; 170 u32 requestedmask; 171 struct regulator *reg; 172 struct mutex lock; 173 174 /* Using monitor modes and buffer at the same time is 175 currently not supported */ 176 bool monitor_on; 177 unsigned int monitor_speed:3; 178 u8 mask_high; 179 u8 mask_low; 180 /* 4x unipolar first then the fours bipolar ones */ 181 s16 thresh_high[8]; 182 s16 thresh_low[8]; 183 struct regulator *vref; 184 u32 vref_uv; 185 int (*send)(const struct i2c_client *client, 186 const char *buf, int count); 187 int (*recv)(const struct i2c_client *client, 188 char *buf, int count); 189 }; 190 191 #define MAX1363_MODE_SINGLE(_num, _mask) { \ 192 .conf = MAX1363_CHANNEL_SEL(_num) \ 193 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 194 | MAX1363_CONFIG_SE, \ 195 .modemask[0] = _mask, \ 196 } 197 198 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \ 199 .conf = MAX1363_CHANNEL_SEL(_num) \ 200 | MAX1363_CONFIG_SCAN_TO_CS \ 201 | MAX1363_CONFIG_SE, \ 202 .modemask[0] = _mask, \ 203 } 204 205 /* note not available for max1363 hence naming */ 206 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \ 207 .conf = MAX1363_CHANNEL_SEL(_num) \ 208 | MAX1236_SCAN_MID_TO_CHANNEL \ 209 | MAX1363_CONFIG_SE, \ 210 .modemask[0] = _mask \ 211 } 212 213 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \ 214 .conf = MAX1363_CHANNEL_SEL(_nump) \ 215 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 216 | MAX1363_CONFIG_DE, \ 217 .modemask[0] = _mask \ 218 } 219 220 /* Can't think how to automate naming so specify for now */ 221 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \ 222 .conf = MAX1363_CHANNEL_SEL(_num) \ 223 | MAX1363_CONFIG_SCAN_TO_CS \ 224 | MAX1363_CONFIG_DE, \ 225 .modemask[0] = _mask \ 226 } 227 228 /* note only available for max1363 hence naming */ 229 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \ 230 .conf = MAX1363_CHANNEL_SEL(_num) \ 231 | MAX1236_SCAN_MID_TO_CHANNEL \ 232 | MAX1363_CONFIG_SE, \ 233 .modemask[0] = _mask \ 234 } 235 236 static const struct max1363_mode max1363_mode_table[] = { 237 /* All of the single channel options first */ 238 MAX1363_MODE_SINGLE(0, 1 << 0), 239 MAX1363_MODE_SINGLE(1, 1 << 1), 240 MAX1363_MODE_SINGLE(2, 1 << 2), 241 MAX1363_MODE_SINGLE(3, 1 << 3), 242 MAX1363_MODE_SINGLE(4, 1 << 4), 243 MAX1363_MODE_SINGLE(5, 1 << 5), 244 MAX1363_MODE_SINGLE(6, 1 << 6), 245 MAX1363_MODE_SINGLE(7, 1 << 7), 246 MAX1363_MODE_SINGLE(8, 1 << 8), 247 MAX1363_MODE_SINGLE(9, 1 << 9), 248 MAX1363_MODE_SINGLE(10, 1 << 10), 249 MAX1363_MODE_SINGLE(11, 1 << 11), 250 251 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12), 252 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13), 253 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14), 254 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15), 255 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16), 256 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17), 257 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18), 258 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19), 259 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20), 260 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21), 261 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22), 262 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23), 263 264 /* The multichannel scans next */ 265 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003), 266 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007), 267 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C), 268 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F), 269 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F), 270 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F), 271 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F), 272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0), 273 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF), 274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0), 275 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF), 276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0), 277 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF), 278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0), 279 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF), 280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0), 281 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF), 282 283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000), 284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000), 285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000), 286 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000), 287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000), 288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000), 289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000), 290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000), 291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000), 292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000), 293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000), 294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000), 295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000), 296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000), 297 }; 298 299 static const struct max1363_mode 300 *max1363_match_mode(const unsigned long *mask, 301 const struct max1363_chip_info *ci) 302 { 303 int i; 304 if (mask) 305 for (i = 0; i < ci->num_modes; i++) 306 if (bitmap_subset(mask, 307 max1363_mode_table[ci->mode_list[i]]. 308 modemask, 309 MAX1363_MAX_CHANNELS)) 310 return &max1363_mode_table[ci->mode_list[i]]; 311 return NULL; 312 } 313 314 static int max1363_smbus_send(const struct i2c_client *client, const char *buf, 315 int count) 316 { 317 int i, err; 318 319 for (i = err = 0; err == 0 && i < count; ++i) 320 err = i2c_smbus_write_byte(client, buf[i]); 321 322 return err ? err : count; 323 } 324 325 static int max1363_smbus_recv(const struct i2c_client *client, char *buf, 326 int count) 327 { 328 int i, ret; 329 330 for (i = 0; i < count; ++i) { 331 ret = i2c_smbus_read_byte(client); 332 if (ret < 0) 333 return ret; 334 buf[i] = ret; 335 } 336 337 return count; 338 } 339 340 static int max1363_write_basic_config(struct max1363_state *st) 341 { 342 u8 tx_buf[2] = { st->setupbyte, st->configbyte }; 343 344 return st->send(st->client, tx_buf, 2); 345 } 346 347 static int max1363_set_scan_mode(struct max1363_state *st) 348 { 349 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 350 | MAX1363_SCAN_MASK 351 | MAX1363_SE_DE_MASK); 352 st->configbyte |= st->current_mode->conf; 353 354 return max1363_write_basic_config(st); 355 } 356 357 static int max1363_read_single_chan(struct iio_dev *indio_dev, 358 struct iio_chan_spec const *chan, 359 int *val, 360 long m) 361 { 362 int ret = 0; 363 s32 data; 364 u8 rxbuf[2]; 365 struct max1363_state *st = iio_priv(indio_dev); 366 struct i2c_client *client = st->client; 367 368 ret = iio_device_claim_direct_mode(indio_dev); 369 if (ret) 370 return ret; 371 mutex_lock(&st->lock); 372 373 /* 374 * If monitor mode is enabled, the method for reading a single 375 * channel will have to be rather different and has not yet 376 * been implemented. 377 * 378 * Also, cannot read directly if buffered capture enabled. 379 */ 380 if (st->monitor_on) { 381 ret = -EBUSY; 382 goto error_ret; 383 } 384 385 /* Check to see if current scan mode is correct */ 386 if (st->current_mode != &max1363_mode_table[chan->address]) { 387 /* Update scan mode if needed */ 388 st->current_mode = &max1363_mode_table[chan->address]; 389 ret = max1363_set_scan_mode(st); 390 if (ret < 0) 391 goto error_ret; 392 } 393 if (st->chip_info->bits != 8) { 394 /* Get reading */ 395 data = st->recv(client, rxbuf, 2); 396 if (data < 0) { 397 ret = data; 398 goto error_ret; 399 } 400 data = (rxbuf[1] | rxbuf[0] << 8) & 401 ((1 << st->chip_info->bits) - 1); 402 } else { 403 /* Get reading */ 404 data = st->recv(client, rxbuf, 1); 405 if (data < 0) { 406 ret = data; 407 goto error_ret; 408 } 409 data = rxbuf[0]; 410 } 411 *val = data; 412 413 error_ret: 414 mutex_unlock(&st->lock); 415 iio_device_release_direct_mode(indio_dev); 416 return ret; 417 418 } 419 420 static int max1363_read_raw(struct iio_dev *indio_dev, 421 struct iio_chan_spec const *chan, 422 int *val, 423 int *val2, 424 long m) 425 { 426 struct max1363_state *st = iio_priv(indio_dev); 427 int ret; 428 429 switch (m) { 430 case IIO_CHAN_INFO_RAW: 431 ret = max1363_read_single_chan(indio_dev, chan, val, m); 432 if (ret < 0) 433 return ret; 434 return IIO_VAL_INT; 435 case IIO_CHAN_INFO_SCALE: 436 *val = st->vref_uv / 1000; 437 *val2 = st->chip_info->bits; 438 return IIO_VAL_FRACTIONAL_LOG2; 439 default: 440 return -EINVAL; 441 } 442 return 0; 443 } 444 445 /* Applies to max1363 */ 446 static const enum max1363_modes max1363_mode_list[] = { 447 _s0, _s1, _s2, _s3, 448 s0to1, s0to2, s0to3, 449 d0m1, d2m3, d1m0, d3m2, 450 d0m1to2m3, d1m0to3m2, 451 }; 452 453 static const struct iio_event_spec max1363_events[] = { 454 { 455 .type = IIO_EV_TYPE_THRESH, 456 .dir = IIO_EV_DIR_RISING, 457 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 458 BIT(IIO_EV_INFO_ENABLE), 459 }, { 460 .type = IIO_EV_TYPE_THRESH, 461 .dir = IIO_EV_DIR_FALLING, 462 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 463 BIT(IIO_EV_INFO_ENABLE), 464 }, 465 }; 466 467 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \ 468 { \ 469 .type = IIO_VOLTAGE, \ 470 .indexed = 1, \ 471 .channel = num, \ 472 .address = addr, \ 473 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 474 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 475 .datasheet_name = "AIN"#num, \ 476 .scan_type = { \ 477 .sign = 'u', \ 478 .realbits = bits, \ 479 .storagebits = (bits > 8) ? 16 : 8, \ 480 .endianness = IIO_BE, \ 481 }, \ 482 .scan_index = si, \ 483 .event_spec = ev_spec, \ 484 .num_event_specs = num_ev_spec, \ 485 } 486 487 /* bipolar channel */ 488 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \ 489 { \ 490 .type = IIO_VOLTAGE, \ 491 .differential = 1, \ 492 .indexed = 1, \ 493 .channel = num, \ 494 .channel2 = num2, \ 495 .address = addr, \ 496 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 497 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 498 .datasheet_name = "AIN"#num"-AIN"#num2, \ 499 .scan_type = { \ 500 .sign = 's', \ 501 .realbits = bits, \ 502 .storagebits = (bits > 8) ? 16 : 8, \ 503 .endianness = IIO_BE, \ 504 }, \ 505 .scan_index = si, \ 506 .event_spec = ev_spec, \ 507 .num_event_specs = num_ev_spec, \ 508 } 509 510 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \ 511 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \ 512 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \ 513 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \ 514 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \ 515 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \ 516 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \ 517 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \ 518 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \ 519 IIO_CHAN_SOFT_TIMESTAMP(8) \ 520 } 521 522 static const struct iio_chan_spec max1036_channels[] = 523 MAX1363_4X_CHANS(8, NULL, 0); 524 static const struct iio_chan_spec max1136_channels[] = 525 MAX1363_4X_CHANS(10, NULL, 0); 526 static const struct iio_chan_spec max1236_channels[] = 527 MAX1363_4X_CHANS(12, NULL, 0); 528 static const struct iio_chan_spec max1361_channels[] = 529 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events)); 530 static const struct iio_chan_spec max1363_channels[] = 531 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events)); 532 533 /* Applies to max1236, max1237 */ 534 static const enum max1363_modes max1236_mode_list[] = { 535 _s0, _s1, _s2, _s3, 536 s0to1, s0to2, s0to3, 537 d0m1, d2m3, d1m0, d3m2, 538 d0m1to2m3, d1m0to3m2, 539 s2to3, 540 }; 541 542 /* Applies to max1238, max1239 */ 543 static const enum max1363_modes max1238_mode_list[] = { 544 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 545 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, 546 s0to7, s0to8, s0to9, s0to10, s0to11, 547 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 548 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 549 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11, 550 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10, 551 s6to7, s6to8, s6to9, s6to10, s6to11, 552 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10, 553 }; 554 555 #define MAX1363_12X_CHANS(bits) { \ 556 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 557 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 558 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 559 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 560 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 561 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 562 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 563 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 564 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \ 565 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \ 566 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \ 567 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \ 568 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \ 569 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \ 570 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \ 571 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \ 572 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \ 573 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \ 574 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \ 575 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \ 576 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \ 577 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \ 578 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \ 579 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \ 580 IIO_CHAN_SOFT_TIMESTAMP(24) \ 581 } 582 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8); 583 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10); 584 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12); 585 586 static const enum max1363_modes max11607_mode_list[] = { 587 _s0, _s1, _s2, _s3, 588 s0to1, s0to2, s0to3, 589 s2to3, 590 d0m1, d2m3, d1m0, d3m2, 591 d0m1to2m3, d1m0to3m2, 592 }; 593 594 static const enum max1363_modes max11608_mode_list[] = { 595 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, 596 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7, 597 s6to7, 598 d0m1, d2m3, d4m5, d6m7, 599 d1m0, d3m2, d5m4, d7m6, 600 d0m1to2m3, d0m1to4m5, d0m1to6m7, 601 d1m0to3m2, d1m0to5m4, d1m0to7m6, 602 }; 603 604 #define MAX1363_8X_CHANS(bits) { \ 605 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 606 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 607 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 608 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 609 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 610 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 611 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 612 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 613 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \ 614 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \ 615 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \ 616 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \ 617 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \ 618 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \ 619 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \ 620 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \ 621 IIO_CHAN_SOFT_TIMESTAMP(16) \ 622 } 623 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8); 624 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10); 625 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12); 626 627 static const enum max1363_modes max11644_mode_list[] = { 628 _s0, _s1, s0to1, d0m1, d1m0, 629 }; 630 631 #define MAX1363_2X_CHANS(bits) { \ 632 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 633 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 634 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \ 635 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \ 636 IIO_CHAN_SOFT_TIMESTAMP(4) \ 637 } 638 639 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10); 640 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12); 641 642 enum { max1361, 643 max1362, 644 max1363, 645 max1364, 646 max1036, 647 max1037, 648 max1038, 649 max1039, 650 max1136, 651 max1137, 652 max1138, 653 max1139, 654 max1236, 655 max1237, 656 max1238, 657 max1239, 658 max11600, 659 max11601, 660 max11602, 661 max11603, 662 max11604, 663 max11605, 664 max11606, 665 max11607, 666 max11608, 667 max11609, 668 max11610, 669 max11611, 670 max11612, 671 max11613, 672 max11614, 673 max11615, 674 max11616, 675 max11617, 676 max11644, 677 max11645, 678 max11646, 679 max11647 680 }; 681 682 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600, 683 8300, 4200, 2000, 1000 }; 684 685 static ssize_t max1363_monitor_show_freq(struct device *dev, 686 struct device_attribute *attr, 687 char *buf) 688 { 689 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev)); 690 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]); 691 } 692 693 static ssize_t max1363_monitor_store_freq(struct device *dev, 694 struct device_attribute *attr, 695 const char *buf, 696 size_t len) 697 { 698 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 699 struct max1363_state *st = iio_priv(indio_dev); 700 int i, ret; 701 unsigned long val; 702 bool found = false; 703 704 ret = kstrtoul(buf, 10, &val); 705 if (ret) 706 return -EINVAL; 707 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++) 708 if (val == max1363_monitor_speeds[i]) { 709 found = true; 710 break; 711 } 712 if (!found) 713 return -EINVAL; 714 715 mutex_lock(&st->lock); 716 st->monitor_speed = i; 717 mutex_unlock(&st->lock); 718 719 return 0; 720 } 721 722 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, 723 max1363_monitor_show_freq, 724 max1363_monitor_store_freq); 725 726 static IIO_CONST_ATTR(sampling_frequency_available, 727 "133000 665000 33300 16600 8300 4200 2000 1000"); 728 729 static int max1363_read_thresh(struct iio_dev *indio_dev, 730 const struct iio_chan_spec *chan, enum iio_event_type type, 731 enum iio_event_direction dir, enum iio_event_info info, int *val, 732 int *val2) 733 { 734 struct max1363_state *st = iio_priv(indio_dev); 735 if (dir == IIO_EV_DIR_FALLING) 736 *val = st->thresh_low[chan->channel]; 737 else 738 *val = st->thresh_high[chan->channel]; 739 return IIO_VAL_INT; 740 } 741 742 static int max1363_write_thresh(struct iio_dev *indio_dev, 743 const struct iio_chan_spec *chan, enum iio_event_type type, 744 enum iio_event_direction dir, enum iio_event_info info, int val, 745 int val2) 746 { 747 struct max1363_state *st = iio_priv(indio_dev); 748 /* make it handle signed correctly as well */ 749 switch (st->chip_info->bits) { 750 case 10: 751 if (val > 0x3FF) 752 return -EINVAL; 753 break; 754 case 12: 755 if (val > 0xFFF) 756 return -EINVAL; 757 break; 758 } 759 760 switch (dir) { 761 case IIO_EV_DIR_FALLING: 762 st->thresh_low[chan->channel] = val; 763 break; 764 case IIO_EV_DIR_RISING: 765 st->thresh_high[chan->channel] = val; 766 break; 767 default: 768 return -EINVAL; 769 } 770 771 return 0; 772 } 773 774 static const u64 max1363_event_codes[] = { 775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 783 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 784 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 785 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 786 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 787 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 788 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 789 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 790 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 791 }; 792 793 static irqreturn_t max1363_event_handler(int irq, void *private) 794 { 795 struct iio_dev *indio_dev = private; 796 struct max1363_state *st = iio_priv(indio_dev); 797 s64 timestamp = iio_get_time_ns(indio_dev); 798 unsigned long mask, loc; 799 u8 rx; 800 u8 tx[2] = { st->setupbyte, 801 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 }; 802 803 st->recv(st->client, &rx, 1); 804 mask = rx; 805 for_each_set_bit(loc, &mask, 8) 806 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp); 807 st->send(st->client, tx, 2); 808 809 return IRQ_HANDLED; 810 } 811 812 static int max1363_read_event_config(struct iio_dev *indio_dev, 813 const struct iio_chan_spec *chan, enum iio_event_type type, 814 enum iio_event_direction dir) 815 { 816 struct max1363_state *st = iio_priv(indio_dev); 817 int val; 818 int number = chan->channel; 819 820 mutex_lock(&st->lock); 821 if (dir == IIO_EV_DIR_FALLING) 822 val = (1 << number) & st->mask_low; 823 else 824 val = (1 << number) & st->mask_high; 825 mutex_unlock(&st->lock); 826 827 return val; 828 } 829 830 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled) 831 { 832 u8 *tx_buf; 833 int ret, i = 3, j; 834 unsigned long numelements; 835 int len; 836 const long *modemask; 837 838 if (!enabled) { 839 /* transition to buffered capture is not currently supported */ 840 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP; 841 st->configbyte &= ~MAX1363_SCAN_MASK; 842 st->monitor_on = false; 843 return max1363_write_basic_config(st); 844 } 845 846 /* Ensure we are in the relevant mode */ 847 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP; 848 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 849 | MAX1363_SCAN_MASK 850 | MAX1363_SE_DE_MASK); 851 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE; 852 if ((st->mask_low | st->mask_high) & 0x0F) { 853 st->configbyte |= max1363_mode_table[s0to3].conf; 854 modemask = max1363_mode_table[s0to3].modemask; 855 } else if ((st->mask_low | st->mask_high) & 0x30) { 856 st->configbyte |= max1363_mode_table[d0m1to2m3].conf; 857 modemask = max1363_mode_table[d0m1to2m3].modemask; 858 } else { 859 st->configbyte |= max1363_mode_table[d1m0to3m2].conf; 860 modemask = max1363_mode_table[d1m0to3m2].modemask; 861 } 862 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS); 863 len = 3 * numelements + 3; 864 tx_buf = kmalloc(len, GFP_KERNEL); 865 if (!tx_buf) { 866 ret = -ENOMEM; 867 goto error_ret; 868 } 869 tx_buf[0] = st->configbyte; 870 tx_buf[1] = st->setupbyte; 871 tx_buf[2] = (st->monitor_speed << 1); 872 873 /* 874 * So we need to do yet another bit of nefarious scan mode 875 * setup to match what we need. 876 */ 877 for (j = 0; j < 8; j++) 878 if (test_bit(j, modemask)) { 879 /* Establish the mode is in the scan */ 880 if (st->mask_low & (1 << j)) { 881 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF; 882 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0; 883 } else if (j < 4) { 884 tx_buf[i] = 0; 885 tx_buf[i + 1] = 0; 886 } else { 887 tx_buf[i] = 0x80; 888 tx_buf[i + 1] = 0; 889 } 890 if (st->mask_high & (1 << j)) { 891 tx_buf[i + 1] |= 892 (st->thresh_high[j] >> 8) & 0x0F; 893 tx_buf[i + 2] = st->thresh_high[j] & 0xFF; 894 } else if (j < 4) { 895 tx_buf[i + 1] |= 0x0F; 896 tx_buf[i + 2] = 0xFF; 897 } else { 898 tx_buf[i + 1] |= 0x07; 899 tx_buf[i + 2] = 0xFF; 900 } 901 i += 3; 902 } 903 904 905 ret = st->send(st->client, tx_buf, len); 906 if (ret < 0) 907 goto error_ret; 908 if (ret != len) { 909 ret = -EIO; 910 goto error_ret; 911 } 912 913 /* 914 * Now that we hopefully have sensible thresholds in place it is 915 * time to turn the interrupts on. 916 * It is unclear from the data sheet if this should be necessary 917 * (i.e. whether monitor mode setup is atomic) but it appears to 918 * be in practice. 919 */ 920 tx_buf[0] = st->setupbyte; 921 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0; 922 ret = st->send(st->client, tx_buf, 2); 923 if (ret < 0) 924 goto error_ret; 925 if (ret != 2) { 926 ret = -EIO; 927 goto error_ret; 928 } 929 ret = 0; 930 st->monitor_on = true; 931 error_ret: 932 933 kfree(tx_buf); 934 935 return ret; 936 } 937 938 /* 939 * To keep this manageable we always use one of 3 scan modes. 940 * Scan 0...3, 0-1,2-3 and 1-0,3-2 941 */ 942 943 static inline int __max1363_check_event_mask(int thismask, int checkmask) 944 { 945 int ret = 0; 946 /* Is it unipolar */ 947 if (thismask < 4) { 948 if (checkmask & ~0x0F) { 949 ret = -EBUSY; 950 goto error_ret; 951 } 952 } else if (thismask < 6) { 953 if (checkmask & ~0x30) { 954 ret = -EBUSY; 955 goto error_ret; 956 } 957 } else if (checkmask & ~0xC0) 958 ret = -EBUSY; 959 error_ret: 960 return ret; 961 } 962 963 static int max1363_write_event_config(struct iio_dev *indio_dev, 964 const struct iio_chan_spec *chan, enum iio_event_type type, 965 enum iio_event_direction dir, int state) 966 { 967 int ret = 0; 968 struct max1363_state *st = iio_priv(indio_dev); 969 u16 unifiedmask; 970 int number = chan->channel; 971 972 ret = iio_device_claim_direct_mode(indio_dev); 973 if (ret) 974 return ret; 975 mutex_lock(&st->lock); 976 977 unifiedmask = st->mask_low | st->mask_high; 978 if (dir == IIO_EV_DIR_FALLING) { 979 980 if (state == 0) 981 st->mask_low &= ~(1 << number); 982 else { 983 ret = __max1363_check_event_mask((1 << number), 984 unifiedmask); 985 if (ret) 986 goto error_ret; 987 st->mask_low |= (1 << number); 988 } 989 } else { 990 if (state == 0) 991 st->mask_high &= ~(1 << number); 992 else { 993 ret = __max1363_check_event_mask((1 << number), 994 unifiedmask); 995 if (ret) 996 goto error_ret; 997 st->mask_high |= (1 << number); 998 } 999 } 1000 1001 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low)); 1002 error_ret: 1003 mutex_unlock(&st->lock); 1004 iio_device_release_direct_mode(indio_dev); 1005 1006 return ret; 1007 } 1008 1009 /* 1010 * As with scan_elements, only certain sets of these can 1011 * be combined. 1012 */ 1013 static struct attribute *max1363_event_attributes[] = { 1014 &iio_dev_attr_sampling_frequency.dev_attr.attr, 1015 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1016 NULL, 1017 }; 1018 1019 static const struct attribute_group max1363_event_attribute_group = { 1020 .attrs = max1363_event_attributes, 1021 }; 1022 1023 static int max1363_update_scan_mode(struct iio_dev *indio_dev, 1024 const unsigned long *scan_mask) 1025 { 1026 struct max1363_state *st = iio_priv(indio_dev); 1027 1028 /* 1029 * Need to figure out the current mode based upon the requested 1030 * scan mask in iio_dev 1031 */ 1032 st->current_mode = max1363_match_mode(scan_mask, st->chip_info); 1033 if (!st->current_mode) 1034 return -EINVAL; 1035 max1363_set_scan_mode(st); 1036 return 0; 1037 } 1038 1039 static const struct iio_info max1238_info = { 1040 .read_raw = &max1363_read_raw, 1041 .update_scan_mode = &max1363_update_scan_mode, 1042 }; 1043 1044 static const struct iio_info max1363_info = { 1045 .read_event_value = &max1363_read_thresh, 1046 .write_event_value = &max1363_write_thresh, 1047 .read_event_config = &max1363_read_event_config, 1048 .write_event_config = &max1363_write_event_config, 1049 .read_raw = &max1363_read_raw, 1050 .update_scan_mode = &max1363_update_scan_mode, 1051 .event_attrs = &max1363_event_attribute_group, 1052 }; 1053 1054 /* max1363 and max1368 tested - rest from data sheet */ 1055 static const struct max1363_chip_info max1363_chip_info_tbl[] = { 1056 [max1361] = { 1057 .bits = 10, 1058 .int_vref_mv = 2048, 1059 .mode_list = max1363_mode_list, 1060 .num_modes = ARRAY_SIZE(max1363_mode_list), 1061 .default_mode = s0to3, 1062 .channels = max1361_channels, 1063 .num_channels = ARRAY_SIZE(max1361_channels), 1064 .info = &max1363_info, 1065 }, 1066 [max1362] = { 1067 .bits = 10, 1068 .int_vref_mv = 4096, 1069 .mode_list = max1363_mode_list, 1070 .num_modes = ARRAY_SIZE(max1363_mode_list), 1071 .default_mode = s0to3, 1072 .channels = max1361_channels, 1073 .num_channels = ARRAY_SIZE(max1361_channels), 1074 .info = &max1363_info, 1075 }, 1076 [max1363] = { 1077 .bits = 12, 1078 .int_vref_mv = 2048, 1079 .mode_list = max1363_mode_list, 1080 .num_modes = ARRAY_SIZE(max1363_mode_list), 1081 .default_mode = s0to3, 1082 .channels = max1363_channels, 1083 .num_channels = ARRAY_SIZE(max1363_channels), 1084 .info = &max1363_info, 1085 }, 1086 [max1364] = { 1087 .bits = 12, 1088 .int_vref_mv = 4096, 1089 .mode_list = max1363_mode_list, 1090 .num_modes = ARRAY_SIZE(max1363_mode_list), 1091 .default_mode = s0to3, 1092 .channels = max1363_channels, 1093 .num_channels = ARRAY_SIZE(max1363_channels), 1094 .info = &max1363_info, 1095 }, 1096 [max1036] = { 1097 .bits = 8, 1098 .int_vref_mv = 4096, 1099 .mode_list = max1236_mode_list, 1100 .num_modes = ARRAY_SIZE(max1236_mode_list), 1101 .default_mode = s0to3, 1102 .info = &max1238_info, 1103 .channels = max1036_channels, 1104 .num_channels = ARRAY_SIZE(max1036_channels), 1105 }, 1106 [max1037] = { 1107 .bits = 8, 1108 .int_vref_mv = 2048, 1109 .mode_list = max1236_mode_list, 1110 .num_modes = ARRAY_SIZE(max1236_mode_list), 1111 .default_mode = s0to3, 1112 .info = &max1238_info, 1113 .channels = max1036_channels, 1114 .num_channels = ARRAY_SIZE(max1036_channels), 1115 }, 1116 [max1038] = { 1117 .bits = 8, 1118 .int_vref_mv = 4096, 1119 .mode_list = max1238_mode_list, 1120 .num_modes = ARRAY_SIZE(max1238_mode_list), 1121 .default_mode = s0to11, 1122 .info = &max1238_info, 1123 .channels = max1038_channels, 1124 .num_channels = ARRAY_SIZE(max1038_channels), 1125 }, 1126 [max1039] = { 1127 .bits = 8, 1128 .int_vref_mv = 2048, 1129 .mode_list = max1238_mode_list, 1130 .num_modes = ARRAY_SIZE(max1238_mode_list), 1131 .default_mode = s0to11, 1132 .info = &max1238_info, 1133 .channels = max1038_channels, 1134 .num_channels = ARRAY_SIZE(max1038_channels), 1135 }, 1136 [max1136] = { 1137 .bits = 10, 1138 .int_vref_mv = 4096, 1139 .mode_list = max1236_mode_list, 1140 .num_modes = ARRAY_SIZE(max1236_mode_list), 1141 .default_mode = s0to3, 1142 .info = &max1238_info, 1143 .channels = max1136_channels, 1144 .num_channels = ARRAY_SIZE(max1136_channels), 1145 }, 1146 [max1137] = { 1147 .bits = 10, 1148 .int_vref_mv = 2048, 1149 .mode_list = max1236_mode_list, 1150 .num_modes = ARRAY_SIZE(max1236_mode_list), 1151 .default_mode = s0to3, 1152 .info = &max1238_info, 1153 .channels = max1136_channels, 1154 .num_channels = ARRAY_SIZE(max1136_channels), 1155 }, 1156 [max1138] = { 1157 .bits = 10, 1158 .int_vref_mv = 4096, 1159 .mode_list = max1238_mode_list, 1160 .num_modes = ARRAY_SIZE(max1238_mode_list), 1161 .default_mode = s0to11, 1162 .info = &max1238_info, 1163 .channels = max1138_channels, 1164 .num_channels = ARRAY_SIZE(max1138_channels), 1165 }, 1166 [max1139] = { 1167 .bits = 10, 1168 .int_vref_mv = 2048, 1169 .mode_list = max1238_mode_list, 1170 .num_modes = ARRAY_SIZE(max1238_mode_list), 1171 .default_mode = s0to11, 1172 .info = &max1238_info, 1173 .channels = max1138_channels, 1174 .num_channels = ARRAY_SIZE(max1138_channels), 1175 }, 1176 [max1236] = { 1177 .bits = 12, 1178 .int_vref_mv = 4096, 1179 .mode_list = max1236_mode_list, 1180 .num_modes = ARRAY_SIZE(max1236_mode_list), 1181 .default_mode = s0to3, 1182 .info = &max1238_info, 1183 .channels = max1236_channels, 1184 .num_channels = ARRAY_SIZE(max1236_channels), 1185 }, 1186 [max1237] = { 1187 .bits = 12, 1188 .int_vref_mv = 2048, 1189 .mode_list = max1236_mode_list, 1190 .num_modes = ARRAY_SIZE(max1236_mode_list), 1191 .default_mode = s0to3, 1192 .info = &max1238_info, 1193 .channels = max1236_channels, 1194 .num_channels = ARRAY_SIZE(max1236_channels), 1195 }, 1196 [max1238] = { 1197 .bits = 12, 1198 .int_vref_mv = 4096, 1199 .mode_list = max1238_mode_list, 1200 .num_modes = ARRAY_SIZE(max1238_mode_list), 1201 .default_mode = s0to11, 1202 .info = &max1238_info, 1203 .channels = max1238_channels, 1204 .num_channels = ARRAY_SIZE(max1238_channels), 1205 }, 1206 [max1239] = { 1207 .bits = 12, 1208 .int_vref_mv = 2048, 1209 .mode_list = max1238_mode_list, 1210 .num_modes = ARRAY_SIZE(max1238_mode_list), 1211 .default_mode = s0to11, 1212 .info = &max1238_info, 1213 .channels = max1238_channels, 1214 .num_channels = ARRAY_SIZE(max1238_channels), 1215 }, 1216 [max11600] = { 1217 .bits = 8, 1218 .int_vref_mv = 4096, 1219 .mode_list = max11607_mode_list, 1220 .num_modes = ARRAY_SIZE(max11607_mode_list), 1221 .default_mode = s0to3, 1222 .info = &max1238_info, 1223 .channels = max1036_channels, 1224 .num_channels = ARRAY_SIZE(max1036_channels), 1225 }, 1226 [max11601] = { 1227 .bits = 8, 1228 .int_vref_mv = 2048, 1229 .mode_list = max11607_mode_list, 1230 .num_modes = ARRAY_SIZE(max11607_mode_list), 1231 .default_mode = s0to3, 1232 .info = &max1238_info, 1233 .channels = max1036_channels, 1234 .num_channels = ARRAY_SIZE(max1036_channels), 1235 }, 1236 [max11602] = { 1237 .bits = 8, 1238 .int_vref_mv = 4096, 1239 .mode_list = max11608_mode_list, 1240 .num_modes = ARRAY_SIZE(max11608_mode_list), 1241 .default_mode = s0to7, 1242 .info = &max1238_info, 1243 .channels = max11602_channels, 1244 .num_channels = ARRAY_SIZE(max11602_channels), 1245 }, 1246 [max11603] = { 1247 .bits = 8, 1248 .int_vref_mv = 2048, 1249 .mode_list = max11608_mode_list, 1250 .num_modes = ARRAY_SIZE(max11608_mode_list), 1251 .default_mode = s0to7, 1252 .info = &max1238_info, 1253 .channels = max11602_channels, 1254 .num_channels = ARRAY_SIZE(max11602_channels), 1255 }, 1256 [max11604] = { 1257 .bits = 8, 1258 .int_vref_mv = 4096, 1259 .mode_list = max1238_mode_list, 1260 .num_modes = ARRAY_SIZE(max1238_mode_list), 1261 .default_mode = s0to11, 1262 .info = &max1238_info, 1263 .channels = max1038_channels, 1264 .num_channels = ARRAY_SIZE(max1038_channels), 1265 }, 1266 [max11605] = { 1267 .bits = 8, 1268 .int_vref_mv = 2048, 1269 .mode_list = max1238_mode_list, 1270 .num_modes = ARRAY_SIZE(max1238_mode_list), 1271 .default_mode = s0to11, 1272 .info = &max1238_info, 1273 .channels = max1038_channels, 1274 .num_channels = ARRAY_SIZE(max1038_channels), 1275 }, 1276 [max11606] = { 1277 .bits = 10, 1278 .int_vref_mv = 4096, 1279 .mode_list = max11607_mode_list, 1280 .num_modes = ARRAY_SIZE(max11607_mode_list), 1281 .default_mode = s0to3, 1282 .info = &max1238_info, 1283 .channels = max1136_channels, 1284 .num_channels = ARRAY_SIZE(max1136_channels), 1285 }, 1286 [max11607] = { 1287 .bits = 10, 1288 .int_vref_mv = 2048, 1289 .mode_list = max11607_mode_list, 1290 .num_modes = ARRAY_SIZE(max11607_mode_list), 1291 .default_mode = s0to3, 1292 .info = &max1238_info, 1293 .channels = max1136_channels, 1294 .num_channels = ARRAY_SIZE(max1136_channels), 1295 }, 1296 [max11608] = { 1297 .bits = 10, 1298 .int_vref_mv = 4096, 1299 .mode_list = max11608_mode_list, 1300 .num_modes = ARRAY_SIZE(max11608_mode_list), 1301 .default_mode = s0to7, 1302 .info = &max1238_info, 1303 .channels = max11608_channels, 1304 .num_channels = ARRAY_SIZE(max11608_channels), 1305 }, 1306 [max11609] = { 1307 .bits = 10, 1308 .int_vref_mv = 2048, 1309 .mode_list = max11608_mode_list, 1310 .num_modes = ARRAY_SIZE(max11608_mode_list), 1311 .default_mode = s0to7, 1312 .info = &max1238_info, 1313 .channels = max11608_channels, 1314 .num_channels = ARRAY_SIZE(max11608_channels), 1315 }, 1316 [max11610] = { 1317 .bits = 10, 1318 .int_vref_mv = 4096, 1319 .mode_list = max1238_mode_list, 1320 .num_modes = ARRAY_SIZE(max1238_mode_list), 1321 .default_mode = s0to11, 1322 .info = &max1238_info, 1323 .channels = max1138_channels, 1324 .num_channels = ARRAY_SIZE(max1138_channels), 1325 }, 1326 [max11611] = { 1327 .bits = 10, 1328 .int_vref_mv = 2048, 1329 .mode_list = max1238_mode_list, 1330 .num_modes = ARRAY_SIZE(max1238_mode_list), 1331 .default_mode = s0to11, 1332 .info = &max1238_info, 1333 .channels = max1138_channels, 1334 .num_channels = ARRAY_SIZE(max1138_channels), 1335 }, 1336 [max11612] = { 1337 .bits = 12, 1338 .int_vref_mv = 4096, 1339 .mode_list = max11607_mode_list, 1340 .num_modes = ARRAY_SIZE(max11607_mode_list), 1341 .default_mode = s0to3, 1342 .info = &max1238_info, 1343 .channels = max1363_channels, 1344 .num_channels = ARRAY_SIZE(max1363_channels), 1345 }, 1346 [max11613] = { 1347 .bits = 12, 1348 .int_vref_mv = 2048, 1349 .mode_list = max11607_mode_list, 1350 .num_modes = ARRAY_SIZE(max11607_mode_list), 1351 .default_mode = s0to3, 1352 .info = &max1238_info, 1353 .channels = max1363_channels, 1354 .num_channels = ARRAY_SIZE(max1363_channels), 1355 }, 1356 [max11614] = { 1357 .bits = 12, 1358 .int_vref_mv = 4096, 1359 .mode_list = max11608_mode_list, 1360 .num_modes = ARRAY_SIZE(max11608_mode_list), 1361 .default_mode = s0to7, 1362 .info = &max1238_info, 1363 .channels = max11614_channels, 1364 .num_channels = ARRAY_SIZE(max11614_channels), 1365 }, 1366 [max11615] = { 1367 .bits = 12, 1368 .int_vref_mv = 2048, 1369 .mode_list = max11608_mode_list, 1370 .num_modes = ARRAY_SIZE(max11608_mode_list), 1371 .default_mode = s0to7, 1372 .info = &max1238_info, 1373 .channels = max11614_channels, 1374 .num_channels = ARRAY_SIZE(max11614_channels), 1375 }, 1376 [max11616] = { 1377 .bits = 12, 1378 .int_vref_mv = 4096, 1379 .mode_list = max1238_mode_list, 1380 .num_modes = ARRAY_SIZE(max1238_mode_list), 1381 .default_mode = s0to11, 1382 .info = &max1238_info, 1383 .channels = max1238_channels, 1384 .num_channels = ARRAY_SIZE(max1238_channels), 1385 }, 1386 [max11617] = { 1387 .bits = 12, 1388 .int_vref_mv = 2048, 1389 .mode_list = max1238_mode_list, 1390 .num_modes = ARRAY_SIZE(max1238_mode_list), 1391 .default_mode = s0to11, 1392 .info = &max1238_info, 1393 .channels = max1238_channels, 1394 .num_channels = ARRAY_SIZE(max1238_channels), 1395 }, 1396 [max11644] = { 1397 .bits = 12, 1398 .int_vref_mv = 4096, 1399 .mode_list = max11644_mode_list, 1400 .num_modes = ARRAY_SIZE(max11644_mode_list), 1401 .default_mode = s0to1, 1402 .info = &max1238_info, 1403 .channels = max11644_channels, 1404 .num_channels = ARRAY_SIZE(max11644_channels), 1405 }, 1406 [max11645] = { 1407 .bits = 12, 1408 .int_vref_mv = 2048, 1409 .mode_list = max11644_mode_list, 1410 .num_modes = ARRAY_SIZE(max11644_mode_list), 1411 .default_mode = s0to1, 1412 .info = &max1238_info, 1413 .channels = max11644_channels, 1414 .num_channels = ARRAY_SIZE(max11644_channels), 1415 }, 1416 [max11646] = { 1417 .bits = 10, 1418 .int_vref_mv = 4096, 1419 .mode_list = max11644_mode_list, 1420 .num_modes = ARRAY_SIZE(max11644_mode_list), 1421 .default_mode = s0to1, 1422 .info = &max1238_info, 1423 .channels = max11646_channels, 1424 .num_channels = ARRAY_SIZE(max11646_channels), 1425 }, 1426 [max11647] = { 1427 .bits = 10, 1428 .int_vref_mv = 2048, 1429 .mode_list = max11644_mode_list, 1430 .num_modes = ARRAY_SIZE(max11644_mode_list), 1431 .default_mode = s0to1, 1432 .info = &max1238_info, 1433 .channels = max11646_channels, 1434 .num_channels = ARRAY_SIZE(max11646_channels), 1435 }, 1436 }; 1437 1438 static int max1363_initial_setup(struct max1363_state *st) 1439 { 1440 st->setupbyte = MAX1363_SETUP_INT_CLOCK 1441 | MAX1363_SETUP_UNIPOLAR 1442 | MAX1363_SETUP_NORESET; 1443 1444 if (st->vref) 1445 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF; 1446 else 1447 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF 1448 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT; 1449 1450 /* Set scan mode writes the config anyway so wait until then */ 1451 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte); 1452 st->current_mode = &max1363_mode_table[st->chip_info->default_mode]; 1453 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte); 1454 1455 return max1363_set_scan_mode(st); 1456 } 1457 1458 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev) 1459 { 1460 struct max1363_state *st = iio_priv(indio_dev); 1461 unsigned long *masks; 1462 int i; 1463 1464 masks = devm_kzalloc(&indio_dev->dev, 1465 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS), 1466 sizeof(long), 1467 st->chip_info->num_modes + 1), 1468 GFP_KERNEL); 1469 if (!masks) 1470 return -ENOMEM; 1471 1472 for (i = 0; i < st->chip_info->num_modes; i++) 1473 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i, 1474 max1363_mode_table[st->chip_info->mode_list[i]] 1475 .modemask, MAX1363_MAX_CHANNELS); 1476 1477 indio_dev->available_scan_masks = masks; 1478 1479 return 0; 1480 } 1481 1482 static irqreturn_t max1363_trigger_handler(int irq, void *p) 1483 { 1484 struct iio_poll_func *pf = p; 1485 struct iio_dev *indio_dev = pf->indio_dev; 1486 struct max1363_state *st = iio_priv(indio_dev); 1487 __u8 *rxbuf; 1488 int b_sent; 1489 size_t d_size; 1490 unsigned long numvals = bitmap_weight(st->current_mode->modemask, 1491 MAX1363_MAX_CHANNELS); 1492 1493 /* Ensure the timestamp is 8 byte aligned */ 1494 if (st->chip_info->bits != 8) 1495 d_size = numvals*2; 1496 else 1497 d_size = numvals; 1498 if (indio_dev->scan_timestamp) { 1499 d_size += sizeof(s64); 1500 if (d_size % sizeof(s64)) 1501 d_size += sizeof(s64) - (d_size % sizeof(s64)); 1502 } 1503 /* Monitor mode prevents reading. Whilst not currently implemented 1504 * might as well have this test in here in the meantime as it does 1505 * no harm. 1506 */ 1507 if (numvals == 0) 1508 goto done; 1509 1510 rxbuf = kmalloc(d_size, GFP_KERNEL); 1511 if (rxbuf == NULL) 1512 goto done; 1513 if (st->chip_info->bits != 8) 1514 b_sent = st->recv(st->client, rxbuf, numvals * 2); 1515 else 1516 b_sent = st->recv(st->client, rxbuf, numvals); 1517 if (b_sent < 0) 1518 goto done_free; 1519 1520 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf, 1521 iio_get_time_ns(indio_dev)); 1522 1523 done_free: 1524 kfree(rxbuf); 1525 done: 1526 iio_trigger_notify_done(indio_dev->trig); 1527 1528 return IRQ_HANDLED; 1529 } 1530 1531 #define MAX1363_COMPATIBLE(of_compatible, cfg) { \ 1532 .compatible = of_compatible, \ 1533 .data = &max1363_chip_info_tbl[cfg], \ 1534 } 1535 1536 static const struct of_device_id max1363_of_match[] = { 1537 MAX1363_COMPATIBLE("maxim,max1361", max1361), 1538 MAX1363_COMPATIBLE("maxim,max1362", max1362), 1539 MAX1363_COMPATIBLE("maxim,max1363", max1363), 1540 MAX1363_COMPATIBLE("maxim,max1364", max1364), 1541 MAX1363_COMPATIBLE("maxim,max1036", max1036), 1542 MAX1363_COMPATIBLE("maxim,max1037", max1037), 1543 MAX1363_COMPATIBLE("maxim,max1038", max1038), 1544 MAX1363_COMPATIBLE("maxim,max1039", max1039), 1545 MAX1363_COMPATIBLE("maxim,max1136", max1136), 1546 MAX1363_COMPATIBLE("maxim,max1137", max1137), 1547 MAX1363_COMPATIBLE("maxim,max1138", max1138), 1548 MAX1363_COMPATIBLE("maxim,max1139", max1139), 1549 MAX1363_COMPATIBLE("maxim,max1236", max1236), 1550 MAX1363_COMPATIBLE("maxim,max1237", max1237), 1551 MAX1363_COMPATIBLE("maxim,max1238", max1238), 1552 MAX1363_COMPATIBLE("maxim,max1239", max1239), 1553 MAX1363_COMPATIBLE("maxim,max11600", max11600), 1554 MAX1363_COMPATIBLE("maxim,max11601", max11601), 1555 MAX1363_COMPATIBLE("maxim,max11602", max11602), 1556 MAX1363_COMPATIBLE("maxim,max11603", max11603), 1557 MAX1363_COMPATIBLE("maxim,max11604", max11604), 1558 MAX1363_COMPATIBLE("maxim,max11605", max11605), 1559 MAX1363_COMPATIBLE("maxim,max11606", max11606), 1560 MAX1363_COMPATIBLE("maxim,max11607", max11607), 1561 MAX1363_COMPATIBLE("maxim,max11608", max11608), 1562 MAX1363_COMPATIBLE("maxim,max11609", max11609), 1563 MAX1363_COMPATIBLE("maxim,max11610", max11610), 1564 MAX1363_COMPATIBLE("maxim,max11611", max11611), 1565 MAX1363_COMPATIBLE("maxim,max11612", max11612), 1566 MAX1363_COMPATIBLE("maxim,max11613", max11613), 1567 MAX1363_COMPATIBLE("maxim,max11614", max11614), 1568 MAX1363_COMPATIBLE("maxim,max11615", max11615), 1569 MAX1363_COMPATIBLE("maxim,max11616", max11616), 1570 MAX1363_COMPATIBLE("maxim,max11617", max11617), 1571 MAX1363_COMPATIBLE("maxim,max11644", max11644), 1572 MAX1363_COMPATIBLE("maxim,max11645", max11645), 1573 MAX1363_COMPATIBLE("maxim,max11646", max11646), 1574 MAX1363_COMPATIBLE("maxim,max11647", max11647), 1575 { /* sentinel */ } 1576 }; 1577 MODULE_DEVICE_TABLE(of, max1363_of_match); 1578 1579 static void max1363_reg_disable(void *reg) 1580 { 1581 regulator_disable(reg); 1582 } 1583 1584 static int max1363_probe(struct i2c_client *client, 1585 const struct i2c_device_id *id) 1586 { 1587 int ret; 1588 struct max1363_state *st; 1589 struct iio_dev *indio_dev; 1590 struct regulator *vref; 1591 1592 indio_dev = devm_iio_device_alloc(&client->dev, 1593 sizeof(struct max1363_state)); 1594 if (!indio_dev) 1595 return -ENOMEM; 1596 1597 st = iio_priv(indio_dev); 1598 1599 mutex_init(&st->lock); 1600 st->reg = devm_regulator_get(&client->dev, "vcc"); 1601 if (IS_ERR(st->reg)) 1602 return PTR_ERR(st->reg); 1603 1604 ret = regulator_enable(st->reg); 1605 if (ret) 1606 return ret; 1607 1608 ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, st->reg); 1609 if (ret) 1610 return ret; 1611 1612 st->chip_info = device_get_match_data(&client->dev); 1613 if (!st->chip_info) 1614 st->chip_info = &max1363_chip_info_tbl[id->driver_data]; 1615 st->client = client; 1616 1617 st->vref_uv = st->chip_info->int_vref_mv * 1000; 1618 vref = devm_regulator_get_optional(&client->dev, "vref"); 1619 if (!IS_ERR(vref)) { 1620 int vref_uv; 1621 1622 ret = regulator_enable(vref); 1623 if (ret) 1624 return ret; 1625 1626 ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, vref); 1627 if (ret) 1628 return ret; 1629 1630 st->vref = vref; 1631 vref_uv = regulator_get_voltage(vref); 1632 if (vref_uv <= 0) 1633 return -EINVAL; 1634 1635 st->vref_uv = vref_uv; 1636 } 1637 1638 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1639 st->send = i2c_master_send; 1640 st->recv = i2c_master_recv; 1641 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE) 1642 && st->chip_info->bits == 8) { 1643 st->send = max1363_smbus_send; 1644 st->recv = max1363_smbus_recv; 1645 } else { 1646 return -EOPNOTSUPP; 1647 } 1648 1649 ret = max1363_alloc_scan_masks(indio_dev); 1650 if (ret) 1651 return ret; 1652 1653 indio_dev->name = id->name; 1654 indio_dev->channels = st->chip_info->channels; 1655 indio_dev->num_channels = st->chip_info->num_channels; 1656 indio_dev->info = st->chip_info->info; 1657 indio_dev->modes = INDIO_DIRECT_MODE; 1658 ret = max1363_initial_setup(st); 1659 if (ret < 0) 1660 return ret; 1661 1662 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, 1663 &max1363_trigger_handler, NULL); 1664 if (ret) 1665 return ret; 1666 1667 if (client->irq) { 1668 ret = devm_request_threaded_irq(&client->dev, st->client->irq, 1669 NULL, 1670 &max1363_event_handler, 1671 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1672 "max1363_event", 1673 indio_dev); 1674 1675 if (ret) 1676 return ret; 1677 } 1678 1679 return devm_iio_device_register(&client->dev, indio_dev); 1680 } 1681 1682 static const struct i2c_device_id max1363_id[] = { 1683 { "max1361", max1361 }, 1684 { "max1362", max1362 }, 1685 { "max1363", max1363 }, 1686 { "max1364", max1364 }, 1687 { "max1036", max1036 }, 1688 { "max1037", max1037 }, 1689 { "max1038", max1038 }, 1690 { "max1039", max1039 }, 1691 { "max1136", max1136 }, 1692 { "max1137", max1137 }, 1693 { "max1138", max1138 }, 1694 { "max1139", max1139 }, 1695 { "max1236", max1236 }, 1696 { "max1237", max1237 }, 1697 { "max1238", max1238 }, 1698 { "max1239", max1239 }, 1699 { "max11600", max11600 }, 1700 { "max11601", max11601 }, 1701 { "max11602", max11602 }, 1702 { "max11603", max11603 }, 1703 { "max11604", max11604 }, 1704 { "max11605", max11605 }, 1705 { "max11606", max11606 }, 1706 { "max11607", max11607 }, 1707 { "max11608", max11608 }, 1708 { "max11609", max11609 }, 1709 { "max11610", max11610 }, 1710 { "max11611", max11611 }, 1711 { "max11612", max11612 }, 1712 { "max11613", max11613 }, 1713 { "max11614", max11614 }, 1714 { "max11615", max11615 }, 1715 { "max11616", max11616 }, 1716 { "max11617", max11617 }, 1717 { "max11644", max11644 }, 1718 { "max11645", max11645 }, 1719 { "max11646", max11646 }, 1720 { "max11647", max11647 }, 1721 {} 1722 }; 1723 1724 MODULE_DEVICE_TABLE(i2c, max1363_id); 1725 1726 static struct i2c_driver max1363_driver = { 1727 .driver = { 1728 .name = "max1363", 1729 .of_match_table = max1363_of_match, 1730 }, 1731 .probe = max1363_probe, 1732 .id_table = max1363_id, 1733 }; 1734 module_i2c_driver(max1363_driver); 1735 1736 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>"); 1737 MODULE_DESCRIPTION("Maxim 1363 ADC"); 1738 MODULE_LICENSE("GPL v2"); 1739