1 /* 2 * iio/adc/max1363.c 3 * Copyright (C) 2008-2010 Jonathan Cameron 4 * 5 * based on linux/drivers/i2c/chips/max123x 6 * Copyright (C) 2002-2004 Stefan Eletzhofer 7 * 8 * based on linux/drivers/acron/char/pcf8583.c 9 * Copyright (C) 2000 Russell King 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * max1363.c 16 * 17 * Partial support for max1363 and similar chips. 18 * 19 * Not currently implemented. 20 * 21 * - Control of internal reference. 22 */ 23 24 #include <linux/interrupt.h> 25 #include <linux/device.h> 26 #include <linux/kernel.h> 27 #include <linux/sysfs.h> 28 #include <linux/list.h> 29 #include <linux/i2c.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/slab.h> 32 #include <linux/err.h> 33 #include <linux/module.h> 34 35 #include <linux/iio/iio.h> 36 #include <linux/iio/sysfs.h> 37 #include <linux/iio/events.h> 38 #include <linux/iio/buffer.h> 39 #include <linux/iio/driver.h> 40 #include <linux/iio/kfifo_buf.h> 41 #include <linux/iio/trigger_consumer.h> 42 #include <linux/iio/triggered_buffer.h> 43 44 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80) 45 46 /* There is a fair bit more defined here than currently 47 * used, but the intention is to support everything these 48 * chips do in the long run */ 49 50 /* see data sheets */ 51 /* max1363 and max1236, max1237, max1238, max1239 */ 52 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00 53 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20 54 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40 55 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60 56 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10 57 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00 58 59 /* think about including max11600 etc - more settings */ 60 #define MAX1363_SETUP_EXT_CLOCK 0x08 61 #define MAX1363_SETUP_INT_CLOCK 0x00 62 #define MAX1363_SETUP_UNIPOLAR 0x00 63 #define MAX1363_SETUP_BIPOLAR 0x04 64 #define MAX1363_SETUP_RESET 0x00 65 #define MAX1363_SETUP_NORESET 0x02 66 /* max1363 only - though don't care on others. 67 * For now monitor modes are not implemented as the relevant 68 * line is not connected on my test board. 69 * The definitions are here as I intend to add this soon. 70 */ 71 #define MAX1363_SETUP_MONITOR_SETUP 0x01 72 73 /* Specific to the max1363 */ 74 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4)) 75 #define MAX1363_MON_INT_ENABLE 0x01 76 77 /* defined for readability reasons */ 78 /* All chips */ 79 #define MAX1363_CONFIG_BYTE(a) ((a)) 80 81 #define MAX1363_CONFIG_SE 0x01 82 #define MAX1363_CONFIG_DE 0x00 83 #define MAX1363_CONFIG_SCAN_TO_CS 0x00 84 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20 85 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40 86 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60 87 /* max123{6-9} only */ 88 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40 89 90 /* max1363 only - merely part of channel selects or don't care for others */ 91 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18 92 93 #define MAX1363_CHANNEL_SEL(a) ((a) << 1) 94 95 /* max1363 strictly 0x06 - but doesn't matter */ 96 #define MAX1363_CHANNEL_SEL_MASK 0x1E 97 #define MAX1363_SCAN_MASK 0x60 98 #define MAX1363_SE_DE_MASK 0x01 99 100 #define MAX1363_MAX_CHANNELS 25 101 /** 102 * struct max1363_mode - scan mode information 103 * @conf: The corresponding value of the configuration register 104 * @modemask: Bit mask corresponding to channels enabled in this mode 105 */ 106 struct max1363_mode { 107 int8_t conf; 108 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS); 109 }; 110 111 /* This must be maintained along side the max1363_mode_table in max1363_core */ 112 enum max1363_modes { 113 /* Single read of a single channel */ 114 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 115 /* Differential single read */ 116 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 117 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 118 /* Scan to channel and mid to channel where overlapping */ 119 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6, 120 s6to7, s0to7, s6to8, s0to8, s6to9, 121 s0to9, s6to10, s0to10, s6to11, s0to11, 122 /* Differential scan to channel and mid to channel where overlapping */ 123 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9, 124 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2, 125 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8, 126 d7m6to11m10, d1m0to11m10, 127 }; 128 129 /** 130 * struct max1363_chip_info - chip specifc information 131 * @info: iio core function callbacks structure 132 * @channels: channel specification 133 * @num_channels: number of channels 134 * @mode_list: array of available scan modes 135 * @default_mode: the scan mode in which the chip starts up 136 * @int_vref_mv: the internal reference voltage 137 * @num_modes: number of modes 138 * @bits: accuracy of the adc in bits 139 */ 140 struct max1363_chip_info { 141 const struct iio_info *info; 142 const struct iio_chan_spec *channels; 143 int num_channels; 144 const enum max1363_modes *mode_list; 145 enum max1363_modes default_mode; 146 u16 int_vref_mv; 147 u8 num_modes; 148 u8 bits; 149 }; 150 151 /** 152 * struct max1363_state - driver instance specific data 153 * @client: i2c_client 154 * @setupbyte: cache of current device setup byte 155 * @configbyte: cache of current device config byte 156 * @chip_info: chip model specific constants, available modes, etc. 157 * @current_mode: the scan mode of this chip 158 * @requestedmask: a valid requested set of channels 159 * @reg: supply regulator 160 * @monitor_on: whether monitor mode is enabled 161 * @monitor_speed: parameter corresponding to device monitor speed setting 162 * @mask_high: bitmask for enabled high thresholds 163 * @mask_low: bitmask for enabled low thresholds 164 * @thresh_high: high threshold values 165 * @thresh_low: low threshold values 166 * @vref: Reference voltage regulator 167 * @vref_uv: Actual (external or internal) reference voltage 168 * @send: function used to send data to the chip 169 * @recv: function used to receive data from the chip 170 */ 171 struct max1363_state { 172 struct i2c_client *client; 173 u8 setupbyte; 174 u8 configbyte; 175 const struct max1363_chip_info *chip_info; 176 const struct max1363_mode *current_mode; 177 u32 requestedmask; 178 struct regulator *reg; 179 180 /* Using monitor modes and buffer at the same time is 181 currently not supported */ 182 bool monitor_on; 183 unsigned int monitor_speed:3; 184 u8 mask_high; 185 u8 mask_low; 186 /* 4x unipolar first then the fours bipolar ones */ 187 s16 thresh_high[8]; 188 s16 thresh_low[8]; 189 struct regulator *vref; 190 u32 vref_uv; 191 int (*send)(const struct i2c_client *client, 192 const char *buf, int count); 193 int (*recv)(const struct i2c_client *client, 194 char *buf, int count); 195 }; 196 197 #define MAX1363_MODE_SINGLE(_num, _mask) { \ 198 .conf = MAX1363_CHANNEL_SEL(_num) \ 199 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 200 | MAX1363_CONFIG_SE, \ 201 .modemask[0] = _mask, \ 202 } 203 204 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \ 205 .conf = MAX1363_CHANNEL_SEL(_num) \ 206 | MAX1363_CONFIG_SCAN_TO_CS \ 207 | MAX1363_CONFIG_SE, \ 208 .modemask[0] = _mask, \ 209 } 210 211 /* note not available for max1363 hence naming */ 212 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \ 213 .conf = MAX1363_CHANNEL_SEL(_num) \ 214 | MAX1236_SCAN_MID_TO_CHANNEL \ 215 | MAX1363_CONFIG_SE, \ 216 .modemask[0] = _mask \ 217 } 218 219 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \ 220 .conf = MAX1363_CHANNEL_SEL(_nump) \ 221 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 222 | MAX1363_CONFIG_DE, \ 223 .modemask[0] = _mask \ 224 } 225 226 /* Can't think how to automate naming so specify for now */ 227 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \ 228 .conf = MAX1363_CHANNEL_SEL(_num) \ 229 | MAX1363_CONFIG_SCAN_TO_CS \ 230 | MAX1363_CONFIG_DE, \ 231 .modemask[0] = _mask \ 232 } 233 234 /* note only available for max1363 hence naming */ 235 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \ 236 .conf = MAX1363_CHANNEL_SEL(_num) \ 237 | MAX1236_SCAN_MID_TO_CHANNEL \ 238 | MAX1363_CONFIG_SE, \ 239 .modemask[0] = _mask \ 240 } 241 242 static const struct max1363_mode max1363_mode_table[] = { 243 /* All of the single channel options first */ 244 MAX1363_MODE_SINGLE(0, 1 << 0), 245 MAX1363_MODE_SINGLE(1, 1 << 1), 246 MAX1363_MODE_SINGLE(2, 1 << 2), 247 MAX1363_MODE_SINGLE(3, 1 << 3), 248 MAX1363_MODE_SINGLE(4, 1 << 4), 249 MAX1363_MODE_SINGLE(5, 1 << 5), 250 MAX1363_MODE_SINGLE(6, 1 << 6), 251 MAX1363_MODE_SINGLE(7, 1 << 7), 252 MAX1363_MODE_SINGLE(8, 1 << 8), 253 MAX1363_MODE_SINGLE(9, 1 << 9), 254 MAX1363_MODE_SINGLE(10, 1 << 10), 255 MAX1363_MODE_SINGLE(11, 1 << 11), 256 257 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12), 258 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13), 259 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14), 260 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15), 261 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16), 262 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17), 263 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18), 264 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19), 265 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20), 266 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21), 267 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22), 268 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23), 269 270 /* The multichannel scans next */ 271 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003), 272 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007), 273 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C), 274 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F), 275 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F), 276 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F), 277 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F), 278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0), 279 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF), 280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0), 281 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF), 282 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0), 283 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF), 284 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0), 285 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF), 286 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0), 287 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF), 288 289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000), 290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000), 291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000), 292 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000), 293 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000), 294 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000), 295 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000), 296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000), 297 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000), 298 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000), 299 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000), 300 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000), 301 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000), 302 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000), 303 }; 304 305 static const struct max1363_mode 306 *max1363_match_mode(const unsigned long *mask, 307 const struct max1363_chip_info *ci) 308 { 309 int i; 310 if (mask) 311 for (i = 0; i < ci->num_modes; i++) 312 if (bitmap_subset(mask, 313 max1363_mode_table[ci->mode_list[i]]. 314 modemask, 315 MAX1363_MAX_CHANNELS)) 316 return &max1363_mode_table[ci->mode_list[i]]; 317 return NULL; 318 } 319 320 static int max1363_smbus_send(const struct i2c_client *client, const char *buf, 321 int count) 322 { 323 int i, err; 324 325 for (i = err = 0; err == 0 && i < count; ++i) 326 err = i2c_smbus_write_byte(client, buf[i]); 327 328 return err ? err : count; 329 } 330 331 static int max1363_smbus_recv(const struct i2c_client *client, char *buf, 332 int count) 333 { 334 int i, ret; 335 336 for (i = 0; i < count; ++i) { 337 ret = i2c_smbus_read_byte(client); 338 if (ret < 0) 339 return ret; 340 buf[i] = ret; 341 } 342 343 return count; 344 } 345 346 static int max1363_write_basic_config(struct max1363_state *st) 347 { 348 u8 tx_buf[2] = { st->setupbyte, st->configbyte }; 349 350 return st->send(st->client, tx_buf, 2); 351 } 352 353 static int max1363_set_scan_mode(struct max1363_state *st) 354 { 355 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 356 | MAX1363_SCAN_MASK 357 | MAX1363_SE_DE_MASK); 358 st->configbyte |= st->current_mode->conf; 359 360 return max1363_write_basic_config(st); 361 } 362 363 static int max1363_read_single_chan(struct iio_dev *indio_dev, 364 struct iio_chan_spec const *chan, 365 int *val, 366 long m) 367 { 368 int ret = 0; 369 s32 data; 370 u8 rxbuf[2]; 371 struct max1363_state *st = iio_priv(indio_dev); 372 struct i2c_client *client = st->client; 373 374 mutex_lock(&indio_dev->mlock); 375 /* 376 * If monitor mode is enabled, the method for reading a single 377 * channel will have to be rather different and has not yet 378 * been implemented. 379 * 380 * Also, cannot read directly if buffered capture enabled. 381 */ 382 if (st->monitor_on || iio_buffer_enabled(indio_dev)) { 383 ret = -EBUSY; 384 goto error_ret; 385 } 386 387 /* Check to see if current scan mode is correct */ 388 if (st->current_mode != &max1363_mode_table[chan->address]) { 389 /* Update scan mode if needed */ 390 st->current_mode = &max1363_mode_table[chan->address]; 391 ret = max1363_set_scan_mode(st); 392 if (ret < 0) 393 goto error_ret; 394 } 395 if (st->chip_info->bits != 8) { 396 /* Get reading */ 397 data = st->recv(client, rxbuf, 2); 398 if (data < 0) { 399 ret = data; 400 goto error_ret; 401 } 402 data = (rxbuf[1] | rxbuf[0] << 8) & 403 ((1 << st->chip_info->bits) - 1); 404 } else { 405 /* Get reading */ 406 data = st->recv(client, rxbuf, 1); 407 if (data < 0) { 408 ret = data; 409 goto error_ret; 410 } 411 data = rxbuf[0]; 412 } 413 *val = data; 414 error_ret: 415 mutex_unlock(&indio_dev->mlock); 416 return ret; 417 418 } 419 420 static int max1363_read_raw(struct iio_dev *indio_dev, 421 struct iio_chan_spec const *chan, 422 int *val, 423 int *val2, 424 long m) 425 { 426 struct max1363_state *st = iio_priv(indio_dev); 427 int ret; 428 429 switch (m) { 430 case IIO_CHAN_INFO_RAW: 431 ret = max1363_read_single_chan(indio_dev, chan, val, m); 432 if (ret < 0) 433 return ret; 434 return IIO_VAL_INT; 435 case IIO_CHAN_INFO_SCALE: 436 *val = st->vref_uv / 1000; 437 *val2 = st->chip_info->bits; 438 return IIO_VAL_FRACTIONAL_LOG2; 439 default: 440 return -EINVAL; 441 } 442 return 0; 443 } 444 445 /* Applies to max1363 */ 446 static const enum max1363_modes max1363_mode_list[] = { 447 _s0, _s1, _s2, _s3, 448 s0to1, s0to2, s0to3, 449 d0m1, d2m3, d1m0, d3m2, 450 d0m1to2m3, d1m0to3m2, 451 }; 452 453 static const struct iio_event_spec max1363_events[] = { 454 { 455 .type = IIO_EV_TYPE_THRESH, 456 .dir = IIO_EV_DIR_RISING, 457 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 458 BIT(IIO_EV_INFO_ENABLE), 459 }, { 460 .type = IIO_EV_TYPE_THRESH, 461 .dir = IIO_EV_DIR_FALLING, 462 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 463 BIT(IIO_EV_INFO_ENABLE), 464 }, 465 }; 466 467 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \ 468 { \ 469 .type = IIO_VOLTAGE, \ 470 .indexed = 1, \ 471 .channel = num, \ 472 .address = addr, \ 473 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 474 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 475 .datasheet_name = "AIN"#num, \ 476 .scan_type = { \ 477 .sign = 'u', \ 478 .realbits = bits, \ 479 .storagebits = (bits > 8) ? 16 : 8, \ 480 .endianness = IIO_BE, \ 481 }, \ 482 .scan_index = si, \ 483 .event_spec = ev_spec, \ 484 .num_event_specs = num_ev_spec, \ 485 } 486 487 /* bipolar channel */ 488 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \ 489 { \ 490 .type = IIO_VOLTAGE, \ 491 .differential = 1, \ 492 .indexed = 1, \ 493 .channel = num, \ 494 .channel2 = num2, \ 495 .address = addr, \ 496 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 497 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 498 .datasheet_name = "AIN"#num"-AIN"#num2, \ 499 .scan_type = { \ 500 .sign = 's', \ 501 .realbits = bits, \ 502 .storagebits = (bits > 8) ? 16 : 8, \ 503 .endianness = IIO_BE, \ 504 }, \ 505 .scan_index = si, \ 506 .event_spec = ev_spec, \ 507 .num_event_specs = num_ev_spec, \ 508 } 509 510 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \ 511 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \ 512 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \ 513 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \ 514 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \ 515 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \ 516 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \ 517 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \ 518 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \ 519 IIO_CHAN_SOFT_TIMESTAMP(8) \ 520 } 521 522 static const struct iio_chan_spec max1036_channels[] = 523 MAX1363_4X_CHANS(8, NULL, 0); 524 static const struct iio_chan_spec max1136_channels[] = 525 MAX1363_4X_CHANS(10, NULL, 0); 526 static const struct iio_chan_spec max1236_channels[] = 527 MAX1363_4X_CHANS(12, NULL, 0); 528 static const struct iio_chan_spec max1361_channels[] = 529 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events)); 530 static const struct iio_chan_spec max1363_channels[] = 531 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events)); 532 533 /* Applies to max1236, max1237 */ 534 static const enum max1363_modes max1236_mode_list[] = { 535 _s0, _s1, _s2, _s3, 536 s0to1, s0to2, s0to3, 537 d0m1, d2m3, d1m0, d3m2, 538 d0m1to2m3, d1m0to3m2, 539 s2to3, 540 }; 541 542 /* Applies to max1238, max1239 */ 543 static const enum max1363_modes max1238_mode_list[] = { 544 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 545 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, 546 s0to7, s0to8, s0to9, s0to10, s0to11, 547 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 548 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 549 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11, 550 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10, 551 s6to7, s6to8, s6to9, s6to10, s6to11, 552 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10, 553 }; 554 555 #define MAX1363_12X_CHANS(bits) { \ 556 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 557 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 558 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 559 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 560 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 561 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 562 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 563 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 564 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \ 565 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \ 566 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \ 567 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \ 568 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \ 569 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \ 570 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \ 571 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \ 572 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \ 573 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \ 574 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \ 575 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \ 576 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \ 577 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \ 578 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \ 579 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \ 580 IIO_CHAN_SOFT_TIMESTAMP(24) \ 581 } 582 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8); 583 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10); 584 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12); 585 586 static const enum max1363_modes max11607_mode_list[] = { 587 _s0, _s1, _s2, _s3, 588 s0to1, s0to2, s0to3, 589 s2to3, 590 d0m1, d2m3, d1m0, d3m2, 591 d0m1to2m3, d1m0to3m2, 592 }; 593 594 static const enum max1363_modes max11608_mode_list[] = { 595 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, 596 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7, 597 s6to7, 598 d0m1, d2m3, d4m5, d6m7, 599 d1m0, d3m2, d5m4, d7m6, 600 d0m1to2m3, d0m1to4m5, d0m1to6m7, 601 d1m0to3m2, d1m0to5m4, d1m0to7m6, 602 }; 603 604 #define MAX1363_8X_CHANS(bits) { \ 605 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 606 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 607 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 608 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 609 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 610 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 611 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 612 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 613 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \ 614 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \ 615 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \ 616 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \ 617 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \ 618 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \ 619 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \ 620 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \ 621 IIO_CHAN_SOFT_TIMESTAMP(16) \ 622 } 623 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8); 624 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10); 625 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12); 626 627 static const enum max1363_modes max11644_mode_list[] = { 628 _s0, _s1, s0to1, d0m1, d1m0, 629 }; 630 631 #define MAX1363_2X_CHANS(bits) { \ 632 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 633 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 634 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \ 635 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \ 636 IIO_CHAN_SOFT_TIMESTAMP(4) \ 637 } 638 639 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10); 640 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12); 641 642 enum { max1361, 643 max1362, 644 max1363, 645 max1364, 646 max1036, 647 max1037, 648 max1038, 649 max1039, 650 max1136, 651 max1137, 652 max1138, 653 max1139, 654 max1236, 655 max1237, 656 max1238, 657 max1239, 658 max11600, 659 max11601, 660 max11602, 661 max11603, 662 max11604, 663 max11605, 664 max11606, 665 max11607, 666 max11608, 667 max11609, 668 max11610, 669 max11611, 670 max11612, 671 max11613, 672 max11614, 673 max11615, 674 max11616, 675 max11617, 676 max11644, 677 max11645, 678 max11646, 679 max11647 680 }; 681 682 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600, 683 8300, 4200, 2000, 1000 }; 684 685 static ssize_t max1363_monitor_show_freq(struct device *dev, 686 struct device_attribute *attr, 687 char *buf) 688 { 689 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev)); 690 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]); 691 } 692 693 static ssize_t max1363_monitor_store_freq(struct device *dev, 694 struct device_attribute *attr, 695 const char *buf, 696 size_t len) 697 { 698 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 699 struct max1363_state *st = iio_priv(indio_dev); 700 int i, ret; 701 unsigned long val; 702 bool found = false; 703 704 ret = kstrtoul(buf, 10, &val); 705 if (ret) 706 return -EINVAL; 707 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++) 708 if (val == max1363_monitor_speeds[i]) { 709 found = true; 710 break; 711 } 712 if (!found) 713 return -EINVAL; 714 715 mutex_lock(&indio_dev->mlock); 716 st->monitor_speed = i; 717 mutex_unlock(&indio_dev->mlock); 718 719 return 0; 720 } 721 722 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, 723 max1363_monitor_show_freq, 724 max1363_monitor_store_freq); 725 726 static IIO_CONST_ATTR(sampling_frequency_available, 727 "133000 665000 33300 16600 8300 4200 2000 1000"); 728 729 static int max1363_read_thresh(struct iio_dev *indio_dev, 730 const struct iio_chan_spec *chan, enum iio_event_type type, 731 enum iio_event_direction dir, enum iio_event_info info, int *val, 732 int *val2) 733 { 734 struct max1363_state *st = iio_priv(indio_dev); 735 if (dir == IIO_EV_DIR_FALLING) 736 *val = st->thresh_low[chan->channel]; 737 else 738 *val = st->thresh_high[chan->channel]; 739 return IIO_VAL_INT; 740 } 741 742 static int max1363_write_thresh(struct iio_dev *indio_dev, 743 const struct iio_chan_spec *chan, enum iio_event_type type, 744 enum iio_event_direction dir, enum iio_event_info info, int val, 745 int val2) 746 { 747 struct max1363_state *st = iio_priv(indio_dev); 748 /* make it handle signed correctly as well */ 749 switch (st->chip_info->bits) { 750 case 10: 751 if (val > 0x3FF) 752 return -EINVAL; 753 break; 754 case 12: 755 if (val > 0xFFF) 756 return -EINVAL; 757 break; 758 } 759 760 switch (dir) { 761 case IIO_EV_DIR_FALLING: 762 st->thresh_low[chan->channel] = val; 763 break; 764 case IIO_EV_DIR_RISING: 765 st->thresh_high[chan->channel] = val; 766 break; 767 default: 768 return -EINVAL; 769 } 770 771 return 0; 772 } 773 774 static const u64 max1363_event_codes[] = { 775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 783 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 784 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 785 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 786 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 787 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 788 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 789 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 790 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 791 }; 792 793 static irqreturn_t max1363_event_handler(int irq, void *private) 794 { 795 struct iio_dev *indio_dev = private; 796 struct max1363_state *st = iio_priv(indio_dev); 797 s64 timestamp = iio_get_time_ns(); 798 unsigned long mask, loc; 799 u8 rx; 800 u8 tx[2] = { st->setupbyte, 801 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 }; 802 803 st->recv(st->client, &rx, 1); 804 mask = rx; 805 for_each_set_bit(loc, &mask, 8) 806 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp); 807 st->send(st->client, tx, 2); 808 809 return IRQ_HANDLED; 810 } 811 812 static int max1363_read_event_config(struct iio_dev *indio_dev, 813 const struct iio_chan_spec *chan, enum iio_event_type type, 814 enum iio_event_direction dir) 815 { 816 struct max1363_state *st = iio_priv(indio_dev); 817 int val; 818 int number = chan->channel; 819 820 mutex_lock(&indio_dev->mlock); 821 if (dir == IIO_EV_DIR_FALLING) 822 val = (1 << number) & st->mask_low; 823 else 824 val = (1 << number) & st->mask_high; 825 mutex_unlock(&indio_dev->mlock); 826 827 return val; 828 } 829 830 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled) 831 { 832 u8 *tx_buf; 833 int ret, i = 3, j; 834 unsigned long numelements; 835 int len; 836 const long *modemask; 837 838 if (!enabled) { 839 /* transition to buffered capture is not currently supported */ 840 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP; 841 st->configbyte &= ~MAX1363_SCAN_MASK; 842 st->monitor_on = false; 843 return max1363_write_basic_config(st); 844 } 845 846 /* Ensure we are in the relevant mode */ 847 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP; 848 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 849 | MAX1363_SCAN_MASK 850 | MAX1363_SE_DE_MASK); 851 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE; 852 if ((st->mask_low | st->mask_high) & 0x0F) { 853 st->configbyte |= max1363_mode_table[s0to3].conf; 854 modemask = max1363_mode_table[s0to3].modemask; 855 } else if ((st->mask_low | st->mask_high) & 0x30) { 856 st->configbyte |= max1363_mode_table[d0m1to2m3].conf; 857 modemask = max1363_mode_table[d0m1to2m3].modemask; 858 } else { 859 st->configbyte |= max1363_mode_table[d1m0to3m2].conf; 860 modemask = max1363_mode_table[d1m0to3m2].modemask; 861 } 862 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS); 863 len = 3 * numelements + 3; 864 tx_buf = kmalloc(len, GFP_KERNEL); 865 if (!tx_buf) { 866 ret = -ENOMEM; 867 goto error_ret; 868 } 869 tx_buf[0] = st->configbyte; 870 tx_buf[1] = st->setupbyte; 871 tx_buf[2] = (st->monitor_speed << 1); 872 873 /* 874 * So we need to do yet another bit of nefarious scan mode 875 * setup to match what we need. 876 */ 877 for (j = 0; j < 8; j++) 878 if (test_bit(j, modemask)) { 879 /* Establish the mode is in the scan */ 880 if (st->mask_low & (1 << j)) { 881 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF; 882 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0; 883 } else if (j < 4) { 884 tx_buf[i] = 0; 885 tx_buf[i + 1] = 0; 886 } else { 887 tx_buf[i] = 0x80; 888 tx_buf[i + 1] = 0; 889 } 890 if (st->mask_high & (1 << j)) { 891 tx_buf[i + 1] |= 892 (st->thresh_high[j] >> 8) & 0x0F; 893 tx_buf[i + 2] = st->thresh_high[j] & 0xFF; 894 } else if (j < 4) { 895 tx_buf[i + 1] |= 0x0F; 896 tx_buf[i + 2] = 0xFF; 897 } else { 898 tx_buf[i + 1] |= 0x07; 899 tx_buf[i + 2] = 0xFF; 900 } 901 i += 3; 902 } 903 904 905 ret = st->send(st->client, tx_buf, len); 906 if (ret < 0) 907 goto error_ret; 908 if (ret != len) { 909 ret = -EIO; 910 goto error_ret; 911 } 912 913 /* 914 * Now that we hopefully have sensible thresholds in place it is 915 * time to turn the interrupts on. 916 * It is unclear from the data sheet if this should be necessary 917 * (i.e. whether monitor mode setup is atomic) but it appears to 918 * be in practice. 919 */ 920 tx_buf[0] = st->setupbyte; 921 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0; 922 ret = st->send(st->client, tx_buf, 2); 923 if (ret < 0) 924 goto error_ret; 925 if (ret != 2) { 926 ret = -EIO; 927 goto error_ret; 928 } 929 ret = 0; 930 st->monitor_on = true; 931 error_ret: 932 933 kfree(tx_buf); 934 935 return ret; 936 } 937 938 /* 939 * To keep this manageable we always use one of 3 scan modes. 940 * Scan 0...3, 0-1,2-3 and 1-0,3-2 941 */ 942 943 static inline int __max1363_check_event_mask(int thismask, int checkmask) 944 { 945 int ret = 0; 946 /* Is it unipolar */ 947 if (thismask < 4) { 948 if (checkmask & ~0x0F) { 949 ret = -EBUSY; 950 goto error_ret; 951 } 952 } else if (thismask < 6) { 953 if (checkmask & ~0x30) { 954 ret = -EBUSY; 955 goto error_ret; 956 } 957 } else if (checkmask & ~0xC0) 958 ret = -EBUSY; 959 error_ret: 960 return ret; 961 } 962 963 static int max1363_write_event_config(struct iio_dev *indio_dev, 964 const struct iio_chan_spec *chan, enum iio_event_type type, 965 enum iio_event_direction dir, int state) 966 { 967 int ret = 0; 968 struct max1363_state *st = iio_priv(indio_dev); 969 u16 unifiedmask; 970 int number = chan->channel; 971 972 mutex_lock(&indio_dev->mlock); 973 unifiedmask = st->mask_low | st->mask_high; 974 if (dir == IIO_EV_DIR_FALLING) { 975 976 if (state == 0) 977 st->mask_low &= ~(1 << number); 978 else { 979 ret = __max1363_check_event_mask((1 << number), 980 unifiedmask); 981 if (ret) 982 goto error_ret; 983 st->mask_low |= (1 << number); 984 } 985 } else { 986 if (state == 0) 987 st->mask_high &= ~(1 << number); 988 else { 989 ret = __max1363_check_event_mask((1 << number), 990 unifiedmask); 991 if (ret) 992 goto error_ret; 993 st->mask_high |= (1 << number); 994 } 995 } 996 997 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low)); 998 error_ret: 999 mutex_unlock(&indio_dev->mlock); 1000 1001 return ret; 1002 } 1003 1004 /* 1005 * As with scan_elements, only certain sets of these can 1006 * be combined. 1007 */ 1008 static struct attribute *max1363_event_attributes[] = { 1009 &iio_dev_attr_sampling_frequency.dev_attr.attr, 1010 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1011 NULL, 1012 }; 1013 1014 static struct attribute_group max1363_event_attribute_group = { 1015 .attrs = max1363_event_attributes, 1016 .name = "events", 1017 }; 1018 1019 static int max1363_update_scan_mode(struct iio_dev *indio_dev, 1020 const unsigned long *scan_mask) 1021 { 1022 struct max1363_state *st = iio_priv(indio_dev); 1023 1024 /* 1025 * Need to figure out the current mode based upon the requested 1026 * scan mask in iio_dev 1027 */ 1028 st->current_mode = max1363_match_mode(scan_mask, st->chip_info); 1029 if (!st->current_mode) 1030 return -EINVAL; 1031 max1363_set_scan_mode(st); 1032 return 0; 1033 } 1034 1035 static const struct iio_info max1238_info = { 1036 .read_raw = &max1363_read_raw, 1037 .driver_module = THIS_MODULE, 1038 .update_scan_mode = &max1363_update_scan_mode, 1039 }; 1040 1041 static const struct iio_info max1363_info = { 1042 .read_event_value_new = &max1363_read_thresh, 1043 .write_event_value_new = &max1363_write_thresh, 1044 .read_event_config_new = &max1363_read_event_config, 1045 .write_event_config_new = &max1363_write_event_config, 1046 .read_raw = &max1363_read_raw, 1047 .update_scan_mode = &max1363_update_scan_mode, 1048 .driver_module = THIS_MODULE, 1049 .event_attrs = &max1363_event_attribute_group, 1050 }; 1051 1052 /* max1363 and max1368 tested - rest from data sheet */ 1053 static const struct max1363_chip_info max1363_chip_info_tbl[] = { 1054 [max1361] = { 1055 .bits = 10, 1056 .int_vref_mv = 2048, 1057 .mode_list = max1363_mode_list, 1058 .num_modes = ARRAY_SIZE(max1363_mode_list), 1059 .default_mode = s0to3, 1060 .channels = max1361_channels, 1061 .num_channels = ARRAY_SIZE(max1361_channels), 1062 .info = &max1363_info, 1063 }, 1064 [max1362] = { 1065 .bits = 10, 1066 .int_vref_mv = 4096, 1067 .mode_list = max1363_mode_list, 1068 .num_modes = ARRAY_SIZE(max1363_mode_list), 1069 .default_mode = s0to3, 1070 .channels = max1361_channels, 1071 .num_channels = ARRAY_SIZE(max1361_channels), 1072 .info = &max1363_info, 1073 }, 1074 [max1363] = { 1075 .bits = 12, 1076 .int_vref_mv = 2048, 1077 .mode_list = max1363_mode_list, 1078 .num_modes = ARRAY_SIZE(max1363_mode_list), 1079 .default_mode = s0to3, 1080 .channels = max1363_channels, 1081 .num_channels = ARRAY_SIZE(max1363_channels), 1082 .info = &max1363_info, 1083 }, 1084 [max1364] = { 1085 .bits = 12, 1086 .int_vref_mv = 4096, 1087 .mode_list = max1363_mode_list, 1088 .num_modes = ARRAY_SIZE(max1363_mode_list), 1089 .default_mode = s0to3, 1090 .channels = max1363_channels, 1091 .num_channels = ARRAY_SIZE(max1363_channels), 1092 .info = &max1363_info, 1093 }, 1094 [max1036] = { 1095 .bits = 8, 1096 .int_vref_mv = 4096, 1097 .mode_list = max1236_mode_list, 1098 .num_modes = ARRAY_SIZE(max1236_mode_list), 1099 .default_mode = s0to3, 1100 .info = &max1238_info, 1101 .channels = max1036_channels, 1102 .num_channels = ARRAY_SIZE(max1036_channels), 1103 }, 1104 [max1037] = { 1105 .bits = 8, 1106 .int_vref_mv = 2048, 1107 .mode_list = max1236_mode_list, 1108 .num_modes = ARRAY_SIZE(max1236_mode_list), 1109 .default_mode = s0to3, 1110 .info = &max1238_info, 1111 .channels = max1036_channels, 1112 .num_channels = ARRAY_SIZE(max1036_channels), 1113 }, 1114 [max1038] = { 1115 .bits = 8, 1116 .int_vref_mv = 4096, 1117 .mode_list = max1238_mode_list, 1118 .num_modes = ARRAY_SIZE(max1238_mode_list), 1119 .default_mode = s0to11, 1120 .info = &max1238_info, 1121 .channels = max1038_channels, 1122 .num_channels = ARRAY_SIZE(max1038_channels), 1123 }, 1124 [max1039] = { 1125 .bits = 8, 1126 .int_vref_mv = 2048, 1127 .mode_list = max1238_mode_list, 1128 .num_modes = ARRAY_SIZE(max1238_mode_list), 1129 .default_mode = s0to11, 1130 .info = &max1238_info, 1131 .channels = max1038_channels, 1132 .num_channels = ARRAY_SIZE(max1038_channels), 1133 }, 1134 [max1136] = { 1135 .bits = 10, 1136 .int_vref_mv = 4096, 1137 .mode_list = max1236_mode_list, 1138 .num_modes = ARRAY_SIZE(max1236_mode_list), 1139 .default_mode = s0to3, 1140 .info = &max1238_info, 1141 .channels = max1136_channels, 1142 .num_channels = ARRAY_SIZE(max1136_channels), 1143 }, 1144 [max1137] = { 1145 .bits = 10, 1146 .int_vref_mv = 2048, 1147 .mode_list = max1236_mode_list, 1148 .num_modes = ARRAY_SIZE(max1236_mode_list), 1149 .default_mode = s0to3, 1150 .info = &max1238_info, 1151 .channels = max1136_channels, 1152 .num_channels = ARRAY_SIZE(max1136_channels), 1153 }, 1154 [max1138] = { 1155 .bits = 10, 1156 .int_vref_mv = 4096, 1157 .mode_list = max1238_mode_list, 1158 .num_modes = ARRAY_SIZE(max1238_mode_list), 1159 .default_mode = s0to11, 1160 .info = &max1238_info, 1161 .channels = max1138_channels, 1162 .num_channels = ARRAY_SIZE(max1138_channels), 1163 }, 1164 [max1139] = { 1165 .bits = 10, 1166 .int_vref_mv = 2048, 1167 .mode_list = max1238_mode_list, 1168 .num_modes = ARRAY_SIZE(max1238_mode_list), 1169 .default_mode = s0to11, 1170 .info = &max1238_info, 1171 .channels = max1138_channels, 1172 .num_channels = ARRAY_SIZE(max1138_channels), 1173 }, 1174 [max1236] = { 1175 .bits = 12, 1176 .int_vref_mv = 4096, 1177 .mode_list = max1236_mode_list, 1178 .num_modes = ARRAY_SIZE(max1236_mode_list), 1179 .default_mode = s0to3, 1180 .info = &max1238_info, 1181 .channels = max1236_channels, 1182 .num_channels = ARRAY_SIZE(max1236_channels), 1183 }, 1184 [max1237] = { 1185 .bits = 12, 1186 .int_vref_mv = 2048, 1187 .mode_list = max1236_mode_list, 1188 .num_modes = ARRAY_SIZE(max1236_mode_list), 1189 .default_mode = s0to3, 1190 .info = &max1238_info, 1191 .channels = max1236_channels, 1192 .num_channels = ARRAY_SIZE(max1236_channels), 1193 }, 1194 [max1238] = { 1195 .bits = 12, 1196 .int_vref_mv = 4096, 1197 .mode_list = max1238_mode_list, 1198 .num_modes = ARRAY_SIZE(max1238_mode_list), 1199 .default_mode = s0to11, 1200 .info = &max1238_info, 1201 .channels = max1238_channels, 1202 .num_channels = ARRAY_SIZE(max1238_channels), 1203 }, 1204 [max1239] = { 1205 .bits = 12, 1206 .int_vref_mv = 2048, 1207 .mode_list = max1238_mode_list, 1208 .num_modes = ARRAY_SIZE(max1238_mode_list), 1209 .default_mode = s0to11, 1210 .info = &max1238_info, 1211 .channels = max1238_channels, 1212 .num_channels = ARRAY_SIZE(max1238_channels), 1213 }, 1214 [max11600] = { 1215 .bits = 8, 1216 .int_vref_mv = 4096, 1217 .mode_list = max11607_mode_list, 1218 .num_modes = ARRAY_SIZE(max11607_mode_list), 1219 .default_mode = s0to3, 1220 .info = &max1238_info, 1221 .channels = max1036_channels, 1222 .num_channels = ARRAY_SIZE(max1036_channels), 1223 }, 1224 [max11601] = { 1225 .bits = 8, 1226 .int_vref_mv = 2048, 1227 .mode_list = max11607_mode_list, 1228 .num_modes = ARRAY_SIZE(max11607_mode_list), 1229 .default_mode = s0to3, 1230 .info = &max1238_info, 1231 .channels = max1036_channels, 1232 .num_channels = ARRAY_SIZE(max1036_channels), 1233 }, 1234 [max11602] = { 1235 .bits = 8, 1236 .int_vref_mv = 4096, 1237 .mode_list = max11608_mode_list, 1238 .num_modes = ARRAY_SIZE(max11608_mode_list), 1239 .default_mode = s0to7, 1240 .info = &max1238_info, 1241 .channels = max11602_channels, 1242 .num_channels = ARRAY_SIZE(max11602_channels), 1243 }, 1244 [max11603] = { 1245 .bits = 8, 1246 .int_vref_mv = 2048, 1247 .mode_list = max11608_mode_list, 1248 .num_modes = ARRAY_SIZE(max11608_mode_list), 1249 .default_mode = s0to7, 1250 .info = &max1238_info, 1251 .channels = max11602_channels, 1252 .num_channels = ARRAY_SIZE(max11602_channels), 1253 }, 1254 [max11604] = { 1255 .bits = 8, 1256 .int_vref_mv = 4098, 1257 .mode_list = max1238_mode_list, 1258 .num_modes = ARRAY_SIZE(max1238_mode_list), 1259 .default_mode = s0to11, 1260 .info = &max1238_info, 1261 .channels = max1238_channels, 1262 .num_channels = ARRAY_SIZE(max1238_channels), 1263 }, 1264 [max11605] = { 1265 .bits = 8, 1266 .int_vref_mv = 2048, 1267 .mode_list = max1238_mode_list, 1268 .num_modes = ARRAY_SIZE(max1238_mode_list), 1269 .default_mode = s0to11, 1270 .info = &max1238_info, 1271 .channels = max1238_channels, 1272 .num_channels = ARRAY_SIZE(max1238_channels), 1273 }, 1274 [max11606] = { 1275 .bits = 10, 1276 .int_vref_mv = 4096, 1277 .mode_list = max11607_mode_list, 1278 .num_modes = ARRAY_SIZE(max11607_mode_list), 1279 .default_mode = s0to3, 1280 .info = &max1238_info, 1281 .channels = max1136_channels, 1282 .num_channels = ARRAY_SIZE(max1136_channels), 1283 }, 1284 [max11607] = { 1285 .bits = 10, 1286 .int_vref_mv = 2048, 1287 .mode_list = max11607_mode_list, 1288 .num_modes = ARRAY_SIZE(max11607_mode_list), 1289 .default_mode = s0to3, 1290 .info = &max1238_info, 1291 .channels = max1136_channels, 1292 .num_channels = ARRAY_SIZE(max1136_channels), 1293 }, 1294 [max11608] = { 1295 .bits = 10, 1296 .int_vref_mv = 4096, 1297 .mode_list = max11608_mode_list, 1298 .num_modes = ARRAY_SIZE(max11608_mode_list), 1299 .default_mode = s0to7, 1300 .info = &max1238_info, 1301 .channels = max11608_channels, 1302 .num_channels = ARRAY_SIZE(max11608_channels), 1303 }, 1304 [max11609] = { 1305 .bits = 10, 1306 .int_vref_mv = 2048, 1307 .mode_list = max11608_mode_list, 1308 .num_modes = ARRAY_SIZE(max11608_mode_list), 1309 .default_mode = s0to7, 1310 .info = &max1238_info, 1311 .channels = max11608_channels, 1312 .num_channels = ARRAY_SIZE(max11608_channels), 1313 }, 1314 [max11610] = { 1315 .bits = 10, 1316 .int_vref_mv = 4098, 1317 .mode_list = max1238_mode_list, 1318 .num_modes = ARRAY_SIZE(max1238_mode_list), 1319 .default_mode = s0to11, 1320 .info = &max1238_info, 1321 .channels = max1238_channels, 1322 .num_channels = ARRAY_SIZE(max1238_channels), 1323 }, 1324 [max11611] = { 1325 .bits = 10, 1326 .int_vref_mv = 2048, 1327 .mode_list = max1238_mode_list, 1328 .num_modes = ARRAY_SIZE(max1238_mode_list), 1329 .default_mode = s0to11, 1330 .info = &max1238_info, 1331 .channels = max1238_channels, 1332 .num_channels = ARRAY_SIZE(max1238_channels), 1333 }, 1334 [max11612] = { 1335 .bits = 12, 1336 .int_vref_mv = 4096, 1337 .mode_list = max11607_mode_list, 1338 .num_modes = ARRAY_SIZE(max11607_mode_list), 1339 .default_mode = s0to3, 1340 .info = &max1238_info, 1341 .channels = max1363_channels, 1342 .num_channels = ARRAY_SIZE(max1363_channels), 1343 }, 1344 [max11613] = { 1345 .bits = 12, 1346 .int_vref_mv = 2048, 1347 .mode_list = max11607_mode_list, 1348 .num_modes = ARRAY_SIZE(max11607_mode_list), 1349 .default_mode = s0to3, 1350 .info = &max1238_info, 1351 .channels = max1363_channels, 1352 .num_channels = ARRAY_SIZE(max1363_channels), 1353 }, 1354 [max11614] = { 1355 .bits = 12, 1356 .int_vref_mv = 4096, 1357 .mode_list = max11608_mode_list, 1358 .num_modes = ARRAY_SIZE(max11608_mode_list), 1359 .default_mode = s0to7, 1360 .info = &max1238_info, 1361 .channels = max11614_channels, 1362 .num_channels = ARRAY_SIZE(max11614_channels), 1363 }, 1364 [max11615] = { 1365 .bits = 12, 1366 .int_vref_mv = 2048, 1367 .mode_list = max11608_mode_list, 1368 .num_modes = ARRAY_SIZE(max11608_mode_list), 1369 .default_mode = s0to7, 1370 .info = &max1238_info, 1371 .channels = max11614_channels, 1372 .num_channels = ARRAY_SIZE(max11614_channels), 1373 }, 1374 [max11616] = { 1375 .bits = 12, 1376 .int_vref_mv = 4098, 1377 .mode_list = max1238_mode_list, 1378 .num_modes = ARRAY_SIZE(max1238_mode_list), 1379 .default_mode = s0to11, 1380 .info = &max1238_info, 1381 .channels = max1238_channels, 1382 .num_channels = ARRAY_SIZE(max1238_channels), 1383 }, 1384 [max11617] = { 1385 .bits = 12, 1386 .int_vref_mv = 2048, 1387 .mode_list = max1238_mode_list, 1388 .num_modes = ARRAY_SIZE(max1238_mode_list), 1389 .default_mode = s0to11, 1390 .info = &max1238_info, 1391 .channels = max1238_channels, 1392 .num_channels = ARRAY_SIZE(max1238_channels), 1393 }, 1394 [max11644] = { 1395 .bits = 12, 1396 .int_vref_mv = 2048, 1397 .mode_list = max11644_mode_list, 1398 .num_modes = ARRAY_SIZE(max11644_mode_list), 1399 .default_mode = s0to1, 1400 .info = &max1238_info, 1401 .channels = max11644_channels, 1402 .num_channels = ARRAY_SIZE(max11644_channels), 1403 }, 1404 [max11645] = { 1405 .bits = 12, 1406 .int_vref_mv = 4096, 1407 .mode_list = max11644_mode_list, 1408 .num_modes = ARRAY_SIZE(max11644_mode_list), 1409 .default_mode = s0to1, 1410 .info = &max1238_info, 1411 .channels = max11644_channels, 1412 .num_channels = ARRAY_SIZE(max11644_channels), 1413 }, 1414 [max11646] = { 1415 .bits = 10, 1416 .int_vref_mv = 2048, 1417 .mode_list = max11644_mode_list, 1418 .num_modes = ARRAY_SIZE(max11644_mode_list), 1419 .default_mode = s0to1, 1420 .info = &max1238_info, 1421 .channels = max11646_channels, 1422 .num_channels = ARRAY_SIZE(max11646_channels), 1423 }, 1424 [max11647] = { 1425 .bits = 10, 1426 .int_vref_mv = 4096, 1427 .mode_list = max11644_mode_list, 1428 .num_modes = ARRAY_SIZE(max11644_mode_list), 1429 .default_mode = s0to1, 1430 .info = &max1238_info, 1431 .channels = max11646_channels, 1432 .num_channels = ARRAY_SIZE(max11646_channels), 1433 }, 1434 }; 1435 1436 static int max1363_initial_setup(struct max1363_state *st) 1437 { 1438 st->setupbyte = MAX1363_SETUP_INT_CLOCK 1439 | MAX1363_SETUP_UNIPOLAR 1440 | MAX1363_SETUP_NORESET; 1441 1442 if (st->vref) 1443 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF; 1444 else 1445 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF 1446 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT; 1447 1448 /* Set scan mode writes the config anyway so wait until then */ 1449 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte); 1450 st->current_mode = &max1363_mode_table[st->chip_info->default_mode]; 1451 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte); 1452 1453 return max1363_set_scan_mode(st); 1454 } 1455 1456 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev) 1457 { 1458 struct max1363_state *st = iio_priv(indio_dev); 1459 unsigned long *masks; 1460 int i; 1461 1462 masks = devm_kzalloc(&indio_dev->dev, 1463 BITS_TO_LONGS(MAX1363_MAX_CHANNELS) * sizeof(long) * 1464 (st->chip_info->num_modes + 1), GFP_KERNEL); 1465 if (!masks) 1466 return -ENOMEM; 1467 1468 for (i = 0; i < st->chip_info->num_modes; i++) 1469 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i, 1470 max1363_mode_table[st->chip_info->mode_list[i]] 1471 .modemask, MAX1363_MAX_CHANNELS); 1472 1473 indio_dev->available_scan_masks = masks; 1474 1475 return 0; 1476 } 1477 1478 static irqreturn_t max1363_trigger_handler(int irq, void *p) 1479 { 1480 struct iio_poll_func *pf = p; 1481 struct iio_dev *indio_dev = pf->indio_dev; 1482 struct max1363_state *st = iio_priv(indio_dev); 1483 __u8 *rxbuf; 1484 int b_sent; 1485 size_t d_size; 1486 unsigned long numvals = bitmap_weight(st->current_mode->modemask, 1487 MAX1363_MAX_CHANNELS); 1488 1489 /* Ensure the timestamp is 8 byte aligned */ 1490 if (st->chip_info->bits != 8) 1491 d_size = numvals*2; 1492 else 1493 d_size = numvals; 1494 if (indio_dev->scan_timestamp) { 1495 d_size += sizeof(s64); 1496 if (d_size % sizeof(s64)) 1497 d_size += sizeof(s64) - (d_size % sizeof(s64)); 1498 } 1499 /* Monitor mode prevents reading. Whilst not currently implemented 1500 * might as well have this test in here in the meantime as it does 1501 * no harm. 1502 */ 1503 if (numvals == 0) 1504 goto done; 1505 1506 rxbuf = kmalloc(d_size, GFP_KERNEL); 1507 if (rxbuf == NULL) 1508 goto done; 1509 if (st->chip_info->bits != 8) 1510 b_sent = st->recv(st->client, rxbuf, numvals * 2); 1511 else 1512 b_sent = st->recv(st->client, rxbuf, numvals); 1513 if (b_sent < 0) 1514 goto done_free; 1515 1516 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf, iio_get_time_ns()); 1517 1518 done_free: 1519 kfree(rxbuf); 1520 done: 1521 iio_trigger_notify_done(indio_dev->trig); 1522 1523 return IRQ_HANDLED; 1524 } 1525 1526 static int max1363_probe(struct i2c_client *client, 1527 const struct i2c_device_id *id) 1528 { 1529 int ret; 1530 struct max1363_state *st; 1531 struct iio_dev *indio_dev; 1532 struct regulator *vref; 1533 1534 indio_dev = devm_iio_device_alloc(&client->dev, 1535 sizeof(struct max1363_state)); 1536 if (!indio_dev) 1537 return -ENOMEM; 1538 1539 indio_dev->dev.of_node = client->dev.of_node; 1540 ret = iio_map_array_register(indio_dev, client->dev.platform_data); 1541 if (ret < 0) 1542 return ret; 1543 1544 st = iio_priv(indio_dev); 1545 1546 st->reg = devm_regulator_get(&client->dev, "vcc"); 1547 if (IS_ERR(st->reg)) { 1548 ret = PTR_ERR(st->reg); 1549 goto error_unregister_map; 1550 } 1551 1552 ret = regulator_enable(st->reg); 1553 if (ret) 1554 goto error_unregister_map; 1555 1556 /* this is only used for device removal purposes */ 1557 i2c_set_clientdata(client, indio_dev); 1558 1559 st->chip_info = &max1363_chip_info_tbl[id->driver_data]; 1560 st->client = client; 1561 1562 st->vref_uv = st->chip_info->int_vref_mv * 1000; 1563 vref = devm_regulator_get(&client->dev, "vref"); 1564 if (!IS_ERR(vref)) { 1565 int vref_uv; 1566 1567 ret = regulator_enable(vref); 1568 if (ret) 1569 goto error_disable_reg; 1570 st->vref = vref; 1571 vref_uv = regulator_get_voltage(vref); 1572 if (vref_uv <= 0) { 1573 ret = -EINVAL; 1574 goto error_disable_reg; 1575 } 1576 st->vref_uv = vref_uv; 1577 } 1578 1579 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1580 st->send = i2c_master_send; 1581 st->recv = i2c_master_recv; 1582 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE) 1583 && st->chip_info->bits == 8) { 1584 st->send = max1363_smbus_send; 1585 st->recv = max1363_smbus_recv; 1586 } else { 1587 ret = -EOPNOTSUPP; 1588 goto error_disable_reg; 1589 } 1590 1591 ret = max1363_alloc_scan_masks(indio_dev); 1592 if (ret) 1593 goto error_disable_reg; 1594 1595 /* Establish that the iio_dev is a child of the i2c device */ 1596 indio_dev->dev.parent = &client->dev; 1597 indio_dev->name = id->name; 1598 indio_dev->channels = st->chip_info->channels; 1599 indio_dev->num_channels = st->chip_info->num_channels; 1600 indio_dev->info = st->chip_info->info; 1601 indio_dev->modes = INDIO_DIRECT_MODE; 1602 ret = max1363_initial_setup(st); 1603 if (ret < 0) 1604 goto error_disable_reg; 1605 1606 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1607 &max1363_trigger_handler, NULL); 1608 if (ret) 1609 goto error_disable_reg; 1610 1611 if (client->irq) { 1612 ret = devm_request_threaded_irq(&client->dev, st->client->irq, 1613 NULL, 1614 &max1363_event_handler, 1615 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1616 "max1363_event", 1617 indio_dev); 1618 1619 if (ret) 1620 goto error_uninit_buffer; 1621 } 1622 1623 ret = iio_device_register(indio_dev); 1624 if (ret < 0) 1625 goto error_uninit_buffer; 1626 1627 return 0; 1628 1629 error_uninit_buffer: 1630 iio_triggered_buffer_cleanup(indio_dev); 1631 error_disable_reg: 1632 if (st->vref) 1633 regulator_disable(st->vref); 1634 regulator_disable(st->reg); 1635 error_unregister_map: 1636 iio_map_array_unregister(indio_dev); 1637 return ret; 1638 } 1639 1640 static int max1363_remove(struct i2c_client *client) 1641 { 1642 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1643 struct max1363_state *st = iio_priv(indio_dev); 1644 1645 iio_device_unregister(indio_dev); 1646 iio_triggered_buffer_cleanup(indio_dev); 1647 if (st->vref) 1648 regulator_disable(st->vref); 1649 regulator_disable(st->reg); 1650 iio_map_array_unregister(indio_dev); 1651 1652 return 0; 1653 } 1654 1655 static const struct i2c_device_id max1363_id[] = { 1656 { "max1361", max1361 }, 1657 { "max1362", max1362 }, 1658 { "max1363", max1363 }, 1659 { "max1364", max1364 }, 1660 { "max1036", max1036 }, 1661 { "max1037", max1037 }, 1662 { "max1038", max1038 }, 1663 { "max1039", max1039 }, 1664 { "max1136", max1136 }, 1665 { "max1137", max1137 }, 1666 { "max1138", max1138 }, 1667 { "max1139", max1139 }, 1668 { "max1236", max1236 }, 1669 { "max1237", max1237 }, 1670 { "max1238", max1238 }, 1671 { "max1239", max1239 }, 1672 { "max11600", max11600 }, 1673 { "max11601", max11601 }, 1674 { "max11602", max11602 }, 1675 { "max11603", max11603 }, 1676 { "max11604", max11604 }, 1677 { "max11605", max11605 }, 1678 { "max11606", max11606 }, 1679 { "max11607", max11607 }, 1680 { "max11608", max11608 }, 1681 { "max11609", max11609 }, 1682 { "max11610", max11610 }, 1683 { "max11611", max11611 }, 1684 { "max11612", max11612 }, 1685 { "max11613", max11613 }, 1686 { "max11614", max11614 }, 1687 { "max11615", max11615 }, 1688 { "max11616", max11616 }, 1689 { "max11617", max11617 }, 1690 {} 1691 }; 1692 1693 MODULE_DEVICE_TABLE(i2c, max1363_id); 1694 1695 static struct i2c_driver max1363_driver = { 1696 .driver = { 1697 .name = "max1363", 1698 }, 1699 .probe = max1363_probe, 1700 .remove = max1363_remove, 1701 .id_table = max1363_id, 1702 }; 1703 module_i2c_driver(max1363_driver); 1704 1705 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>"); 1706 MODULE_DESCRIPTION("Maxim 1363 ADC"); 1707 MODULE_LICENSE("GPL v2"); 1708