1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MAX11410 SPI ADC driver 4 * 5 * Copyright 2022 Analog Devices Inc. 6 */ 7 #include <asm-generic/unaligned.h> 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/spi/spi.h> 18 19 #include <linux/iio/buffer.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/trigger.h> 22 #include <linux/iio/trigger_consumer.h> 23 #include <linux/iio/triggered_buffer.h> 24 25 #define MAX11410_REG_CONV_START 0x01 26 #define MAX11410_CONV_TYPE_SINGLE 0x00 27 #define MAX11410_CONV_TYPE_CONTINUOUS 0x01 28 #define MAX11410_REG_CAL_START 0x03 29 #define MAX11410_CAL_START_SELF 0x00 30 #define MAX11410_CAL_START_PGA 0x01 31 #define MAX11410_REG_GPIO_CTRL(ch) ((ch) ? 0x05 : 0x04) 32 #define MAX11410_GPIO_INTRB 0xC1 33 #define MAX11410_REG_FILTER 0x08 34 #define MAX11410_FILTER_RATE_MASK GENMASK(3, 0) 35 #define MAX11410_FILTER_RATE_MAX 0x0F 36 #define MAX11410_FILTER_LINEF_MASK GENMASK(5, 4) 37 #define MAX11410_FILTER_50HZ BIT(5) 38 #define MAX11410_FILTER_60HZ BIT(4) 39 #define MAX11410_REG_CTRL 0x09 40 #define MAX11410_CTRL_REFSEL_MASK GENMASK(2, 0) 41 #define MAX11410_CTRL_VREFN_BUF_BIT BIT(3) 42 #define MAX11410_CTRL_VREFP_BUF_BIT BIT(4) 43 #define MAX11410_CTRL_FORMAT_BIT BIT(5) 44 #define MAX11410_CTRL_UNIPOLAR_BIT BIT(6) 45 #define MAX11410_REG_MUX_CTRL0 0x0B 46 #define MAX11410_REG_PGA 0x0E 47 #define MAX11410_PGA_GAIN_MASK GENMASK(2, 0) 48 #define MAX11410_PGA_SIG_PATH_MASK GENMASK(5, 4) 49 #define MAX11410_PGA_SIG_PATH_BUFFERED 0x00 50 #define MAX11410_PGA_SIG_PATH_BYPASS 0x01 51 #define MAX11410_PGA_SIG_PATH_PGA 0x02 52 #define MAX11410_REG_DATA0 0x30 53 #define MAX11410_REG_STATUS 0x38 54 #define MAX11410_STATUS_CONV_READY_BIT BIT(0) 55 #define MAX11410_STATUS_CAL_READY_BIT BIT(2) 56 57 #define MAX11410_REFSEL_AVDD_AGND 0x03 58 #define MAX11410_REFSEL_MAX 0x06 59 #define MAX11410_SIG_PATH_MAX 0x02 60 #define MAX11410_CHANNEL_INDEX_MAX 0x0A 61 #define MAX11410_AINP_AVDD 0x0A 62 #define MAX11410_AINN_GND 0x0A 63 64 #define MAX11410_CONVERSION_TIMEOUT_MS 2000 65 #define MAX11410_CALIB_TIMEOUT_MS 2000 66 67 #define MAX11410_SCALE_AVAIL_SIZE 8 68 69 enum max11410_filter { 70 MAX11410_FILTER_FIR5060, 71 MAX11410_FILTER_FIR50, 72 MAX11410_FILTER_FIR60, 73 MAX11410_FILTER_SINC4, 74 }; 75 76 static const u8 max11410_sampling_len[] = { 77 [MAX11410_FILTER_FIR5060] = 5, 78 [MAX11410_FILTER_FIR50] = 6, 79 [MAX11410_FILTER_FIR60] = 6, 80 [MAX11410_FILTER_SINC4] = 10, 81 }; 82 83 static const int max11410_sampling_rates[4][10][2] = { 84 [MAX11410_FILTER_FIR5060] = { 85 { 1, 100000 }, 86 { 2, 100000 }, 87 { 4, 200000 }, 88 { 8, 400000 }, 89 { 16, 800000 } 90 }, 91 [MAX11410_FILTER_FIR50] = { 92 { 1, 300000 }, 93 { 2, 700000 }, 94 { 5, 300000 }, 95 { 10, 700000 }, 96 { 21, 300000 }, 97 { 40 } 98 }, 99 [MAX11410_FILTER_FIR60] = { 100 { 1, 300000 }, 101 { 2, 700000 }, 102 { 5, 300000 }, 103 { 10, 700000 }, 104 { 21, 300000 }, 105 { 40 } 106 }, 107 [MAX11410_FILTER_SINC4] = { 108 { 4 }, 109 { 10 }, 110 { 20 }, 111 { 40 }, 112 { 60 }, 113 { 120 }, 114 { 240 }, 115 { 480 }, 116 { 960 }, 117 { 1920 } 118 } 119 }; 120 121 struct max11410_channel_config { 122 u32 settling_time_us; 123 u32 *scale_avail; 124 u8 refsel; 125 u8 sig_path; 126 u8 gain; 127 bool bipolar; 128 bool buffered_vrefp; 129 bool buffered_vrefn; 130 }; 131 132 struct max11410_state { 133 struct spi_device *spi_dev; 134 struct iio_trigger *trig; 135 struct completion completion; 136 struct mutex lock; /* Prevent changing channel config during sampling */ 137 struct regmap *regmap; 138 struct regulator *avdd; 139 struct regulator *vrefp[3]; 140 struct regulator *vrefn[3]; 141 struct max11410_channel_config *channels; 142 int irq; 143 struct { 144 u32 data __aligned(IIO_DMA_MINALIGN); 145 s64 ts __aligned(8); 146 } scan; 147 }; 148 149 static const struct iio_chan_spec chanspec_template = { 150 .type = IIO_VOLTAGE, 151 .indexed = 1, 152 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 153 BIT(IIO_CHAN_INFO_SCALE) | 154 BIT(IIO_CHAN_INFO_OFFSET), 155 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 156 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 157 .scan_type = { 158 .sign = 's', 159 .realbits = 24, 160 .storagebits = 32, 161 .endianness = IIO_LE, 162 }, 163 }; 164 165 static unsigned int max11410_reg_size(unsigned int reg) 166 { 167 /* Registers from 0x00 to 0x10 are 1 byte, the rest are 3 bytes long. */ 168 return reg <= 0x10 ? 1 : 3; 169 } 170 171 static int max11410_write_reg(struct max11410_state *st, unsigned int reg, 172 unsigned int val) 173 { 174 /* This driver only needs to write 8-bit registers */ 175 if (max11410_reg_size(reg) != 1) 176 return -EINVAL; 177 178 return regmap_write(st->regmap, reg, val); 179 } 180 181 static int max11410_read_reg(struct max11410_state *st, unsigned int reg, 182 int *val) 183 { 184 int ret; 185 186 if (max11410_reg_size(reg) == 3) { 187 ret = regmap_bulk_read(st->regmap, reg, &st->scan.data, 3); 188 if (ret) 189 return ret; 190 191 *val = get_unaligned_be24(&st->scan.data); 192 return 0; 193 } 194 195 return regmap_read(st->regmap, reg, val); 196 } 197 198 static struct regulator *max11410_get_vrefp(struct max11410_state *st, 199 u8 refsel) 200 { 201 refsel = refsel % 4; 202 if (refsel == 3) 203 return st->avdd; 204 205 return st->vrefp[refsel]; 206 } 207 208 static struct regulator *max11410_get_vrefn(struct max11410_state *st, 209 u8 refsel) 210 { 211 if (refsel > 2) 212 return NULL; 213 214 return st->vrefn[refsel]; 215 } 216 217 static const struct regmap_config regmap_config = { 218 .reg_bits = 8, 219 .val_bits = 8, 220 .max_register = 0x39, 221 }; 222 223 static ssize_t max11410_notch_en_show(struct device *dev, 224 struct device_attribute *devattr, 225 char *buf) 226 { 227 struct iio_dev *indio_dev = dev_get_drvdata(dev); 228 struct max11410_state *state = iio_priv(indio_dev); 229 struct iio_dev_attr *iio_attr = to_iio_dev_attr(devattr); 230 unsigned int val; 231 int ret; 232 233 ret = max11410_read_reg(state, MAX11410_REG_FILTER, &val); 234 if (ret) 235 return ret; 236 237 switch (iio_attr->address) { 238 case 0: 239 val = !FIELD_GET(MAX11410_FILTER_50HZ, val); 240 break; 241 case 1: 242 val = !FIELD_GET(MAX11410_FILTER_60HZ, val); 243 break; 244 case 2: 245 val = FIELD_GET(MAX11410_FILTER_LINEF_MASK, val) == 3; 246 break; 247 default: 248 return -EINVAL; 249 } 250 251 return sysfs_emit(buf, "%d\n", val); 252 } 253 254 static ssize_t max11410_notch_en_store(struct device *dev, 255 struct device_attribute *devattr, 256 const char *buf, size_t count) 257 { 258 struct iio_dev_attr *iio_attr = to_iio_dev_attr(devattr); 259 struct iio_dev *indio_dev = dev_get_drvdata(dev); 260 struct max11410_state *state = iio_priv(indio_dev); 261 unsigned int filter_bits; 262 bool enable; 263 int ret; 264 265 ret = kstrtobool(buf, &enable); 266 if (ret) 267 return ret; 268 269 switch (iio_attr->address) { 270 case 0: 271 filter_bits = MAX11410_FILTER_50HZ; 272 break; 273 case 1: 274 filter_bits = MAX11410_FILTER_60HZ; 275 break; 276 case 2: 277 default: 278 filter_bits = MAX11410_FILTER_50HZ | MAX11410_FILTER_60HZ; 279 enable = !enable; 280 break; 281 } 282 283 if (enable) 284 ret = regmap_clear_bits(state->regmap, MAX11410_REG_FILTER, 285 filter_bits); 286 else 287 ret = regmap_set_bits(state->regmap, MAX11410_REG_FILTER, 288 filter_bits); 289 290 if (ret) 291 return ret; 292 293 return count; 294 } 295 296 static ssize_t in_voltage_filter2_notch_center_show(struct device *dev, 297 struct device_attribute *devattr, 298 char *buf) 299 { 300 struct iio_dev *indio_dev = dev_get_drvdata(dev); 301 struct max11410_state *state = iio_priv(indio_dev); 302 int ret, reg, rate, filter; 303 304 ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®); 305 if (ret) 306 return ret; 307 308 rate = FIELD_GET(MAX11410_FILTER_RATE_MASK, reg); 309 rate = clamp_val(rate, 0, 310 max11410_sampling_len[MAX11410_FILTER_SINC4] - 1); 311 filter = max11410_sampling_rates[MAX11410_FILTER_SINC4][rate][0]; 312 313 return sysfs_emit(buf, "%d\n", filter); 314 } 315 316 static IIO_CONST_ATTR(in_voltage_filter0_notch_center, "50"); 317 static IIO_CONST_ATTR(in_voltage_filter1_notch_center, "60"); 318 static IIO_DEVICE_ATTR_RO(in_voltage_filter2_notch_center, 2); 319 320 static IIO_DEVICE_ATTR(in_voltage_filter0_notch_en, 0644, 321 max11410_notch_en_show, max11410_notch_en_store, 0); 322 static IIO_DEVICE_ATTR(in_voltage_filter1_notch_en, 0644, 323 max11410_notch_en_show, max11410_notch_en_store, 1); 324 static IIO_DEVICE_ATTR(in_voltage_filter2_notch_en, 0644, 325 max11410_notch_en_show, max11410_notch_en_store, 2); 326 327 static struct attribute *max11410_attributes[] = { 328 &iio_const_attr_in_voltage_filter0_notch_center.dev_attr.attr, 329 &iio_const_attr_in_voltage_filter1_notch_center.dev_attr.attr, 330 &iio_dev_attr_in_voltage_filter2_notch_center.dev_attr.attr, 331 &iio_dev_attr_in_voltage_filter0_notch_en.dev_attr.attr, 332 &iio_dev_attr_in_voltage_filter1_notch_en.dev_attr.attr, 333 &iio_dev_attr_in_voltage_filter2_notch_en.dev_attr.attr, 334 NULL 335 }; 336 337 static const struct attribute_group max11410_attribute_group = { 338 .attrs = max11410_attributes, 339 }; 340 341 static int max11410_set_input_mux(struct max11410_state *st, u8 ainp, u8 ainn) 342 { 343 if (ainp > MAX11410_CHANNEL_INDEX_MAX || 344 ainn > MAX11410_CHANNEL_INDEX_MAX) 345 return -EINVAL; 346 347 return max11410_write_reg(st, MAX11410_REG_MUX_CTRL0, 348 (ainp << 4) | ainn); 349 } 350 351 static int max11410_configure_channel(struct max11410_state *st, 352 struct iio_chan_spec const *chan) 353 { 354 struct max11410_channel_config cfg = st->channels[chan->address]; 355 unsigned int regval; 356 int ret; 357 358 if (chan->differential) 359 ret = max11410_set_input_mux(st, chan->channel, chan->channel2); 360 else 361 ret = max11410_set_input_mux(st, chan->channel, 362 MAX11410_AINN_GND); 363 364 if (ret) 365 return ret; 366 367 regval = FIELD_PREP(MAX11410_CTRL_VREFP_BUF_BIT, cfg.buffered_vrefp) | 368 FIELD_PREP(MAX11410_CTRL_VREFN_BUF_BIT, cfg.buffered_vrefn) | 369 FIELD_PREP(MAX11410_CTRL_REFSEL_MASK, cfg.refsel) | 370 FIELD_PREP(MAX11410_CTRL_UNIPOLAR_BIT, cfg.bipolar ? 0 : 1); 371 ret = regmap_update_bits(st->regmap, MAX11410_REG_CTRL, 372 MAX11410_CTRL_REFSEL_MASK | 373 MAX11410_CTRL_VREFP_BUF_BIT | 374 MAX11410_CTRL_VREFN_BUF_BIT | 375 MAX11410_CTRL_UNIPOLAR_BIT, regval); 376 if (ret) 377 return ret; 378 379 regval = FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, cfg.sig_path) | 380 FIELD_PREP(MAX11410_PGA_GAIN_MASK, cfg.gain); 381 ret = regmap_write(st->regmap, MAX11410_REG_PGA, regval); 382 if (ret) 383 return ret; 384 385 if (cfg.settling_time_us) 386 fsleep(cfg.settling_time_us); 387 388 return 0; 389 } 390 391 static int max11410_sample(struct max11410_state *st, int *sample_raw, 392 struct iio_chan_spec const *chan) 393 { 394 int val, ret; 395 396 ret = max11410_configure_channel(st, chan); 397 if (ret) 398 return ret; 399 400 if (st->irq > 0) 401 reinit_completion(&st->completion); 402 403 /* Start Conversion */ 404 ret = max11410_write_reg(st, MAX11410_REG_CONV_START, 405 MAX11410_CONV_TYPE_SINGLE); 406 if (ret) 407 return ret; 408 409 if (st->irq > 0) { 410 /* Wait for an interrupt. */ 411 ret = wait_for_completion_timeout(&st->completion, 412 msecs_to_jiffies(MAX11410_CONVERSION_TIMEOUT_MS)); 413 if (!ret) 414 return -ETIMEDOUT; 415 } else { 416 int ret2; 417 418 /* Wait for status register Conversion Ready flag */ 419 ret = read_poll_timeout(max11410_read_reg, ret2, 420 ret2 || (val & MAX11410_STATUS_CONV_READY_BIT), 421 5000, MAX11410_CONVERSION_TIMEOUT_MS * 1000, 422 true, st, MAX11410_REG_STATUS, &val); 423 if (ret) 424 return ret; 425 if (ret2) 426 return ret2; 427 } 428 429 /* Read ADC Data */ 430 return max11410_read_reg(st, MAX11410_REG_DATA0, sample_raw); 431 } 432 433 static int max11410_get_scale(struct max11410_state *state, 434 struct max11410_channel_config cfg) 435 { 436 struct regulator *vrefp, *vrefn; 437 int scale; 438 439 vrefp = max11410_get_vrefp(state, cfg.refsel); 440 441 scale = regulator_get_voltage(vrefp) / 1000; 442 vrefn = max11410_get_vrefn(state, cfg.refsel); 443 if (vrefn) 444 scale -= regulator_get_voltage(vrefn) / 1000; 445 446 if (cfg.bipolar) 447 scale *= 2; 448 449 return scale >> cfg.gain; 450 } 451 452 static int max11410_read_raw(struct iio_dev *indio_dev, 453 struct iio_chan_spec const *chan, 454 int *val, int *val2, long info) 455 { 456 struct max11410_state *state = iio_priv(indio_dev); 457 struct max11410_channel_config cfg = state->channels[chan->address]; 458 int ret, reg_val, filter, rate; 459 460 switch (info) { 461 case IIO_CHAN_INFO_SCALE: 462 *val = max11410_get_scale(state, cfg); 463 *val2 = chan->scan_type.realbits; 464 return IIO_VAL_FRACTIONAL_LOG2; 465 case IIO_CHAN_INFO_OFFSET: 466 if (cfg.bipolar) 467 *val = -BIT(chan->scan_type.realbits - 1); 468 else 469 *val = 0; 470 471 return IIO_VAL_INT; 472 case IIO_CHAN_INFO_RAW: 473 ret = iio_device_claim_direct_mode(indio_dev); 474 if (ret) 475 return ret; 476 477 mutex_lock(&state->lock); 478 479 ret = max11410_sample(state, ®_val, chan); 480 481 mutex_unlock(&state->lock); 482 483 iio_device_release_direct_mode(indio_dev); 484 485 if (ret) 486 return ret; 487 488 *val = reg_val; 489 490 return IIO_VAL_INT; 491 case IIO_CHAN_INFO_SAMP_FREQ: 492 ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®_val); 493 if (ret) 494 return ret; 495 496 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val); 497 rate = reg_val & MAX11410_FILTER_RATE_MASK; 498 if (rate >= max11410_sampling_len[filter]) 499 rate = max11410_sampling_len[filter] - 1; 500 501 *val = max11410_sampling_rates[filter][rate][0]; 502 *val2 = max11410_sampling_rates[filter][rate][1]; 503 504 return IIO_VAL_INT_PLUS_MICRO; 505 } 506 return -EINVAL; 507 } 508 509 static int max11410_write_raw(struct iio_dev *indio_dev, 510 struct iio_chan_spec const *chan, 511 int val, int val2, long mask) 512 { 513 struct max11410_state *st = iio_priv(indio_dev); 514 int i, ret, reg_val, filter, gain; 515 u32 *scale_avail; 516 517 switch (mask) { 518 case IIO_CHAN_INFO_SCALE: 519 scale_avail = st->channels[chan->address].scale_avail; 520 if (!scale_avail) 521 return -EOPNOTSUPP; 522 523 /* Accept values in range 0.000001 <= scale < 1.000000 */ 524 if (val != 0 || val2 == 0) 525 return -EINVAL; 526 527 ret = iio_device_claim_direct_mode(indio_dev); 528 if (ret) 529 return ret; 530 531 /* Convert from INT_PLUS_MICRO to FRACTIONAL_LOG2 */ 532 val2 = val2 * DIV_ROUND_CLOSEST(BIT(24), 1000000); 533 val2 = DIV_ROUND_CLOSEST(scale_avail[0], val2); 534 gain = order_base_2(val2); 535 536 st->channels[chan->address].gain = clamp_val(gain, 0, 7); 537 538 iio_device_release_direct_mode(indio_dev); 539 540 return 0; 541 case IIO_CHAN_INFO_SAMP_FREQ: 542 ret = iio_device_claim_direct_mode(indio_dev); 543 if (ret) 544 return ret; 545 546 mutex_lock(&st->lock); 547 548 ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val); 549 if (ret) 550 goto out; 551 552 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val); 553 554 for (i = 0; i < max11410_sampling_len[filter]; ++i) { 555 if (val == max11410_sampling_rates[filter][i][0] && 556 val2 == max11410_sampling_rates[filter][i][1]) 557 break; 558 } 559 if (i == max11410_sampling_len[filter]) { 560 ret = -EINVAL; 561 goto out; 562 } 563 564 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER, 565 MAX11410_FILTER_RATE_MASK, i); 566 567 out: 568 mutex_unlock(&st->lock); 569 iio_device_release_direct_mode(indio_dev); 570 571 return ret; 572 default: 573 return -EINVAL; 574 } 575 } 576 577 static int max11410_read_avail(struct iio_dev *indio_dev, 578 struct iio_chan_spec const *chan, 579 const int **vals, int *type, int *length, 580 long info) 581 { 582 struct max11410_state *st = iio_priv(indio_dev); 583 struct max11410_channel_config cfg; 584 int ret, reg_val, filter; 585 586 switch (info) { 587 case IIO_CHAN_INFO_SAMP_FREQ: 588 ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val); 589 if (ret) 590 return ret; 591 592 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val); 593 594 *vals = (const int *)max11410_sampling_rates[filter]; 595 *length = max11410_sampling_len[filter] * 2; 596 *type = IIO_VAL_INT_PLUS_MICRO; 597 598 return IIO_AVAIL_LIST; 599 case IIO_CHAN_INFO_SCALE: 600 cfg = st->channels[chan->address]; 601 602 if (!cfg.scale_avail) 603 return -EINVAL; 604 605 *vals = cfg.scale_avail; 606 *length = MAX11410_SCALE_AVAIL_SIZE * 2; 607 *type = IIO_VAL_FRACTIONAL_LOG2; 608 609 return IIO_AVAIL_LIST; 610 } 611 return -EINVAL; 612 } 613 614 static const struct iio_info max11410_info = { 615 .read_raw = max11410_read_raw, 616 .write_raw = max11410_write_raw, 617 .read_avail = max11410_read_avail, 618 .attrs = &max11410_attribute_group, 619 }; 620 621 static irqreturn_t max11410_trigger_handler(int irq, void *p) 622 { 623 struct iio_poll_func *pf = p; 624 struct iio_dev *indio_dev = pf->indio_dev; 625 struct max11410_state *st = iio_priv(indio_dev); 626 int ret; 627 628 ret = max11410_read_reg(st, MAX11410_REG_DATA0, &st->scan.data); 629 if (ret) { 630 dev_err(&indio_dev->dev, "cannot read data\n"); 631 goto out; 632 } 633 634 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan, 635 iio_get_time_ns(indio_dev)); 636 637 out: 638 iio_trigger_notify_done(indio_dev->trig); 639 640 return IRQ_HANDLED; 641 } 642 643 static int max11410_buffer_postenable(struct iio_dev *indio_dev) 644 { 645 struct max11410_state *st = iio_priv(indio_dev); 646 int scan_ch, ret; 647 648 scan_ch = ffs(*indio_dev->active_scan_mask) - 1; 649 650 ret = max11410_configure_channel(st, &indio_dev->channels[scan_ch]); 651 if (ret) 652 return ret; 653 654 /* Start continuous conversion. */ 655 return max11410_write_reg(st, MAX11410_REG_CONV_START, 656 MAX11410_CONV_TYPE_CONTINUOUS); 657 } 658 659 static int max11410_buffer_predisable(struct iio_dev *indio_dev) 660 { 661 struct max11410_state *st = iio_priv(indio_dev); 662 663 /* Stop continuous conversion. */ 664 return max11410_write_reg(st, MAX11410_REG_CONV_START, 665 MAX11410_CONV_TYPE_SINGLE); 666 } 667 668 static const struct iio_buffer_setup_ops max11410_buffer_ops = { 669 .postenable = &max11410_buffer_postenable, 670 .predisable = &max11410_buffer_predisable, 671 .validate_scan_mask = &iio_validate_scan_mask_onehot, 672 }; 673 674 static const struct iio_trigger_ops max11410_trigger_ops = { 675 .validate_device = iio_trigger_validate_own_device, 676 }; 677 678 static irqreturn_t max11410_interrupt(int irq, void *dev_id) 679 { 680 struct iio_dev *indio_dev = dev_id; 681 struct max11410_state *st = iio_priv(indio_dev); 682 683 if (iio_buffer_enabled(indio_dev)) 684 iio_trigger_poll_chained(st->trig); 685 else 686 complete(&st->completion); 687 688 return IRQ_HANDLED; 689 }; 690 691 static int max11410_parse_channels(struct max11410_state *st, 692 struct iio_dev *indio_dev) 693 { 694 struct iio_chan_spec chanspec = chanspec_template; 695 struct device *dev = &st->spi_dev->dev; 696 struct max11410_channel_config *cfg; 697 struct iio_chan_spec *channels; 698 struct fwnode_handle *child; 699 u32 reference, sig_path; 700 const char *node_name; 701 u32 inputs[2], scale; 702 unsigned int num_ch; 703 int chan_idx = 0; 704 int ret, i; 705 706 num_ch = device_get_child_node_count(dev); 707 if (num_ch == 0) 708 return dev_err_probe(&indio_dev->dev, -ENODEV, 709 "FW has no channels defined\n"); 710 711 /* Reserve space for soft timestamp channel */ 712 num_ch++; 713 channels = devm_kcalloc(dev, num_ch, sizeof(*channels), GFP_KERNEL); 714 if (!channels) 715 return -ENOMEM; 716 717 st->channels = devm_kcalloc(dev, num_ch, sizeof(*st->channels), 718 GFP_KERNEL); 719 if (!st->channels) 720 return -ENOMEM; 721 722 device_for_each_child_node(dev, child) { 723 node_name = fwnode_get_name(child); 724 if (fwnode_property_present(child, "diff-channels")) { 725 ret = fwnode_property_read_u32_array(child, 726 "diff-channels", 727 inputs, 728 ARRAY_SIZE(inputs)); 729 730 chanspec.differential = 1; 731 } else { 732 ret = fwnode_property_read_u32(child, "reg", &inputs[0]); 733 734 inputs[1] = 0; 735 chanspec.differential = 0; 736 } 737 if (ret) { 738 fwnode_handle_put(child); 739 return ret; 740 } 741 742 if (inputs[0] > MAX11410_CHANNEL_INDEX_MAX || 743 inputs[1] > MAX11410_CHANNEL_INDEX_MAX) { 744 fwnode_handle_put(child); 745 return dev_err_probe(&indio_dev->dev, -EINVAL, 746 "Invalid channel index for %s, should be less than %d\n", 747 node_name, 748 MAX11410_CHANNEL_INDEX_MAX + 1); 749 } 750 751 cfg = &st->channels[chan_idx]; 752 753 reference = MAX11410_REFSEL_AVDD_AGND; 754 fwnode_property_read_u32(child, "adi,reference", &reference); 755 if (reference > MAX11410_REFSEL_MAX) { 756 fwnode_handle_put(child); 757 return dev_err_probe(&indio_dev->dev, -EINVAL, 758 "Invalid adi,reference value for %s, should be less than %d.\n", 759 node_name, MAX11410_REFSEL_MAX + 1); 760 } 761 762 if (!max11410_get_vrefp(st, reference) || 763 (!max11410_get_vrefn(st, reference) && reference <= 2)) { 764 fwnode_handle_put(child); 765 return dev_err_probe(&indio_dev->dev, -EINVAL, 766 "Invalid VREF configuration for %s, either specify corresponding VREF regulators or change adi,reference property.\n", 767 node_name); 768 } 769 770 sig_path = MAX11410_PGA_SIG_PATH_BUFFERED; 771 fwnode_property_read_u32(child, "adi,input-mode", &sig_path); 772 if (sig_path > MAX11410_SIG_PATH_MAX) { 773 fwnode_handle_put(child); 774 return dev_err_probe(&indio_dev->dev, -EINVAL, 775 "Invalid adi,input-mode value for %s, should be less than %d.\n", 776 node_name, MAX11410_SIG_PATH_MAX + 1); 777 } 778 779 fwnode_property_read_u32(child, "settling-time-us", 780 &cfg->settling_time_us); 781 cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 782 cfg->buffered_vrefp = fwnode_property_read_bool(child, "adi,buffered-vrefp"); 783 cfg->buffered_vrefn = fwnode_property_read_bool(child, "adi,buffered-vrefn"); 784 cfg->refsel = reference; 785 cfg->sig_path = sig_path; 786 cfg->gain = 0; 787 788 /* Enable scale_available property if input mode is PGA */ 789 if (sig_path == MAX11410_PGA_SIG_PATH_PGA) { 790 __set_bit(IIO_CHAN_INFO_SCALE, 791 &chanspec.info_mask_separate_available); 792 cfg->scale_avail = devm_kcalloc(dev, MAX11410_SCALE_AVAIL_SIZE * 2, 793 sizeof(*cfg->scale_avail), 794 GFP_KERNEL); 795 if (!cfg->scale_avail) { 796 fwnode_handle_put(child); 797 return -ENOMEM; 798 } 799 800 scale = max11410_get_scale(st, *cfg); 801 for (i = 0; i < MAX11410_SCALE_AVAIL_SIZE; i++) { 802 cfg->scale_avail[2 * i] = scale >> i; 803 cfg->scale_avail[2 * i + 1] = chanspec.scan_type.realbits; 804 } 805 } else { 806 __clear_bit(IIO_CHAN_INFO_SCALE, 807 &chanspec.info_mask_separate_available); 808 } 809 810 chanspec.address = chan_idx; 811 chanspec.scan_index = chan_idx; 812 chanspec.channel = inputs[0]; 813 chanspec.channel2 = inputs[1]; 814 815 channels[chan_idx] = chanspec; 816 chan_idx++; 817 } 818 819 channels[chan_idx] = (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(chan_idx); 820 821 indio_dev->num_channels = chan_idx + 1; 822 indio_dev->channels = channels; 823 824 return 0; 825 } 826 827 static void max11410_disable_reg(void *reg) 828 { 829 regulator_disable(reg); 830 } 831 832 static int max11410_init_vref(struct device *dev, 833 struct regulator **vref, 834 const char *id) 835 { 836 struct regulator *reg; 837 int ret; 838 839 reg = devm_regulator_get_optional(dev, id); 840 if (PTR_ERR(reg) == -ENODEV) { 841 *vref = NULL; 842 return 0; 843 } else if (IS_ERR(reg)) { 844 return PTR_ERR(reg); 845 } 846 ret = regulator_enable(reg); 847 if (ret) 848 return dev_err_probe(dev, ret, 849 "Failed to enable regulator %s\n", id); 850 851 *vref = reg; 852 return devm_add_action_or_reset(dev, max11410_disable_reg, reg); 853 } 854 855 static int max11410_calibrate(struct max11410_state *st, u32 cal_type) 856 { 857 int ret, ret2, val; 858 859 ret = max11410_write_reg(st, MAX11410_REG_CAL_START, cal_type); 860 if (ret) 861 return ret; 862 863 /* Wait for status register Calibration Ready flag */ 864 ret = read_poll_timeout(max11410_read_reg, ret2, 865 ret2 || (val & MAX11410_STATUS_CAL_READY_BIT), 866 50000, MAX11410_CALIB_TIMEOUT_MS * 1000, true, 867 st, MAX11410_REG_STATUS, &val); 868 if (ret) 869 return ret; 870 871 return ret2; 872 } 873 874 static int max11410_self_calibrate(struct max11410_state *st) 875 { 876 int ret, i; 877 878 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER, 879 MAX11410_FILTER_RATE_MASK, 880 FIELD_PREP(MAX11410_FILTER_RATE_MASK, 881 MAX11410_FILTER_RATE_MAX)); 882 if (ret) 883 return ret; 884 885 ret = max11410_calibrate(st, MAX11410_CAL_START_SELF); 886 if (ret) 887 return ret; 888 889 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA, 890 MAX11410_PGA_SIG_PATH_MASK, 891 FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, 892 MAX11410_PGA_SIG_PATH_PGA)); 893 if (ret) 894 return ret; 895 896 /* PGA calibrations */ 897 for (i = 1; i < 8; ++i) { 898 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA, 899 MAX11410_PGA_GAIN_MASK, i); 900 if (ret) 901 return ret; 902 903 ret = max11410_calibrate(st, MAX11410_CAL_START_PGA); 904 if (ret) 905 return ret; 906 } 907 908 /* Cleanup */ 909 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA, 910 MAX11410_PGA_GAIN_MASK, 0); 911 if (ret) 912 return ret; 913 914 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER, 915 MAX11410_FILTER_RATE_MASK, 0); 916 if (ret) 917 return ret; 918 919 return regmap_write_bits(st->regmap, MAX11410_REG_PGA, 920 MAX11410_PGA_SIG_PATH_MASK, 921 FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, 922 MAX11410_PGA_SIG_PATH_BUFFERED)); 923 } 924 925 static int max11410_probe(struct spi_device *spi) 926 { 927 const char *vrefp_regs[] = { "vref0p", "vref1p", "vref2p" }; 928 const char *vrefn_regs[] = { "vref0n", "vref1n", "vref2n" }; 929 struct device *dev = &spi->dev; 930 struct max11410_state *st; 931 struct iio_dev *indio_dev; 932 int ret, irqs[2]; 933 int i; 934 935 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 936 if (!indio_dev) 937 return -ENOMEM; 938 939 st = iio_priv(indio_dev); 940 st->spi_dev = spi; 941 init_completion(&st->completion); 942 mutex_init(&st->lock); 943 944 indio_dev->name = "max11410"; 945 indio_dev->modes = INDIO_DIRECT_MODE; 946 indio_dev->info = &max11410_info; 947 948 st->regmap = devm_regmap_init_spi(spi, ®map_config); 949 if (IS_ERR(st->regmap)) 950 return dev_err_probe(dev, PTR_ERR(st->regmap), 951 "regmap initialization failed\n"); 952 953 ret = max11410_init_vref(dev, &st->avdd, "avdd"); 954 if (ret) 955 return ret; 956 957 for (i = 0; i < ARRAY_SIZE(vrefp_regs); i++) { 958 ret = max11410_init_vref(dev, &st->vrefp[i], vrefp_regs[i]); 959 if (ret) 960 return ret; 961 962 ret = max11410_init_vref(dev, &st->vrefn[i], vrefn_regs[i]); 963 if (ret) 964 return ret; 965 } 966 967 /* 968 * Regulators must be configured before parsing channels for 969 * validating "adi,reference" property of each channel. 970 */ 971 ret = max11410_parse_channels(st, indio_dev); 972 if (ret) 973 return ret; 974 975 irqs[0] = fwnode_irq_get_byname(dev_fwnode(dev), "gpio0"); 976 irqs[1] = fwnode_irq_get_byname(dev_fwnode(dev), "gpio1"); 977 978 if (irqs[0] > 0) { 979 st->irq = irqs[0]; 980 ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(0), 981 MAX11410_GPIO_INTRB); 982 } else if (irqs[1] > 0) { 983 st->irq = irqs[1]; 984 ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(1), 985 MAX11410_GPIO_INTRB); 986 } else if (spi->irq > 0) { 987 return dev_err_probe(dev, -ENODEV, 988 "no interrupt name specified"); 989 } 990 991 if (ret) 992 return ret; 993 994 ret = regmap_set_bits(st->regmap, MAX11410_REG_CTRL, 995 MAX11410_CTRL_FORMAT_BIT); 996 if (ret) 997 return ret; 998 999 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 1000 &max11410_trigger_handler, 1001 &max11410_buffer_ops); 1002 if (ret) 1003 return ret; 1004 1005 if (st->irq > 0) { 1006 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 1007 indio_dev->name, 1008 iio_device_id(indio_dev)); 1009 if (!st->trig) 1010 return -ENOMEM; 1011 1012 st->trig->ops = &max11410_trigger_ops; 1013 ret = devm_iio_trigger_register(dev, st->trig); 1014 if (ret) 1015 return ret; 1016 1017 ret = devm_request_threaded_irq(dev, st->irq, NULL, 1018 &max11410_interrupt, 1019 IRQF_ONESHOT, "max11410", 1020 indio_dev); 1021 if (ret) 1022 return ret; 1023 } 1024 1025 ret = max11410_self_calibrate(st); 1026 if (ret) 1027 return dev_err_probe(dev, ret, 1028 "cannot perform device self calibration\n"); 1029 1030 return devm_iio_device_register(dev, indio_dev); 1031 } 1032 1033 static const struct of_device_id max11410_spi_of_id[] = { 1034 { .compatible = "adi,max11410" }, 1035 { } 1036 }; 1037 MODULE_DEVICE_TABLE(of, max11410_spi_of_id); 1038 1039 static const struct spi_device_id max11410_id[] = { 1040 { "max11410" }, 1041 { } 1042 }; 1043 MODULE_DEVICE_TABLE(spi, max11410_id); 1044 1045 static struct spi_driver max11410_driver = { 1046 .driver = { 1047 .name = "max11410", 1048 .of_match_table = max11410_spi_of_id, 1049 }, 1050 .probe = max11410_probe, 1051 .id_table = max11410_id, 1052 }; 1053 module_spi_driver(max11410_driver); 1054 1055 MODULE_AUTHOR("David Jung <David.Jung@analog.com>"); 1056 MODULE_AUTHOR("Ibrahim Tilki <Ibrahim.Tilki@analog.com>"); 1057 MODULE_DESCRIPTION("Analog Devices MAX11410 ADC"); 1058 MODULE_LICENSE("GPL"); 1059