xref: /openbmc/linux/drivers/iio/adc/max1118.c (revision f746ab0b)
136edc939SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2a9e9c715SAkinobu Mita /*
3a9e9c715SAkinobu Mita  * MAX1117/MAX1118/MAX1119 8-bit, dual-channel ADCs driver
4a9e9c715SAkinobu Mita  *
5a9e9c715SAkinobu Mita  * Copyright (c) 2017 Akinobu Mita <akinobu.mita@gmail.com>
6a9e9c715SAkinobu Mita  *
7a9e9c715SAkinobu Mita  * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX1117-MAX1119.pdf
8a9e9c715SAkinobu Mita  *
9a9e9c715SAkinobu Mita  * SPI interface connections
10a9e9c715SAkinobu Mita  *
11a9e9c715SAkinobu Mita  * SPI                MAXIM
12a9e9c715SAkinobu Mita  * Master  Direction  MAX1117/8/9
13a9e9c715SAkinobu Mita  * ------  ---------  -----------
14a9e9c715SAkinobu Mita  * nCS        -->     CNVST
15a9e9c715SAkinobu Mita  * SCK        -->     SCLK
16a9e9c715SAkinobu Mita  * MISO       <--     DOUT
17a9e9c715SAkinobu Mita  * ------  ---------  -----------
18a9e9c715SAkinobu Mita  */
19a9e9c715SAkinobu Mita 
20a9e9c715SAkinobu Mita #include <linux/module.h>
211fa8b34aSJonathan Cameron #include <linux/mod_devicetable.h>
22a9e9c715SAkinobu Mita #include <linux/spi/spi.h>
23a9e9c715SAkinobu Mita #include <linux/iio/iio.h>
24a9e9c715SAkinobu Mita #include <linux/iio/buffer.h>
25a9e9c715SAkinobu Mita #include <linux/iio/triggered_buffer.h>
26a9e9c715SAkinobu Mita #include <linux/iio/trigger_consumer.h>
27a9e9c715SAkinobu Mita #include <linux/regulator/consumer.h>
28a9e9c715SAkinobu Mita 
29a9e9c715SAkinobu Mita enum max1118_id {
30a9e9c715SAkinobu Mita 	max1117,
31a9e9c715SAkinobu Mita 	max1118,
32a9e9c715SAkinobu Mita 	max1119,
33a9e9c715SAkinobu Mita };
34a9e9c715SAkinobu Mita 
35a9e9c715SAkinobu Mita struct max1118 {
36a9e9c715SAkinobu Mita 	struct spi_device *spi;
37a9e9c715SAkinobu Mita 	struct mutex lock;
38a9e9c715SAkinobu Mita 	struct regulator *reg;
39db8f06d9SJonathan Cameron 	/* Ensure natural alignment of buffer elements */
40db8f06d9SJonathan Cameron 	struct {
41db8f06d9SJonathan Cameron 		u8 channels[2];
42db8f06d9SJonathan Cameron 		s64 ts __aligned(8);
43db8f06d9SJonathan Cameron 	} scan;
44a9e9c715SAkinobu Mita 
45*f746ab0bSJonathan Cameron 	u8 data __aligned(IIO_DMA_MINALIGN);
46a9e9c715SAkinobu Mita };
47a9e9c715SAkinobu Mita 
48a9e9c715SAkinobu Mita #define MAX1118_CHANNEL(ch)						\
49a9e9c715SAkinobu Mita 	{								\
50a9e9c715SAkinobu Mita 		.type = IIO_VOLTAGE,					\
51a9e9c715SAkinobu Mita 		.indexed = 1,						\
52a9e9c715SAkinobu Mita 		.channel = (ch),					\
53a9e9c715SAkinobu Mita 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
54a9e9c715SAkinobu Mita 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
55a9e9c715SAkinobu Mita 		.scan_index = ch,					\
56a9e9c715SAkinobu Mita 		.scan_type = {						\
57a9e9c715SAkinobu Mita 			.sign = 'u',					\
58a9e9c715SAkinobu Mita 			.realbits = 8,					\
59a9e9c715SAkinobu Mita 			.storagebits = 8,				\
60a9e9c715SAkinobu Mita 		},							\
61a9e9c715SAkinobu Mita 	}
62a9e9c715SAkinobu Mita 
63a9e9c715SAkinobu Mita static const struct iio_chan_spec max1118_channels[] = {
64a9e9c715SAkinobu Mita 	MAX1118_CHANNEL(0),
65a9e9c715SAkinobu Mita 	MAX1118_CHANNEL(1),
66a9e9c715SAkinobu Mita 	IIO_CHAN_SOFT_TIMESTAMP(2),
67a9e9c715SAkinobu Mita };
68a9e9c715SAkinobu Mita 
max1118_read(struct iio_dev * indio_dev,int channel)693c43b6e1SJonathan Cameron static int max1118_read(struct iio_dev *indio_dev, int channel)
70a9e9c715SAkinobu Mita {
71a9e9c715SAkinobu Mita 	struct max1118 *adc = iio_priv(indio_dev);
72a9e9c715SAkinobu Mita 	struct spi_transfer xfers[] = {
73a9e9c715SAkinobu Mita 		/*
74a9e9c715SAkinobu Mita 		 * To select CH1 for conversion, CNVST pin must be brought high
75a9e9c715SAkinobu Mita 		 * and low for a second time.
76a9e9c715SAkinobu Mita 		 */
77a9e9c715SAkinobu Mita 		{
78a9e9c715SAkinobu Mita 			.len = 0,
795f0ea0f5SSergiu Cuciurean 			.delay = {	/* > CNVST Low Time 100 ns */
805f0ea0f5SSergiu Cuciurean 				.value = 1,
815f0ea0f5SSergiu Cuciurean 				.unit = SPI_DELAY_UNIT_USECS
825f0ea0f5SSergiu Cuciurean 			},
83a9e9c715SAkinobu Mita 			.cs_change = 1,
84a9e9c715SAkinobu Mita 		},
85a9e9c715SAkinobu Mita 		/*
86a9e9c715SAkinobu Mita 		 * The acquisition interval begins with the falling edge of
87a9e9c715SAkinobu Mita 		 * CNVST.  The total acquisition and conversion process takes
88a9e9c715SAkinobu Mita 		 * <7.5us.
89a9e9c715SAkinobu Mita 		 */
90a9e9c715SAkinobu Mita 		{
91a9e9c715SAkinobu Mita 			.len = 0,
925f0ea0f5SSergiu Cuciurean 			.delay = {
935f0ea0f5SSergiu Cuciurean 				.value = 8,
945f0ea0f5SSergiu Cuciurean 				.unit = SPI_DELAY_UNIT_USECS
955f0ea0f5SSergiu Cuciurean 			},
96a9e9c715SAkinobu Mita 		},
97a9e9c715SAkinobu Mita 		{
98a9e9c715SAkinobu Mita 			.rx_buf = &adc->data,
99a9e9c715SAkinobu Mita 			.len = 1,
100a9e9c715SAkinobu Mita 		},
101a9e9c715SAkinobu Mita 	};
102a9e9c715SAkinobu Mita 	int ret;
103a9e9c715SAkinobu Mita 
104a9e9c715SAkinobu Mita 	if (channel == 0)
1053c43b6e1SJonathan Cameron 		ret = spi_sync_transfer(adc->spi, xfers + 1, 2);
106a9e9c715SAkinobu Mita 	else
1073c43b6e1SJonathan Cameron 		ret = spi_sync_transfer(adc->spi, xfers, 3);
108a9e9c715SAkinobu Mita 
109a9e9c715SAkinobu Mita 	if (ret)
110a9e9c715SAkinobu Mita 		return ret;
111a9e9c715SAkinobu Mita 
112a9e9c715SAkinobu Mita 	return adc->data;
113a9e9c715SAkinobu Mita }
114a9e9c715SAkinobu Mita 
max1118_get_vref_mV(struct iio_dev * indio_dev)1153c43b6e1SJonathan Cameron static int max1118_get_vref_mV(struct iio_dev *indio_dev)
116a9e9c715SAkinobu Mita {
117a9e9c715SAkinobu Mita 	struct max1118 *adc = iio_priv(indio_dev);
1183c43b6e1SJonathan Cameron 	const struct spi_device_id *id = spi_get_device_id(adc->spi);
119a9e9c715SAkinobu Mita 	int vref_uV;
120a9e9c715SAkinobu Mita 
121a9e9c715SAkinobu Mita 	switch (id->driver_data) {
122a9e9c715SAkinobu Mita 	case max1117:
123a9e9c715SAkinobu Mita 		return 2048;
124a9e9c715SAkinobu Mita 	case max1119:
125a9e9c715SAkinobu Mita 		return 4096;
126a9e9c715SAkinobu Mita 	case max1118:
127a9e9c715SAkinobu Mita 		vref_uV = regulator_get_voltage(adc->reg);
128a9e9c715SAkinobu Mita 		if (vref_uV < 0)
129a9e9c715SAkinobu Mita 			return vref_uV;
130a9e9c715SAkinobu Mita 		return vref_uV / 1000;
131a9e9c715SAkinobu Mita 	}
132a9e9c715SAkinobu Mita 
133a9e9c715SAkinobu Mita 	return -ENODEV;
134a9e9c715SAkinobu Mita }
135a9e9c715SAkinobu Mita 
max1118_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)136a9e9c715SAkinobu Mita static int max1118_read_raw(struct iio_dev *indio_dev,
137a9e9c715SAkinobu Mita 			struct iio_chan_spec const *chan,
138a9e9c715SAkinobu Mita 			int *val, int *val2, long mask)
139a9e9c715SAkinobu Mita {
140a9e9c715SAkinobu Mita 	struct max1118 *adc = iio_priv(indio_dev);
141a9e9c715SAkinobu Mita 
142a9e9c715SAkinobu Mita 	switch (mask) {
143a9e9c715SAkinobu Mita 	case IIO_CHAN_INFO_RAW:
144a9e9c715SAkinobu Mita 		mutex_lock(&adc->lock);
1453c43b6e1SJonathan Cameron 		*val = max1118_read(indio_dev, chan->channel);
146a9e9c715SAkinobu Mita 		mutex_unlock(&adc->lock);
147a9e9c715SAkinobu Mita 		if (*val < 0)
148a9e9c715SAkinobu Mita 			return *val;
149a9e9c715SAkinobu Mita 
150a9e9c715SAkinobu Mita 		return IIO_VAL_INT;
151a9e9c715SAkinobu Mita 	case IIO_CHAN_INFO_SCALE:
1523c43b6e1SJonathan Cameron 		*val = max1118_get_vref_mV(indio_dev);
153a9e9c715SAkinobu Mita 		if (*val < 0)
154a9e9c715SAkinobu Mita 			return *val;
155a9e9c715SAkinobu Mita 		*val2 = 8;
156a9e9c715SAkinobu Mita 
157a9e9c715SAkinobu Mita 		return IIO_VAL_FRACTIONAL_LOG2;
158a9e9c715SAkinobu Mita 	}
159a9e9c715SAkinobu Mita 
160a9e9c715SAkinobu Mita 	return -EINVAL;
161a9e9c715SAkinobu Mita }
162a9e9c715SAkinobu Mita 
163a9e9c715SAkinobu Mita static const struct iio_info max1118_info = {
164a9e9c715SAkinobu Mita 	.read_raw = max1118_read_raw,
165a9e9c715SAkinobu Mita };
166a9e9c715SAkinobu Mita 
max1118_trigger_handler(int irq,void * p)167a9e9c715SAkinobu Mita static irqreturn_t max1118_trigger_handler(int irq, void *p)
168a9e9c715SAkinobu Mita {
169a9e9c715SAkinobu Mita 	struct iio_poll_func *pf = p;
170a9e9c715SAkinobu Mita 	struct iio_dev *indio_dev = pf->indio_dev;
171a9e9c715SAkinobu Mita 	struct max1118 *adc = iio_priv(indio_dev);
172a9e9c715SAkinobu Mita 	int scan_index;
173a9e9c715SAkinobu Mita 	int i = 0;
174a9e9c715SAkinobu Mita 
175a9e9c715SAkinobu Mita 	mutex_lock(&adc->lock);
176a9e9c715SAkinobu Mita 
177a9e9c715SAkinobu Mita 	for_each_set_bit(scan_index, indio_dev->active_scan_mask,
178a9e9c715SAkinobu Mita 			indio_dev->masklength) {
179a9e9c715SAkinobu Mita 		const struct iio_chan_spec *scan_chan =
180a9e9c715SAkinobu Mita 				&indio_dev->channels[scan_index];
1813c43b6e1SJonathan Cameron 		int ret = max1118_read(indio_dev, scan_chan->channel);
182a9e9c715SAkinobu Mita 
183a9e9c715SAkinobu Mita 		if (ret < 0) {
184a9e9c715SAkinobu Mita 			dev_warn(&adc->spi->dev,
185a9e9c715SAkinobu Mita 				"failed to get conversion data\n");
186a9e9c715SAkinobu Mita 			goto out;
187a9e9c715SAkinobu Mita 		}
188a9e9c715SAkinobu Mita 
189db8f06d9SJonathan Cameron 		adc->scan.channels[i] = ret;
190a9e9c715SAkinobu Mita 		i++;
191a9e9c715SAkinobu Mita 	}
192db8f06d9SJonathan Cameron 	iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
193a9e9c715SAkinobu Mita 					   iio_get_time_ns(indio_dev));
194a9e9c715SAkinobu Mita out:
195a9e9c715SAkinobu Mita 	mutex_unlock(&adc->lock);
196a9e9c715SAkinobu Mita 
197a9e9c715SAkinobu Mita 	iio_trigger_notify_done(indio_dev->trig);
198a9e9c715SAkinobu Mita 
199a9e9c715SAkinobu Mita 	return IRQ_HANDLED;
200a9e9c715SAkinobu Mita }
201a9e9c715SAkinobu Mita 
max1118_reg_disable(void * reg)20230b527ddSJonathan Cameron static void max1118_reg_disable(void *reg)
20330b527ddSJonathan Cameron {
20430b527ddSJonathan Cameron 	regulator_disable(reg);
20530b527ddSJonathan Cameron }
20630b527ddSJonathan Cameron 
max1118_probe(struct spi_device * spi)207a9e9c715SAkinobu Mita static int max1118_probe(struct spi_device *spi)
208a9e9c715SAkinobu Mita {
209a9e9c715SAkinobu Mita 	struct iio_dev *indio_dev;
210a9e9c715SAkinobu Mita 	struct max1118 *adc;
211a9e9c715SAkinobu Mita 	const struct spi_device_id *id = spi_get_device_id(spi);
212a9e9c715SAkinobu Mita 	int ret;
213a9e9c715SAkinobu Mita 
214a9e9c715SAkinobu Mita 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
215a9e9c715SAkinobu Mita 	if (!indio_dev)
216a9e9c715SAkinobu Mita 		return -ENOMEM;
217a9e9c715SAkinobu Mita 
218a9e9c715SAkinobu Mita 	adc = iio_priv(indio_dev);
219a9e9c715SAkinobu Mita 	adc->spi = spi;
220a9e9c715SAkinobu Mita 	mutex_init(&adc->lock);
221a9e9c715SAkinobu Mita 
222a9e9c715SAkinobu Mita 	if (id->driver_data == max1118) {
223a9e9c715SAkinobu Mita 		adc->reg = devm_regulator_get(&spi->dev, "vref");
2249444794bSCai Huoqing 		if (IS_ERR(adc->reg))
2259444794bSCai Huoqing 			return dev_err_probe(&spi->dev, PTR_ERR(adc->reg),
2269444794bSCai Huoqing 					     "failed to get vref regulator\n");
227a9e9c715SAkinobu Mita 		ret = regulator_enable(adc->reg);
228a9e9c715SAkinobu Mita 		if (ret)
229a9e9c715SAkinobu Mita 			return ret;
23030b527ddSJonathan Cameron 
23130b527ddSJonathan Cameron 		ret = devm_add_action_or_reset(&spi->dev, max1118_reg_disable,
23230b527ddSJonathan Cameron 					       adc->reg);
23330b527ddSJonathan Cameron 		if (ret)
23430b527ddSJonathan Cameron 			return ret;
23530b527ddSJonathan Cameron 
236a9e9c715SAkinobu Mita 	}
237a9e9c715SAkinobu Mita 
238a9e9c715SAkinobu Mita 	indio_dev->name = spi_get_device_id(spi)->name;
239a9e9c715SAkinobu Mita 	indio_dev->info = &max1118_info;
240a9e9c715SAkinobu Mita 	indio_dev->modes = INDIO_DIRECT_MODE;
241a9e9c715SAkinobu Mita 	indio_dev->channels = max1118_channels;
242a9e9c715SAkinobu Mita 	indio_dev->num_channels = ARRAY_SIZE(max1118_channels);
243a9e9c715SAkinobu Mita 
244a9e9c715SAkinobu Mita 	/*
245a9e9c715SAkinobu Mita 	 * To reinitiate a conversion on CH0, it is necessary to allow for a
246a9e9c715SAkinobu Mita 	 * conversion to be complete and all of the data to be read out.  Once
247a9e9c715SAkinobu Mita 	 * a conversion has been completed, the MAX1117/MAX1118/MAX1119 will go
248a9e9c715SAkinobu Mita 	 * into AutoShutdown mode until the next conversion is initiated.
249a9e9c715SAkinobu Mita 	 */
2503c43b6e1SJonathan Cameron 	max1118_read(indio_dev, 0);
251a9e9c715SAkinobu Mita 
25230b527ddSJonathan Cameron 	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
253a9e9c715SAkinobu Mita 					      max1118_trigger_handler, NULL);
254a9e9c715SAkinobu Mita 	if (ret)
255a9e9c715SAkinobu Mita 		return ret;
256a9e9c715SAkinobu Mita 
25730b527ddSJonathan Cameron 	return devm_iio_device_register(&spi->dev, indio_dev);
258a9e9c715SAkinobu Mita }
259a9e9c715SAkinobu Mita 
260a9e9c715SAkinobu Mita static const struct spi_device_id max1118_id[] = {
261a9e9c715SAkinobu Mita 	{ "max1117", max1117 },
262a9e9c715SAkinobu Mita 	{ "max1118", max1118 },
263a9e9c715SAkinobu Mita 	{ "max1119", max1119 },
264a9e9c715SAkinobu Mita 	{}
265a9e9c715SAkinobu Mita };
266a9e9c715SAkinobu Mita MODULE_DEVICE_TABLE(spi, max1118_id);
267a9e9c715SAkinobu Mita 
268a9e9c715SAkinobu Mita static const struct of_device_id max1118_dt_ids[] = {
269a9e9c715SAkinobu Mita 	{ .compatible = "maxim,max1117" },
270a9e9c715SAkinobu Mita 	{ .compatible = "maxim,max1118" },
271a9e9c715SAkinobu Mita 	{ .compatible = "maxim,max1119" },
272a9e9c715SAkinobu Mita 	{},
273a9e9c715SAkinobu Mita };
274a9e9c715SAkinobu Mita MODULE_DEVICE_TABLE(of, max1118_dt_ids);
275a9e9c715SAkinobu Mita 
276a9e9c715SAkinobu Mita static struct spi_driver max1118_spi_driver = {
277a9e9c715SAkinobu Mita 	.driver = {
278a9e9c715SAkinobu Mita 		.name = "max1118",
2791fa8b34aSJonathan Cameron 		.of_match_table = max1118_dt_ids,
280a9e9c715SAkinobu Mita 	},
281a9e9c715SAkinobu Mita 	.probe = max1118_probe,
282a9e9c715SAkinobu Mita 	.id_table = max1118_id,
283a9e9c715SAkinobu Mita };
284a9e9c715SAkinobu Mita module_spi_driver(max1118_spi_driver);
285a9e9c715SAkinobu Mita 
286a9e9c715SAkinobu Mita MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
287a9e9c715SAkinobu Mita MODULE_DESCRIPTION("MAXIM MAX1117/MAX1118/MAX1119 ADCs driver");
288a9e9c715SAkinobu Mita MODULE_LICENSE("GPL v2");
289